a high precision micropower operational amplifier

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1048 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979

memory array interface, the observed performance is vastly

superior to that seen in l ine-addressed versions.

ACKNOWLEDGMENT

The author gratefully acknowledges the guidance and en-

couragement of D. D. Buss and W. H. Bailey and the technical

assistance of P. L. Ham.

[1]

[2]

[3]

[4]

[5]

REFERENCES

W. L. Eversole, D. J. Mayer, P. W. Bosshart, M. deWitt, C. R.Hewes, and D. D. Buss, “A completely integrated thirty-two point

chirp Z transform,” IEEE J. Solid-State Ctrcuits, vol. SC-13, pp.822-831, Dec. 1978.D. J. Mayer, W. L. Eversole, C. R. Hewes,and H. F. Benz, “Aprogrammable CCD correlator for pattern classif icat ion,” pre-sentedat the SPIETech. Symp.,Washington,DC, Apr. 1979.J. B. G. Roberts, R. Eames,and R. F. Simons,“A CCD SAWpro-cessorfor pulseDoppler radarsignals,”in Proc. 1975 Int. Cbnf on

the Application of C7rarge Cbupled Devices, San Diego, CA, Oct.1975, pp. 295-300.J. B. G. Roberts, R. Eames, D. V. McCaughan, and R. F. Simons,

“A processor for pulse-Doppler radar,” IEEE J. Solid-State C7r-

cuits, vol. SC-11, pp. 100-104, Feb. 1976.R. J. Kansy, R. C. Bennett, W. H. Bailey, and L. H. Ragan, “An

analog Doppler processor using CCD and SWD technologies,;’ in

[6]

[7]

[8]

1977 Ultrasonics Symp. Proc., IEEE Cat. 77CH1264-ISU, pp.

952-956.

W. H. Bailey, R. J. Kansy, R. A. Kempf, R. C. Bennet, and J. L.Owens, “A complementary CCD/SAW radar signal processor,” inProc. 1978 Int. Conf on the Application of Charge Coupled

Devices, San Diego, CA, Oct. 1978, pp. 3B-41-3B-52.

C. H. Sequin, “Two dimensional charge transfer arrays,” IEEE J.

Solid-State (lrcults, vol. SC-9, pp. 134-142, June 1974.W. L. EverSole, I). J. Mayer, and R. J. Kansy, “A CCD two-dimens-

ional transform,” in Proc. 1978 Irrt. Cbnf, on the Application of

Charge Coupled Devices, San Diego, CA, Oct. 1978, pp. 3B-31-3B-40.

Robert J. Kansy (S’68-M’70) was born inSpringf ield, IL, on June 9, 1947. He receivedthe B.S., M.S., and Ph.D. degreesin electricalengineering from the University of Illinois,Urbana,in 1970, 1971, and 1975, respectively.In 1974 he joined Magnavox, Ft. Wayne, IN,

where he was involved with the designand ap-plication of surfaceacoustic wavedevices. Hejoined TexasInstruments Incorporated, DaBas,in 1976 where he has been engaged in the de-velopment of MOS and CCD integrated circuits.

A member of the Advanced Technology Laboratory in the EquipmentGroup, his current interests iuclude the development of analog signalprocessors for infrared imaging and radar systems.

A High Precision Micropower Operational Amplifier

KIYOSHI FUKAHORI, MEMBER, lEEE, YUKIO NISHIKAWA, MEMBER, IEEE,

AND ADIB R. HAMADE’, MEMBER, IEEE

Abstract -Described is an operational ampli fier configurat ion imple-

mented as a true micropower high precision OPamp. It includes a wel l

controlled and predictable dc biasing network that is insensitive to

variations in temperature, supply voltages, and process. Also, it permits

single supply operation. Excelfent dc precision characteristics, compar-

able to or better than the very best precision op ampscurrently available,

are real ized yet at micropower levels. By simply increasing the biasing

currents, a version of this design operates in generaf purpose applications

without any degradation in its high precision characteristics. Thus, the

ac performance levels of generaJ purpose op amps are attained at a

fraction of supply current. This device is fabricated using a standard

bipolar IC process; an ion-implanted JFET is added to simplify biasing.

I. INTRODUCTION

sINCE the advent of the 709 monolithic operational ampli-

fier (op amp) [1] nearly 15 years ago, a large number of

different op amps have followed with some finding wide usage.

They have ranged from general purpose types introduced in

Manuscript received April 12, 1979; revised July 15, 1979.The authors are with Precision Monolithic, Inc., Santa Clara, CA

95050.

1967 [2] to more special purpose types which are still beingintroduced today [3] .

This paper describes the design of a true micropower high

precision op amp Although this op amp is a special purpose

device, its design demonstrates that high precis ion character-

istics do not necessarily have to be sacrificed to attain micro-

power operation. A variety of micropower op amps have been

designed [4] - [15] , but most have gained limited acceptance,

The majority are general purpose designs biased down to

micropower levels, and consequently, they have retained many

of the limitations while introducing others. To be a true

micropower and high precision op amp, it must possess the

following characteristics:

1) a well controlled and predictable supply current in the

low microampere range that is insensitive to variations in

supply voltage, ambient temperature, and process;

2) flexibility y of operation from a single low supply voltage;

3) inherent high precision with low offset voltage (Vo.), low

offset drift (TCJ’ ), low input bias current (lB), low input off-

set current (10~), hi@ open loop gain (Avol), high common-

mode rejection ratio (CMRR), and high power supply rejec-

tion ratio (PSRR);

0018 -9200/79 /1200-1048 00.75 @ 1979 IEEE



FUKAHORI et al.: PRECISION MICROPOWER OP AMP

4) moderate bandwidth and slew rate commensurate with

supply current.

The micropower op amp [16] described here possesses all

of these characteristics. Also, this circuit configuraticrn allows

the quiescent biasing currents to be easily increased to attain

general purpose op amp performance without degradation of

i ts high precision character ist ics.

Design activities in bipolar op amps have been decreasing in

recent years due to the limitations of the standard IC process.

In this paper, many of these limitations are examineci to show

how this op amp configuration evolved and why it has both

high precision and micropower characteristics. S?ction II

describes the dc biasing schemes; by incorporating, an ion-

impkmted JFET into the design of the biasing circuit, a

major micropower limitation will be shown to hwe been

circumvented. Section III examines various input stages and

describes why a Darlington p-n-p input stage with a balanced

second stage was chosen for single supply operation and for

precision performance. Section IV covers the selection of

an output stage suitable for micropower levels. %ction V

reports the performance and experiment al results obtained

from thk design.

II. BIASING

The dc biasing network for a micropower op amp nnust pro-

vide precisely determined and well regulated quiescent biasing

currents at low microampere levels. This current must be in-

sensitive to process tolerances and to changes in temperature

and supply voltages. Various bias schemes have been im-

plemented in the past, but each have some major limitations

for micropower operat ions.

A. Traditional Br ining Techniques

Four most commorily used biasing schemes are shown in

Fig. 1. The use of the epi-FET [2] as shown in Fig. l(a) is

a simple biasing method which does not need any additional

processing steps. Since the epi-FET has ahigh pinch-off voltage

(>20 V), it will be prohibitively large to attain the large re-

sistance needed below saturat ion to realize the small currents

for low voltage operation.

A more direct approach [see Fig. l(b)] uses a resistor in

series with diodes across the power supply terminals [17] -

[19] . However, the resistor approaches allow the biasing

currents to vary directly with power supply voltages to un-

acceptably high currents at high voltages. To avoid that

problem the resistor is placed external to the op amp [see

Fig. l(c)] . By choosing the resistor value, the desired biasing

currents are set. These programmable op amps permit adjust-

ment of the biasing currents for each application. However,

when flexibility is weighed against simplicity, the users tend to

choose simplicity; e.g., the 741 with fixed compensation has

found wider usage than its predecessor, the 101 with external

compensation. Hence, the design with internal micropower

biasing is preferred.

To obtain the very low currents without the power supply

sensitivity of large resistors, a complementary pair of current

sources in a loop [see Fig. 1(d)] hasbeen integrated [11] , [20] .

Unfortunately, the circuit has two stable states: one state is at

T

B i

PI-FET

I

IOUT

(a)

EXTERNALRESISTOR

j 10.1

(c)

1049

W,0”,,BASE

RESISTOR

J _

10”,2

(b)

(d)

Fig. 1. Traditional biasing techniques used in op amps. (a) Epi-FET

biasing. It suffers from wide current variations. (b) Resistor biasing.Bias current varies with supply voltage. (c) ExternaJ resistor biasing.The value of the external resistor becomes excessively large for small

currents. (d) Latching current source biasing. It requi res a start -up

circuit.

IT w’1~CWT

(a) (b)

Fig 2. Ion-implanted JFET that provides low microampere current, buthas wide current variations. (a) Simple JFET current source withIout = IDSS. (b) A bet ter regulated JFET current source.

the desired operating point and the other is at zero current.

Since neither leakage currents nor fast power supply voltage

rise can be relied on for turn-on, additional circuitry is required

which consumes area aswell aspower.

B. Micropower Biasing

This design adopts a different approach to realize a reliable

and efficient scheme to set a low microampere current. A

compatible and widely used ion-implanted p-channel JFET

[21 ] - [25] is used. It is very small in area, has greatly reduced

power supply voltage sensitivity, and does not have any start-

up problems. However, it cannot be used directly asa current

source [see Fig. 2(a)] because its saturation drain current

(ZDSS) is sensitive to process and temperature variations, and

it is not as welt controlled as desired. Although this problem

could be reduced by adding a resistor [25] at the source of

the JFET, as shown in Fig. 2(b), better regulation is’ still

needed.

Variations of IDSS can be greatly reduced by running the

JFET current through a regulator as shown in Fig. 3(a). Its

transfer characteristics, shown in Fig. 3(b), has a maxima, and




v+

i

Ii

i10

v-

(a)

051=I=l=cI=I=I=lR3=26K

T=25-C

0.3

\\~_

~

_.

0,2

/

0.1 /

/

I

0 ~~0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Ii ( A)

(b)

Fig. 3. The peaking current source which holds 10 relatively constant with respect to It (a) The circuit schematic of the

peaking current source fed from a JFET current source. (b) Transfer characterist ic wi th a peak that depends on R 3.

hence, it is called “peaking current source” [26]. This peaking

behavior can easily be seen. When the input current ~ is small,

voltage drop ~R 3 is negligible and the transfer of ~ to 10, the

output current, is linear. As ~ increases, AR3 subtracts from

V of Q32, and a reduced voltage is applied to drive Q33 re-

ducing 10. When ~R3 becomes large, Q33 is nearly shut off.

By examining the behavior of this regulator quantitatively its

usefulness in a design of micropower op amp can be seen. 10

can be easily derived to be

R310=~exp -—

VT ‘(1)

where VT = kT/q is a thermal voltage at temperature T(K).

Infinite current gain (~) and identical characteristics for both

Q32 and Q33 are assumed. Fig. 3(b) is a plot of (l), and, as

can be seen, the sensitivity of 10 to ~ is reduced to O at the

peak. I , peak or maximum value of 10, and its corresponding

Iin, are determined directly from ( 1), and these are

and

1+. ~mI =—–=—.0mR3e e

Consequently,

(2)

(3)

(4)

The ratio of peak currents in (4) can be scaled up or down by

changing the emitter area ratio of Q32 and Q33.

By normalizing 10 to the maximum value {Om and expressing

it in terms of multiples f14of ~m,

NORMALIZE INPUT CURRENT (M)

Fig. 4. Normal ized transfer characteristics of the peaking current source

for a single stage, curve a, and for two cascaded stages to further

improve regulation, curve b.

where

Curve a in Fig. 4. is a plot of (5). For +50 to -40 percent

change in input current, to is regulated to within 10 percent.

The transistor current gain (~) dependen~e of the peaking

current source is found by including the effect of finite base

currents of Q32 and Q33. The output current is given by

~ = –eMe-~

Iom(6)



FUKAHORI et al.: PRECISION MICROPOWER OP AMP 1051

1.2 v+

1,0

c

I IN4

0.8

0F

5 0.6

7

~

1-

0.4v-

Fig. 7. A current source formed by cascadingtwo peaking currentsource stagesto improve regulation of ~out.

0.2

Similarity, sensitivity of 10 to temperature is found to be

01 2 2,5 3.3 5.0 10 20 25 33 50 100

(T R3 ~T) ‘9)+~=~ (l-M)+M 2-l W

CURF IENT GAIN (P)

Fig. 5. Dependenceof the transfer characteristics on current gain P’forz

a simple current source, curve a, peakingcurrent source,curveb, and At the peak lkf = 1, andpeakingcurrent sourcewith a compensationresistor, curve c.

,’

;()1 MOm 1 1 dR3—— .— - ——~m dT TR3aT”

(10)

&

/1,.Thus, Ion has a reduced temperature coefficient resulting from

the difference of two terms. Since 1IT > aR3/R3aT for a

R3~ 10UT

typical base-diffused resistor, Iom shows a slight posit ive tem-

Rz = R3/e perature coefficient. At high temperatures the regulation isQ 3,

quite good while at low temperatures it is slightly degraded.

032 Current regulation can be further improved by cascading two

peaking current sources as shown in Fig. 7, and its transferv-

characteristics are plotted as curve b in Fig. 4. As can be seenFig. 6. Peaking current source with R 2 to compensate for (3. 10 changes by only 2 percent for a t50 percent variation in 1;.

Its sensitivity to changes inR is about the same as a single stage

The solution of this equation, with Z. normalized to IOm regulator while its temperature sensitivityy is slightly worse.

(IJ = CO),is plotted in Fig. 5. It can be seen that the peaking Also, better control of the absolute value of R3 can be realized

current source is lesssensit ive to B than a simple current source. by using a trim technique [27].

Also, by adding R2 =R3/e (Fig. 6), the sensitivity to Pcan be This JFET/peaking current source arrangement provides a

further reduced. In this case, predictable and consistent dc biasing current for low micro-

(

O_ 6

)

ampere operation. It has a low sensitivity to process and

1’= ~~-~”p+ltemperature variations. By simply changing the values of both

the IDSS and R3 the op amp can be biased for a higher slew

{ ‘[

R3 b-: 1-:

1}rate and a wider bandwidth. This dc biasing scheme is a useful

building block for various types of analog integrated circuits. exp —+10— (7)

-—~io+lT W+ 1) “and is easily implemented since the ion-implanted JFET can

be easily added to the standard bipolar process. Hence, theThe normalized solution of (7) is plotted as curve c in Fig. 5.

If/3 is low, then its error contributions will be reduced by R2.inclusion of this JFET allows micropower design character-

The sensitivity of 10 to R3 is found from (1) to be

ist ics heretofore not easi ly attained.

aIO _ aR3III. INPUT STAGE CONFIGURATIONS

—-- M— (8) The configuration of the input stage determines the precision10 R3 .

characteristics of all op amps. It also dictates if the op amp

At the peak, ill= 1 and can be used in a single supply applicat ion. With recent advance-

aIom aR3ments in process technology, it is possible to realize an input

=—z R3 “

stage configuration with the fol lowing characteristics:om 1) high precision defiied by low J&,” low TCVo~, low lB,

The peak value will vary directly with R3. However, 10 will low Io~; high input impedance, high CMRR, and high PSRR;

still be well regulated, although it will be more sensitive to 2) high gain so that two stagesw ill provide sufficiently high

variations in ~.. overall open loop gain for the op amp;




v+

(1

v-

V.

N

1 1

v-

V+

t,,.s

v-

(a) (b) (c)

Fig. 8. Common n-p-n input stages in earlv op amps. (a) A simple resist ively-loaded n-p-n stage. It has high precision

characteristics, but suffers from Zener breakdown. (b) High gain active load stage with protection. Its input impedance

changes wi th large input vol tages. (c) Unique n-p-n/p-n-p stagethat does not allow single supply operation.

v. v+

B’ Ii : w :?

v.

1 1 1 1 1 1 1

v-

v- v- Y

(a) (b) (c)

Fig. 9. Common p-n-p input stages. (a) Actively-loaded input stage that has inherent imbalances. (b) Input stage with the

active load sensing. (c) Darlington input stage that allows single supply operation.

3) ability to withstand large input differential voltage with-

out long-term deterioration of performance of the op amp;

4) its common-inode input range includes negative powersupply volt age for single supply operation.

A. Common Input Stages

In early monolithic op amp designs, input stages predomi-

nantly used n-p-n transistors due to their high current gains.

A resistively-loaded n-p-n differential pair [see Fig. 8(a)] has ex-

cellent higli precision characteristics [28] due to its simplicity,

but the ‘ p ransistors break down when a large differential

voltage is applied. This occurs when the op amp slews to’ follow

a fast signal [29]. A deterioration of current gain occurs each

time the transistor is Zenered [30] , and eventually ‘current

gain becomes so low and the input pair becomes so mismatched

that the lB, Io~, J , and ‘TCVo~ of the op amp become prohibi-

tively large. Also, the use of the resistive loads forces a low in-

put stage gain to insure adequate input common-mode range.

Consequently, three gain stages are needed to attain adequate

op. amp gain, and such a circuit is difficult” to frequency-

compensate. The use of a simple current mirror active load

with n-p-n input stages [see Fig. 8(b)] provides ‘high gains

without compromising input common-mode range. However,

this configuration does not have the high precision of the re-

sistive load due to the inherent imbalances of the differential-

to-single-ended c’onversion~ For protection agajnst breakdown

of the n-p-n transistors, two diodes and two resistors are added

across the input terminals, but the input impedance drops

during large different input signals. A unique n-p-n/p-n-p

input stage structure [2], shown in Fig. 8(c), evolved to pro-vide the needed protection by using high breakdown lateral

p-n-p transistors to stand off the large differential input volt-

ages. However, a serious drawback of all n-p-n input stages i s

that single supply operations are not possible. The simple

lateral p-n-p input stage [14] [see Fig. 9(a)] came into usage

when improved process techniques raised their current gains to

acceptable levels. Precision was improved incrementally by

adding another emitter follower [9] [see Fig. 9(b)] to balance

the sensing of the active load. By using a Darlingt on pair

[see Fig. 9(c)] single supply operation was realized [31] .

Compatible bipolar/JFET and bipolar/MOSFET devices

[32] are commonplace. The needed devices are easily added

as was done for tlhe micropowcr dc biasing network described

above. Used as input devices they offer great improvement

[33] of slew rate, input impedance, and input bias current.

However, they do not match well [34] ; they also have high

1/f noise [35 ] anc~self-heat [23] , making it difficult to achieve

a high precision irnput stage.

B. High Precision Input Stage

In order to avoicl the drawbacks discussed above and to achieve

a high precision and single supply operation, a Darlington p-n-p

input stage in conjunction with completely balanced n-p-n

active load is used as shown in Fig. 10. The input transistors



FUKAHORIetal.: PRECISION MICROPOWEROP AMP

T—–—–. -–- —–—_____T1 I v+

IQ37

I

vBlbS1 /Io

k I

I I

~{ ,,4” ‘“ ~ 2,0 I 8–l-l

L—_. .———————.——A

Fig. 10. High precision iuput stage that uses balanced active loads and

eliminates iuherent sources of Vo~.

Q3 and Q4 are vertical p-n-p’s with high current gain for low

input bias current and high breakdown for large differential

volt,age protection. These devices are biased from current

source Q38 to insure good slew characteristics. They drive the

lateral p-n-p differential pair Q1 and Q2 which in turn feeds

identical collector active loads Q5 and Q6, respectively. Both

Q5 and Q6 are degenerated to reduce noise and offset [35].

The collector-base voltage of Q5 and Q6 are clamped near OV

by the symmetrical second stage. Q7 and Q8 buffer the dif-

ferential pair Q9 and Q1O to insure high input stage gain and

set the active load collectors 1 V~E above the negative supply

voltage to allow single supply operation. As can be seen, the

input stage is perfectly balanced so that high precision is in-

herently designed in. Imbalances of the second stage caused

by differences in VCE of Q9 and Q1O and by the diffisrential-

to-single-ended conversion ofQ11 are divided by the high in-

put stage gain when referred to the input; therefore, those im-

balances do not signif icantly affect the input stage balance.

Since the collectors of Q1 and Q2 are directly connected to

those of Q5 and Q6, respectively, a localized common-mode

feedback loop, composed of Q7/Q8 and Q9/QIO, is used to

adjust the currents in the active loads, thus, establishing the

proper operating bias [21 ] . Since this loop is a shunt feedback

in form, the common-mode load as seen by Q1/Q2 is reduced

by the common-mode loop gain. This loop gain is essentially

equal to the voltage gain of the common emitter Q5/Q6 stage

and is approximately 2000. Hence, CMRR of the op amp is

greatly improved. Differential ,ac signals are rejected lbecause

the emitters of Q9 and Q 10 are at virtual ground for, such

signals. Because of its high gain, this common-mode feedbackloop is compensated to insure stable operation. Pole splitting

capacitor C2 [33] , which compensates the complete clp amp,

acts to stabilize the common-mode loop by making the collector

of Q1O appear as a virtual ground. Equal valued capacitor Cl,

placed across the collector of Q5 and the negative supply,

balances the other half of the loop. Hence, each hall-of the

common-mode loop is rolled off identically resulting in superior

CMRR as well as PSRR over frequency. A pole and zero pair,

a doublet, created by Cl at about 100 Hz, is separated by an

octave. This separation is compressed by a factor equal to the

1053

closed loop gain of the op amp at the doublet frequency when

the op amp is used in a closed loop configuration, and con-

sequently, it does not affect the step response [36].

Great care was taken in the layout of this op amp to minimize

the total offset voltage: The input transistors QI through Q4

are laid out in the cross-coupled quad fashion to reduce the

effects of thermal and process gradients. Current sources for

Q3 and Q4 are made by a p-n-p transistor whose collectors

are split into identical halves. Resistors RE and l? at the

emitters of Q5 and Q6 are well matched; they ‘provide a way

for offset adjustment. Since the perfectly balanced input

stage circuit design insures that there are no inherent offset

voltage sources, the offset volt agescome only from mismatches

induced by the fabrication process.

To examine the effects of these mismatches, five offset

voltage sources are considered. These are

where CPIZ, CPM, EAB; en, and CR are mismatches between Q1

and Q2, Q3 and Q4, IIA and IIB, Q5 and Q6, and RE and R~,

respectively. Transconductance gm of the input stage is equai

to l./ VT. Total offset voltage is

where

Ifgm >>1, then

11)

12)

In order to minimize the offset voltage,RE and R are trimmed

by using Zener-zapping [27] such that

13)

Thus, offset volt age contribution of the first four sources are

nulled by deliberately unbalancing RE and R such that 13)

is satisfied.

The drift of VO~s found by differentiating 12) with respect

to temperature. Then,

14)

For the trimmed case, substitution of 13) in 14) results in

15)




A

k-d+OUT t., ,,

~ r.2-

Q,Qe

v BIAS

~

Fig. 11. A simplified active load stage.

Comparison of 14) and 15) shows that offset trimming re-

duces the P as well as drift. Also, the offset voltage drift is

nearly proportional to en, the mismatch between Q5 and Q6.

That is, when the active load emitter degeneration resistors are

trimmed for low offset voltage, the drift of V of the input

stages is directly dependent upon the matching of the active

load transistors. This differs from resistively-loaded input

stages in which trimming for VO.= O assures TCVO~= O [37].)

For this reason active load transistors Q5 and Q6 are split

into two devices each and laid out in cross-coupled quad

fashion to insure minimum en.

When the temperature dependence of 10 as derived in 1 O) is

substituted in 15), TCVO~= O results. Obviously, in a real op

amp, this is difficult to achieve consistently. Nevertheless, it

shows that this input stage design inherently possesses an ex-

tremely low offset voltage drift characteristic.

The very high open loop gain of this op amp is obtained by

using two active load stages whose output impedance is

preserved by double buffering. Q7 and Q8 buffer the input

stage active loads from the second stage driver Q9 and Q1O.

The double complementary output stage isolates the second

active load from the op amp load thereby making the second

gain stage insensitive to external load variation. For this op

amp, therefore, the open loop gain is very high. Gain X for

each active load stage Fig. 11) is

A.O = gmrO 16)

where

[0A = — and ro = rol lln32lri = rdh

VT

since

rol, roz << n“.

The output resistances, rol of p-n-p transistors and roz of n-p-n

transistors, are

v~p v~~rol = —— and roz = —

10 10 ‘ 17)

where VAP and VAN are the Early voltages of p-n-p and n-p-n

devices, respectively. If

VAN ‘ VAF = VA ,

then

18)

Therefore, the maximum gain available from a single active

load stage, of Fig. 11 type, is limited to the ratio of Early

voltage to thermal voltage regardless of operating current

levels. Attempts to raise AVOhigher than this ratio are diff icult.Typically, VA = 100 V, and AUO= 2000 per stage is attainable.

So the maximum gain available from two stages is limited to

about 4 X 106, but at such a high voltage gain, thermal effects

on the die become dominant making it virtually impossible to

distinguish higher voltage gai [33] . Hence, any added com-

ponents or circuitry is difficult to justify. The voltage gain of

this op amp approaches the maximum value.

IV. MICROPOWER OUTPUT STAGE

Perhaps one of the stages that causes the greatest problems

for the users and, therefore, the manufacturers, is the output

stage of micropower op amps. It must provide sufficient out-

put drive capability while quiescently consuming as little poweras possible. The output stage must possess the following

characteristics

1) predictably small and well controlled idle current for

minimum power dissipation and maximum efficiency;

2) ability to drive an adequate external load in both positive

and negative directions equally;

3) buffering capability of the previous gain stage from the

effects of the external load.

A simple Class A output stage [see Fig. 12 a)] an emitter

follower) has a weU controlled current. But it can only source

large currents in on~edirection, and it allows the load to greatly

lower the gain of the op amp. A starved down asymmetrical

Class All output stage [see Fig. 12 b)] can sink and source the

desired currents, but i t may introduce crossover distortion when

the operating point is shifted by process variables or by changes

in temperature andl supply voltages.

This micropower op amp uses the symmetrical and comple-

mentary Class All [38] output stage [see Fig. 12 c)] . It pro-

vides adequate drive capability at low biasing currents and is

free of crossover distortion. It consists of two cascaded emitter

follower stages in parallel; one stage is composed of Q26, II,

and Q29 while the other is composed of Q27, 12, and Q28.

Since both Q27 and Q29 are substrate p-n-p transistors, their

VB~’s are well matched. Since II and 12 are derived from the

well-controlled dc bias circuitry, they are known and fixed.

By emitter-area scaling Q26 to Q28 and Q27 to Q29, 10 is

set accurately and is not affected by temperature or process

variations. Common collector transistors Q28 and Q29 can

provide large output currents of up to 32812 and /329II , respec.

tively, yet with a very small standby current. Since Q28 and

Q29 are both active when the output swing is near zero, there

is no crossover distort ion.

This complementary cascaded emitter follower arrangement

buffers the high impedance node at the bases of Q26 and Q27

and insures that the gain stays high even when heavily loaded.

Also, it is stable when it is capacitively loaded.



FUKAHORI et al.: PRECISION MICROPOWER OP AMP

“Zur <z ‘v: ;’ ‘f

‘- (a)v- v-

(b) (c)

Fig. 12. Output stages considered for micropower levels. (a) A simple ClassA stage that has l imited current sinking capa-

bility. (b) The asymmetrical Class All stage that may have crossover distort ion. (c) The symmetr ical ClassAB stage. I t

has good current sinking capability and no crossc,ver distortion.

—~.

M?Qi”‘ “ TI

(-)

(

D(+)

Q,.

I I I II I I I I I wo,,

4 02,

z“::;~~:‘

Q,, Q,,0,

v.”,

3c,

0, Q,.

Q. Q,

c,

0,, 0,, 0,, 0,4 Q*,

0,,

10s5

~N.LLd cv-

Fig. 13. The complete circuit schematicof the true micropower highprecision op amp.

High breakdown p-n-p diode DI, connected as shown in The layout of the circuit is shown in Fig. 14. Symmetry of

Fig. 12(c), insures that n-p-n transistors Q26 and Q28 do not

Zener break down under all loading conditions. Because 11

and 12 are isolated from the rest of the dc bias circuitry, inter-

nal biasing is not affected when the op amp is overdrive

toward either power supply voltage.

V. PERFORMANCE AND RESULTS

In the previous sections this true micropower high precision

op amp hasbeen described in parts. Fig. 13 shows its schematicdiagram in its entirety. Q1 through Q6 is the input stage which

provides the high precision characteristics and allows single

supply operation. The well regulated dc biasing network is

composed of .11, l?3, Q32, and Q33 with the main bias line

connected to the base of Q34. Part of the second stage and

the common-mode loop is formed by Q7 through Q1O; Q13

supplies the tail current while Q 11 is the second stage active

load. Finally, the output stage is composed of Q26 through

Q30 which provides efficient drive at minimum current.

the circuit layout is observed for thermal ~onsideration [39].

The input is on the left side while the output is on the right.

The Zener trimming circuitry is located at the upper left

corner near the apparent extra pads. The standard bipolar

IC process is used to fabricate this op amp with the compatible

ion-implanted JFET added. Silicon-nitride protects the device

from ionic contaminants. On board capacitors are proportion-

ally smaller since the silicon-nitride has a higher dielectric con-

stant than silicon dioxide. The chip size is 1.73 X 1.14 mm2(68 X45 roil’).

The high precision nature of this op amp can be seen b y ex-

amining Table I. Untrimmed input offset voltage centered

near 400 MV is realized with a standard deviation of 400 pV.

With ~1.6 mV Zener-trimming range, the Offset voltage is re-

duced to below* 50 PV. Over 60 percent of the trimmed parts

had an offset drift of less than 1 p V/°C. The value of the open

loop gain centered around 2 X 106 and stayed over 1 X 106

for a wide range of supply voltages (Fig. 15), and temperature




Fig. 14. The die photo of the true micropower high precision op amp.

TABLE I

TYPICAL PERFORMANCEOF HIGH PRECISIONMICROPOWEROP AMP

PARAMETER MI CROPOWER GENERAL PURPOSE

VERS1ON VERS1ON

supply current (at +15V) 45 Ja 3ooua

Sin gle su pply +3 to +30V +3 +30V

Oual Supply voltage range il.5 to *15V 31.5 to ilsv

Input offset voltage ?400UV 400UV(untrimmed)

Input offset voltage t50 Jv t 50U V

(trimmed)

Input offset voltage dr]ft <1 .Ouvl”c <1. Ouvl”c

PSRR 120dB 120dB

CMRR l13dB 113d8

Open loop voltage gai” 126dB 126dB

Input bias current 10na 7olla

Input offset current 0,5na 2na

Max load drive capability lma 5ma

Un ity gain b and wid th 100 KHz 800 KHz

Slew ra te .05v/us o.3v/ps

Equivalent noise density 50nV/Hz’ 20nV/Hz%,at IOOHZ

c 1–

12 14 16 18

DUALSUPPLYVOLTAGE(V]

Fig. 15. Open loop gain versus supply voltages. It stayswelf over 120 dBfor a wide range of supply voltages.

140

120

VS=+15V

100

G=

z80

zo

:Cj

z60

K0

40

20

0-60 -40 -20 0 20 40 60 80 100 120 1 0

TEMPERATU RE (°C )

Fig. 16. Open loop gain versus temperature. It remains relatively con-

stant c,ver the military temperature range.

140

120 -

\ ~

T=2 s oc

100

s *Oe-

k

~

uu

8 600Jz

Y ~.0

20

0

0.01 0.1 1 10 100 lK 10K 100K lM

~~~Q”~~~y (I+z)

Fig. 1‘7. Open loc)p gain versus frequency.

(Fig. 16). These results show that this input stage is well

balanced and properly laid out. The frequency characteristics

of AVO1,PSRR, and CMRR can be seen in Figs. 17 and 18; they

all roll off with a 6 dB/oct slope.

The mi.i-opowar nature c~f this op amp can also be seen by

examining Table 1. The supply current is 45 PA at +15 V

power supply voltages with a standard deviation of about

15 vA. The variation in supply current is mainly due to varia-

tion of R3, a base resistor which was not trimmed. As shown

in Fig. 19, supply current increases slowly with temperature.

The change to 125°C increases supply current by 10 percent

while the decline to -55°C decreases it by 20 percent.

Another version of this c)p amp which operates at nearly six

times the supply current was made; all internal currents were

increased proportionally. The resulting performance is shown

in Table 1. The well behaved step responses for two different



FUKAHORIet al.: PRECISION MICROPOWEROP AMP

b)

.) VS =t15V

‘ ‘ ‘ ~1

0.1 1 10 100 lK 10K

FREQUENCY Hz)

Fig. 18. CMRR, curvea,and PSRR, curveb versusfrequency.

‘WH+H-H+ld~;o

T EM PE RAT uRE 0 C )

Fig. 19. Supply current versus temperature. Supply current exhibits

small variation over the temperature range.

a) b)

Fig. 20. Unity gain step response with R=5k.f2 and CL=lOOPF,

for supply voltages of a) *15 V and b) +5 V.

supply voltages are shown in Fig. 20. Hence= general purpose

op amp ac performance has been realized, but at much lower

supply current while simultaneously having very superior dc

characteristics. That is, with today’s technology, performance

can be ascertained at minimum power.

1057

VI. CONCLUSION

A configuration for a true micropower op amp with near-

ideal precision characteristics has been achieved. Thedc biasing

scheme uti lizes compatible ion-implanted JFET in conjunction

with the well regulated peaking current source. This biasing

method is analyzed to show its usefulness as a building block

for analog integrated circuits. Despite the number of devices

that are used in the input stalge, excellent high precision char-acteristics are achieved by proper design of the most critical

devices. Also, it permits single supply operation. It has been

shown that the matching of the balanced active load transistors

is needed to achieve low offset voltage drift; the drift is further

improved when the active load emitter degeneration resistors

are trimmed for minimum offset volt age. The maximum dis-

tinguishable gain has been achieved by double-buffering the

gain stages. A symmetrical output stage provides the needed

load-driving capability at micropower levels. Improved ac

characteristics are obtained merely by increasing the dc bias-

ing currents. At a fraction of the supply current of a g eneral

purpose op amp, comparable ac performance is achieved.

ACKNOWLEDGMENT

The authors would like to thank J. Hellguera for an excellent

layout and A. Lippold for device characterization.

[1]

[2]

[3]

[4][5][6][7][8]

[9]

10]11]12]13]14]15]

16]17]

[18]

[19]

[Zo]

[21]

[22]

f@ F13RENcES

R. J. Widlar, “A unique circuit design for a high performance

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tion;’ in Proc. NEC, vol. 21, pp. 85-89, Oct. 1965; also, Fairchild

Semiconductor Tech.Publ., TP-32,Nov. 1965.

—, “A monolithic op amp with simplified frequency compensa-

tion,” EEE, vol. 15, pp. 58-63, July 1967; also, ‘<A new mono-

lithic operational amplif ier design,” Nat. Semiconductor Tech.

Paper, ~P-2, June 196?.“Low voltage techniques,” IEEE J. Solid-State Circui ts , vol.

SC-~3, pp. 838-846, Dec. 1 178.

AiA735 Data Sheet, Fairchild Semiconductor, Aug. 1969.

1.tA776 Data Sheet, Fairchild Semiconductor, Oct. 1971.HA2720/2725 Data Sheet, Harris Semiconductor, Jan. 1974.

ML4202C Data Sheet, Microsystems Internation Ltd.

LHOOOIA/LOOOIAC Data Sheet, National Semiconductor, Mar.

1972.

LM146/LM246/LM346 Dal.a Sheet, National Semiconductor,NOV. 1976.

CA3078 Data Sheet, RCA, Jan. 1971.RM4132 Data Sheet, Raytheon, June 1969.

SE533 Data Sheet, Signetics, Feb. 1971.

L144 Data Sheet, Siliconix, 1973.

UC4250 Data Sheet, Solitron Device, Inc.

A. B. Grebene, Ana log Integrated CYrcuit Design. Princeton, NJ:

Van Nostrand, 1972, ch. 11.

OP-20 Data Sheet, Precision Monolithic. Inc., Sept. 1978.

D. Fullagar, “A new high performance monolithic operational

amplifier,” Fairchild Semiconductor Tech. Infer.; also “Fairchildbrings out ful ly compensated op-amp IC’S,” EEE, May 1968.

J. D. Macl)ougall, K. E. Manchester, and P. E. Roughan, “High

value implanted resistors for microcircuits, ” Proc. IEEE, vol.57, pp. 1538-1542, Sept. 1969.C. A. Bittmann, G. H. Wilson, R. J. Whittier, and R. K. Waits,

“Technology for the design of low-power circuits, ” IEEE J.

Solid-State Circuits, vol. SC-5, pp. 29-37, Feb. 1970.A. Tuszynski ancl J. H. Bohorquez, “Micropo Wer techniques in

di fferential amplif iers,” in NL?REM Rec., NOV. 1970, pp. 26-27.R. W. Russell and D. D. Ctslmer, “Ion-implanted JFET-bipolar

monolithic analog circuits, “ in IEEE ISSCC Dig. Tech. Papers,

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A. R. Hamade and J. F. Albarran, “A JFET/bipolar eight-channel



1058

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analog multiplexer,” IEEE J. Solid-State Circuits, vol. SC-10, pp.

399-406, Dec. 1975.J. Metzger, “A special report on bipolar and FET op amp:,”

Electron Products Msg., pp. 51-58, June 1977.A. R. Hamade and P. M. Brown, “Temperature compensated

quad analog switch,” in IEEE ISSCC Dig. Tech. Papers, Feb.

1979, pp. 182-183.

D. L. Cave and W. R. Davis, “A quad JFET wide-band operational-

amplifier integrated circuit featuring temperature-compensatedbandwidth,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 382-

388, Aug. 1977.

T. M. Frederiksen, “Constant current source,” U.S. patent

3659121, Apr. 25, 1972; also K. IL Stafford, P. R. Gray, and

R. A. Blanchard, “Complete monoli th ic sample/hold ampli fier,”

IEEE J. Solid-State Circuits, vol. SC-9, pp. 381-387, Dec. 1974;also T. M. Frederiksen, private communications, adapted fromM. J.Gay amplifier output stage. Used in MC1554, LM3900, and

LM324.

G. Erdi, “A precision trim technique for monolithic anaJog

circuits:’ IEEE J. Solid-State Circuits, vol. SC-10, pp. 412-416,

Dec. 1975.—, “A low drift, low noise monolithic operation amplifier forlow level signal processing,” Fairchild Semiconductor Appl. Brief,

136, July 1969.

M. A. Maidique, “A high-precision monolithic super-beta opera-

tional amplifier,” IEEE J Solid -Sta te Circu its, vol. SC-7, pp. 480-

487, Dec. 1972.

D. R. ColJins, “hFE degradation due to reverse bias emitter-basejunction stress,” IEEE Trans. Elect?on Devices, vol. ED-16, pp.

403-406, Apr. 1969.

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electronic bui ld ing blocks,” IEEE J. Solid-State Circuits, VOL

SC-7, pp. 446-454, Dec. 1972.

0. H. Schade, Jr., “A new generation of MOS/bipolar operational

amplifiers,” RCA Rev., vol. 37, pp. 404-424, Sept. 1976.J. E. Solomon, “The monolithic op amp: A tutorial study,” IEEE

J. Solid-State Circuits, vol. SC-9, pp. 314-343, Dec. 1974.

H. C. Lln, “Comparison of input offset voltage of different ial

ampl if llers using bipolar transistors and field-effect transistors, ”

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Integrated Circuits. New York: Wiley, 1977, ch. 4, 11.

—, “Recent advancesin monolithic operational amplifier design,”

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A. H. Hoffait and R. D. Thornton, “Limitations of transistor DCamplifiers,” Proc. IEEE, vol. 52, pp. 179-184, Feb. 1964.

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Klyoshi Fukahori S’72-M’77 was born inFukuoka City, Japan, in 1948. He received the

B.S. degree from San Francisco State University,

San Francisco, CA, in 1972, and the M.S. and

Ph.D. degrees from the University of California,

Berkeley, in 1974 and 1977, respectively.In December of 1976, he joined Precision

Monoli thic, Inc., Santa Clara, CA, and hasbeen

involved in the design of l inear integrated circuitsfor data conversion and telecommunications.

Dr. Fukahori is a member of Sigma Xi.

Yukio Nishikawa S’66-M’66 was born in San

Francisco, CA, in 1939, He received the B.S.

degree from the University of California, Los

Angeles, in 1966, and the M.S.E.E. degree from

the University of Santa Clara, Santa Clara, CA,

in 1971.

In 1967 he joined the Linear Microcircuits

Group at Fairchild Semiconductor, Mountain

View, CA, where he worked on the design and

characterization of linear and interface inte-

grated circuits. From 1971 to 1977 he worked

in the Standard Linear IC Group of National Semiconductor and lead a

group in the design of l inear and telecommunications integrated circuits.

In 1977 he joined Precision Monolithic, Inc., Santa Clara, CA, as a

Senior Staff Engineer and ispresently engagedin the design of integrated

circuits for telecommunications and data acquisition.

Adib R. Hamade’ M’74 received the B.SC.de-

gree in electrical engineering from the University

of Leeds, Leeds, England, in 1964, and he wilf

complete the M.B.A. program at the University

of Santa Clara, Santa Clara, CA, in December

1979.For three years hewason the engineering staff

at the Kuwait Broadcasting Service where he

held technical and managerial responsibil ities.

He then joined Plessey Semiconductor in En-

gland asa designer of hi -rel l inear integrated ci r-

cuits. He joined Natiomd Semiconductor Corporation, Santa Clara, CA,

in 1971, where he designed state-of-the-art consumer l inear integrated

circuits. In 1973, he started a design group at Nat ional for the develop-

ment of monolithic clata acquisit ion and data conversion products. Inthe summer of 1976, he joined Precision Monolithic, Inc., Santa Clara,

CA, asthe Manager of anew department whose responsibil ity isprimarily

the development of telecommunications and data acquisition integrated

ci rcuits. He has publ ished technical articles in various IEEE journals,

presented papers at I.EEE conferences, and was the recipient of the BestPaper Award. He was also awarded several patents in the field of in-

tegrated circuit design.

a high precision micropower operational amplifier

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