A high cell count cascade full bridge converter forwide bandwidth ultrasonic transducer excitation

Geoffrey R. Walker, Negareh Ghasemi, Mark A. H. Broadmeadow and Gerard F. LedwichSchool of Electrical Engineering and Computer Science

Queensland University of TechnologyBrisbane, Australia

Email: geoffrey.walker@qut.edu.au

Abstract—A nine level modular multilevel cascade converter(MMCC) based on four full bridge cells is shown driving apiezoelectric ultrasonic transducer at 71 and 39 kHz, in simula-tion and experimentally. The modular cells are small stackablePCBs, each with two fully integrated surface mount 22 V, 40 AMOSFET half-bridge converters, and include all control signaland power isolation. In this work, the bridges operate at 12 V and384 kHz, to deliver a 96 Vpp 9 level waveform with an effectiveswitching frequency of 3 MHz. A 9 µH air cored inductor formsa low pass filter in conjunction with the 3000 pF capacitanceof the transducer load. Eight equally phase-displaced naturallysampled pulse width modulation (PWM) drive signals, along withthe modulating sinusoid, are generated using phase accumulationtechniques in a dedicated FPGA. Experimental time domain andFFT plots of the multilevel and transducer output waveforms arepresented and discussed.

I. INTRODUCTION

High power piezoelectric transducers find use in numerousapplications, such as ultrasonic motors and actuators [1],or in biomedical applications [2]. In these applications, thepiezoelectric transducer generally requires driving at ultrasonicfrequencies at relatively modest power levels (10’s to 100’s ofWatts).

Ultrasonic transducers operate above 20 kHz, by defini-tion. Generating a low-distortion sinusoidal waveform at thisfrequency using pulse width modulation (PWM) requires aswitching frequency at least 10-20 times higher, which haspreviously not been practical at high powers. As an alternative,a single-phase, multilevel (four level) voltage source converterwith unequal DC link voltages, controlled with a harmonicelimination technique, demonstrated improved performancewith minimised energy at unwanted frequencies [3].

The highly capacitive nature of the ultrasonic transduceralso presents a challenge to the use of traditional voltagesource converters. A voltage source converter with its steppedoutput voltage waveform and high dV/dt results in significantcurrent spikes impressed upon the ultrasonic transducer. Alogical remedy is the use of an LC filter, however, the LCfilter can change the characteristic and resonant frequency ofthe ultrasonic transducer [4]. An alternative approach is to usea current source converter to avoid the problems associatedwith high dV/dt [4].

This work examines the possibility of driving the trans-ducer with a high cell count multilevel voltage source con-

verter, with an effective switching frequency more than anorder of magnitude higher than the resonant frequency of thetransducer. Both the small voltage steps and high effectiveswitching frequency minimise the required filter inductance inseries with the ultrasonic transducer. A series cascade of lowvoltage high switching frequency full bridge converter cells— a Modular Multilevel Cascade Converter (MMCC) — isintroduced in section IV for this purpose.

II. DRIVING ULTRASONIC PIEZOELECTRIC TRANSDUCERS

The equivalent electrical model of a piezoelectric ultrasonictransducer is most simply modelled an LCR series reso-nant network shunted by a significant capacitance (Van Dykemodel). The series resonant network is not due to electricalelements of the ultrasonic device, but rather “the apparentbehaviour of the first mode of mechanical vibration, as seenthrough the electrical port” [5]. The power delivered to theresistance of the network is due to the loss of the ultrasonictransducer, or when mechanically loaded, real ultrasonic powerdelivered by the transducer to its physical environment. Theshunt capacitance is a physical property of the transducer, andresults in the transducer appearing as a capacitive load whendriven at the frequency of its mechanical resonance.

In practice, multiple modes of vibration lead to multipleresonances and a more complex equivalent circuit [6]. In thiswork, the simple, single LCR branch model is sufficient forconsidering the problem of driving the ultrasonic transducer.

To excite a high-power ultrasonic transducer, a high powerand high quality excitation signal is required. From the per-spective of quality, a pure sinusoidal signal is naturally thebest option to be applied to drive an ultrasonic transducer. Thiscan be delivered by a linear amplifier, however, this requires alarger power supply and results in significant power dissipationin the amplifier. If a switching converter is used to drivethe transducer, amplifier efficiency improves but drive signalquality suffers. In a comparison between the two differentexcitation methods of a high power linear amplifier and a threelevel converter, it was demonstrated that driving an ultrasonictransducer with a low quality signal (that is, one with highharmonic distortion) is detrimental to the energy conversionperformance of the ultrasonic transducer and result in energydelivery at undesired frequencies [7]. This is unacceptable forsome applications, particularly biomedical applications.

978–1–4799–5776–7/14/$31.00 c© 2014 IEEE

III. MMCC CONVERTER FAMILY HISTORY

The Modular Multilevel Cascade Converter (MMCC) fam-ily was formally categorised by Akagi [8]. Three members, theSingle Star Bridge Cells (SSBC), Single Delta Bridge Cells(SDBC), and Double Star Chopper Cells (DSCC) are demon-strated to be well suited to a grid-level Battery Energy StorageSystem (BESS) [9], a Static Synchronous Compensator (STAT-COM) for negative-sequence reactive-power control [10], andan adjustable speed motor drive [11], [12], respectively.

Akagi [8] identifies Marchesoni [13], [14] as an originatorof the concept of the series cascade connection of full bridgesto create a high voltage multilevel output during the 1980s.Soon after, three phase star connected cascaded full bridgeswere commercialised for medium voltage drives by Robicon[15] but relied on a multi-winding line frequency transformerto supply power to each bridge module. For STATCOMapplications where only reactive power was processed, thistransformer could be avoided with appropriate modulation[16], [17].

Real power can be delivered without a central multi-winding transformer if each bridge has its own isolated batterysupply [18], [19] or a dedicated isolated dc-dc converter [20].

Marquardt and colleagues first demonstrated the possibilityof real power flow in series connected cells without individualcell power supplies for both DC-AC [21], [22] and AC-AC[23] applications, which led to renewed interest in the area.An important part of the control of any member of the MMCCfamily is the control of the cascaded half bridge or full bridgecapacitor voltage. Akagi and colleagues have demonstrated therequired PWM control of the MMCC-SSBC for the STATCOMapplication [24] and of the MMCC-DSCC [12].

A number of the MMCC experimental converters describedin the literature are at significant scale [24], [12], [25], orfull scale [13], [14], [15], [23]. This hardware consequentlydemands a significant investment of time, space and expense,compounded by the nature of MMCC architectures which, bydefinition, consist of multiple cells. If the intended researchfocus is on the initial experimental proof of concept of newarchitectures or control algorithms, rather than demonstrationat scale, a small, modular, versatile, reusable building block ismore appropriate.

In section IV, a small, low voltage high frequency MMCCfull bridge cell recently developed by our group is introduced.This module, suitable for all MMCC converter architectures,is specifically adopted for very high switching frequencycapability in this paper.

As this work is an initial proof of concept with an emphasison generating a high frequency multilevel output, each fullbridge is supplied by its own isolated supply, similar to theapproach taken by Ertl, Kolar and Zach [19], [20].

IV. MMCC CONVERTER EXPERIMENTAL PROTOTYPINGCELL

A small MMCC full bridge cell for “bench top” experimen-tal laboratory work is presented in [26]. The circuit design isbased around a number of highly integrated components tominimise complexity and design effort in this initial design(see Figure 1).

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Fig. 1. Extracts of the schematic diagram showing (top to bottom) the halfbridge driver (one of two), isolated supply and signal isolators

The full bridge is implemented using two 22 V, 40 AMOSFET half bridge converters (CSD97370). These deviceshave integrated gate drivers and associated logic and acceptlogic level PWM and enable signals. Their intended applicationis as synchronous buck converters, optimised for 12 V to1.2 V, 25 A operation at 500 kHz switching frequency. Theirmaximum switching frequency of 2 MHz and extremely lowinductance “stacked MOSFET” construction in a 5×6 mmSMD package also allows these modules to target new ap-plication areas for both MMCCs and other topologies. Onesuch target area — very high bandwidth amplifiers suitablefor ultrasonic transducer drive — is the focus of this paper.

The performance goals set out for the module along withthe design outcomes were as follows:

• Small size and mass — The size of the individualcell was chosen such that a converter of significantcomplexity (for example, a 24 cell MMCC-DSCC)could fit on a bench top alongside power supplies andoscilloscopes. Likewise, the complete converter masstarget was to be less than that of the surrounding benchtop test equipment.The completed full bridge converter cell consists ofa single four layer Printed Circuit Board (PCB) withdimensions 65×30 mm (see Figure 2), and mass mea-sured in grams. The complete experimental 17 levelfull bridge converter including the FPGA based mod-ulator used in this paper measures approximately250×100 mm.

Fig. 2. The top and bottom sides of the full bridge cell PCB. To stack thesemodules, the right hand side cell would be flipped over to sit on top of theleft hand side module.

• Enable easy cascading of power and signal connec-tions — Signal connections and power connections areautomatically made from board to board through theuse of SMD stacking PCB connectors (see Figure 2).These mate with matching gold flashed PCB contactlands on the underside of the next cell when the cellsare clamped together. Through a choice of connectorplacement, the module bridges can be either parallelor series connected. A simple double sided PCB isused as a mounting board for a stack of cells, andto introduce the PWM drive signals from an FPGA,microcontroller, or DSP.This approach of stacking provides a convenientmethod of passing signal and power connections alongthe chain of cascaded cells. This simplifies and speedsconverter construction and reconfiguration, and re-duces the risk of errors or poor connections. In a highcell count converter, this is a significant advantage.

• Include signal isolation and necessary isolated aux-iliary power supplies — Signal isolation is achievedusing high speed logic level signal isolators (Si8420)which offer 2.5 kV voltage isolation, 20 kV/µs dV/dtimmunity and 10 ns propagation delay. An isolatedsupply required by the isolators and integrated halfbridge gate drivers is supplied by a 500 mW, 2.5 kVisolated 5 V DC-DC converter (ADuM5000). Thissmall (SOIC16) integrated solution traded convenienceand size for cost and efficiency.By isolating all switching and other necessary signalsat each cell, any MMCC topology can be config-ured. The separate per cell isolated power supplysimplifies start-up consideration and removes potential

complications, easing operation in the unpredictableexperimental environment.

• Minimise losses and thus cooling requirements — Theneed for significant heat-sinking of each cell adds tothe size and mass of cell, which is then multipliedby the high cell count. All the components on thedesigned modules rely purely on cooling via the PCBcopper planes, and for output currents below 5 A, thepower loss per device is less than 1 W. In experimentalwork to these levels, the PCBs run noticeably warm,but never alarmingly hot.

• Implement on board protection — In any experimentalwork, a cell which protects itself as far as possiblespeeds implementation and result gathering. The inte-grated half bridge MOSFET ICs utilised provide someprotection through features such as under voltagelockouts, however, other desirable features such asover voltage or over current limits are not present. Inthis regard, a degree of caution is required on the partof the experimenter in the operation of these modules.

• Easy to manufacture and low in cost — When aconverter requires 24 or more cells, the material costof components and time required for manufacture (es-pecially if undertaken “in house”) rapidly multiplies.The full bridge cell was implemented exclusively withsurface mounted devices, with the goal of allowingautomated manufacture. The modules were manufac-tured in a small run of 50 PCBs by a local contractmanufacturer at a very reasonable cost (approximately$AUD 60 per cell for PCB, components and manufac-ture, including set-up) in a relatively quick turn-around(approximately four weeks).

A. Initial performance evaluation

For simplicity, the full bridge cell module was initiallytested in a parallel configuration, with four stacked modulesgenerating two five level anti-phase outputs. A 2 kHz sinewave of varying amplitude was impressed across a bridge tiedload (BTL) consisting of a 1 Ω resistor with a parallel 100 nFfilter capacitor. Total power levels from 1 W to 30 Wrmswere delivered to the load. Modules were tested with cellbus voltages of 5 V and 12 V, and carrier frequencies of192 and 384 kHz. The DC supply to resistive load efficiencyachieved a broad plateau of between 70 and 80% over thisrange, including filter component losses.

At an output current of approximately 2 A (sinking),the 12 V output voltage transitions were 10 to 20 ns induration. Almost no voltage overshoot was observed whichdemonstrated the low inductance layout and good supplydecoupling. A propagation delay due to the isolator and gatedrive circuitry of approximately 100 ns was observed, withwell matched rising and falling edge delays.

These initial results are more fully documented in the paperdiscussing the full bridge experimental cell design [26].

V. DIGITAL NATURAL MULTILEVEL MODULATION

Phase shifted PWM suitable for multi-level converter mod-ulation is generated using a Xilinx Spartan-6 FPGA on a low

cost “Mojo” development board [27]. The multilevel modu-lation is a digital implementation of natural sampling usingmultiple phase shifted triangular carriers, where the carriersare generated using phase accumulators rather than counters[28]. This technique allows the generation of PWM carrierswith arbitrary phase and frequency. In this implementation, 32-bit phase accumulators (carrier “triangles”) are updated andcompared with a 16-bit modulation waveform register all atthe 50 MHz system clock; ensuring true natural sampling,important for a low distortion waveform generation [29]. Inthis experimental work, a carrier frequency of 384 kHz isgenerated, with eight carriers shifted with equal phase shiftsof 45 degrees. While in this case these eight carriers canbe trivially created from the one phase accumulation regis-ter by manipulating the most significant three bits, separatephase accumulation registers are generated for more readableand generic VHDL code. The generous resources of modernFPGAs easily support this approach.

Two methods of modulating signal generation were imple-mented. For initial ease of evaluation and modification of themodulating signal, FPGA code to accept a SPDIF signals froma TosLink optical receiver was implemented, which alloweda two channel 16-bit, 48 kHz digital audio data-stream to beaccepted from a personal computer sound card or DVD player.This allowed for a rapid first proof of operation using sinewaves of arbitrary frequency and amplitude, and even musicalinput.

The sound card optical output used in this experimentalwork limited the modulating signals to 48 kHz, insufficient fordriving the ultrasonic transducer. To generate the 71 kHz mod-ulating waveform required, a direct digital synthesis (DDS)sine wave generator was implemented within the FPGA togenerate any arbitrary frequency and amplitude sinusoidalwaveform, using a 32-bit phase accumulator and a 12-bitpolynomial approximation sine generator [30]. In this initialwork, the frequency and amplitude are hard coded in theVHDL at synthesis, which did slow experimental testing. Thiswill be rectified in subsequent work.

The eight PWM signals are assigned to appropriate con-nector pins on the FPGA development board. The bench topexperimental set-up of four series connected full bridge cellsstacked on a carrier board, plugged into the Mojo FPGAdevelopment board connector, can be seen in Figure 5.

After the initial testing proved both the FPGA code andstackable modules were performing as expected, a digital audioamplifier was demonstrated using the SPDIF as a modulatinginput and a resistor and then speaker across the bridge outputs.Although formal tests were not pursued, no visible or audibledistortion was evident, and noise levels with the input mutedwere inaudible at the low power levels trialled.

Finally, the experimental tests using the ultrasonic trans-ducer was undertaken. The complete experimental setup in-cluding power supplies is shown in Figure 6.

VI. SIMULATION AND EXPERIMENTAL CONFIGURATION

The ultrasonic transducer used in this experimental workhas been previously used and characterised [31]; the electricalequivalent component values and resonant modes are listed in

Fig. 3. The LTSpice simulation of the nine level (four cell) multilevelconverter showing the unfiltered cascaded bridge output voltage (V(b45), red),the filtered voltage across the transducer (V(piezo), lime green), the currentflowing in the (internal) resonant branch of the piezo (I(L3), cyan), the currentflowing in the 9 µH filter inductor (I(L4), dark green), and one of the eightphase shifted half bridge outputs (V(b1pos), blue, offset). The simulationconditions: modulating frequency of 71.0 kHz, modulation depth of 0.9, PWMcarrier (switch) frequency of 384 kHz, and each full bridge powered from 12 V.

Fig. 4. Two oscilloscope images of the nine level (four cell) multilevelvoltage output (ch2, red), the driven (ch3, green) and receiving (ch4, orange)piezo transducer voltages, and one of the eight phase shifted logic level PWMdrive signals (ch1, blue). The modulating frequencies are 71.0 kHz (upper)and 38.8 kHz (lower); other conditions match the simulation.

Fig. 5. The nine level cascaded full bridge bench top experimental test setup. The FPGA PCB (left, black) supplies 8 PWM signals to the four stackedfull bridge cells (right). Bridge power input is via four barrel jacks (right rear)directly to the cells; multilevel output is via flying leads (yellow & black, farright).

Fig. 6. The bench top experimental test setup up showing (L-R) ultrasonictransducers (transmitter and receiver on opposite sides of water filled box),MMCC converter, 9 mH spider wound inductor and (behind) four isolatedpower supplies for each bridge.

Table I. Two matching transducers were mounted on oppositefaces of a rigid plastic, water filled box. While one transducerwas driven, the open circuit voltage of the second could bemonitored to check for operation at resonance and estimate themagnitude of power transmitted into the water. The transducerwas excited in this work at both the 71.0 kHz and 38.8 kHzresonant modes. The modulation depth selected was 0.9. Theswitching frequency for each half bridge cell was maintainedat 384 kHz from the previous experimental work.

The 3000 pF shunt capacitance of the transducer is sig-nificant, and does not naturally suit the direct connectionof a switched voltage source converter. Given the effectiveswitching frequency of approximately 3 MHz, a 9 µH air-cored inductor was used between the output of the nine level

TABLE I. PARAMETERS OF THE ULTRASONIC PIEZOELECTRICTRANSDUCER USED IN THIS EXPERIMENTAL WORK.

Shunt branch Resonant frequency Component values (LCR)

First resonant mode 70.2 kHz 56.6 mH, 89 pF, 492 Ω

Second resonant mode 48.6 kHz 48.3 mH, 218 pF, 640 Ω

Third resonant mode 38.8 kHz 48.3 mH, 341 pF, 583 Ω

Shunt capacitance — 3003 pF, 10 Ω

Shunt resistance — 100 kΩ

converter and ultrasonic transducer (see Figure 6). Combinedwith the 3000 pF shunt capacitance, this forms a low pass filterwith a -3 dB corner frequency of approximately 970 kHz. Themaximum ripple current can be calculated assuming a 12 V3 MHz squarewave impressed across the 9 µH inductor; thisgives 110 mA peak ripple. This is the peak magnitude seenin the Spice simulation (Figure 3); a slightly lower value wasmeasured in the experimental circuit.

The four floating power supplies for the full bridge cells areconveniently provided by 240 Vac to 12 Vdc, 0.5 A regulated“plugpack” style flyback power supplies. They naturally pro-vide the necessary isolation, and the measured output to outputcapacitance was of the order of 10 pF. Each cell additionallyhad a board mounted 1000 µF, 16 V electrolytic capacitor andzener diode for supply bypassing and protection.

An additional 5 V power supply was used for the FPGAdevelopment board and cell auxiliary supplies, rather than relyon the USB supply. With four full bridge cells and the FPGAdevelopment board operating at 384 kHz switching frequency,the supply requirement was 0.48 A.

VII. SIMULATION AND EXPERIMENTAL RESULTS ANDDISCUSSION

The unfiltered cascaded bridge output voltage (V(b45),red), the filtered by the 9 µH inductor and piezo capacitance(3000 pF) to give the voltage across the transducer (V(piezo),lime green). The current flowing in the (internal) resonantbranch of the piezo (I(L3), cyan) is a smooth sinewave inphase with the piezo voltage. In contrast, the current flowingin the 9 µH inductor (I(L4), dark green) displays the 3 MHzeffective switching frequency ripple current component. Oneof the eight phase shifted half bridge outputs (V(b1pos), blue)is shown offset for reference.

The experimentally gathered results (Figure 4) very closelymatched the waveforms generated by Spice (Figure 3). Themost significant area of difference was the behaviour of the realultrasonic transducer as compared to the ideal single resonantbranch model used in the Spice simulation. As the modulatingfrequency was hard-coded in the VHDL code for the FPGA,changing this value to match the actual resonant frequencywas somewhat laborious. Further, as the modulating frequencywas moved towards resonant frequency, some unexpected“beating” behaviour in the ultrasonic transducer waveformswas observed.

The oscilloscope was used to generate fast fourier trans-forms (FFTs) of the nine level MMCC output voltage (red) andtransducer voltage (green) (Figures 7 and 8). A logarithmic dB-Vrms vertical axis was used along with a hanning windowingfunction to better show low level harmonic performance. The

Fig. 7. Two oscilloscope FFT images of the nine level (four cell) multilevelvoltage output (upper, red) and the driven piezo transducer voltage (lower,green). The colours match those in Figure 4. The 39 kHz fundamental ison the LHS axis. The first and second uncancelled carrier groups are clearlyvisible centred around 3 MHz and 6 MHz respectively in the MMCC converteroutput (red), but are mostly filtered in the transducer waveform (green). (x-axisDC to 7.5 MHz bandwidth displayed).

first and second multilevel carrier groups are clearly visible inthe MMCC output voltage, centred at 3 and 6 MHz (8 and16×384 kHz), spanning approximately 1 and 2 MHz respec-tively. The amplitude of the first carrier group is approximately30 dB below the fundamental even before filtering (Figures 7,upper, red). After the filtering provided by the 9 µH inductorand the resonant characteristic of the transducer, both carriergroups are very well supressed, but an unexpected spuriousmode is excited around 1 MHz. This is evident in the timedomain waveforms in Figure 4, (lower plot, green trace). It isconjectured that spurious harmonics associated with the (12bit) DDS sinusoidal fundamental generation or DDS PWMgeneration are exciting higher order resonant modes in thetransducer, and further research is required into this issue.

When the spectrum between DC and 150 kHz is examined(Figure 8), some low level spurious harmonics are observedin the multilevel output waveform (red, upper), but these aremostly 30 dB below the 39 kHz fundamental. These arecompletely suppressed in the transducer waveform (green,lower).

Fig. 8. FFT images of the nine level (four cell) multilevel voltage output(upper, red) and the driven piezo transducer voltage (lower, green), as perFigure 7 but zoomed in on the 39 kHz fundamental sinewave (x-axis DC to150 kHz). Some spurious harmonics due to the DDS sinewave and/or PWMgeneration processes are visible in the MMCC converter output (red), but arecompletely suppressed by the transducer high Q resonant filter characteristic.

VIII. CONCLUSION

A nine level modular multilevel cascade converter(MMCC) based on four full bridge cells is shown drivinga piezoelectric ultrasonic transducer at 39 and 71 kHz, insimulation and experimentally. The modular cells are smallstackable PCBs, each with two fully integrated surface mount22 V, 40 A MOSFET half-bridge converters, and include allcontrol signal and power isolation. In this work, the bridgesoperate at 12 V and 384 kHz, to deliver a 96 Vpp nine levelwaveform with an effective switching frequency of 3 MHz.

A 9 µH air cored inductor forms a low pass filter in con-junction with the 3000 pF capacitance and high Q resonanceof the transducer load. Eight equally phase-displaced naturallysampled pulse width modulation (PWM) drive signals, alongwith the 39 or 71 kHz modulating sinusoid, are both generatedusing phase accumulation techniques in a dedicated FPGA.These techniques produce very low distortion of the funda-mental waveform, but can generate spurious low level tones.

Experimental waveforms at the converter output and acrossthe transducer are as expected, with very good harmonic per-formance. Some spurious harmonic tones due the modulationprocess are observed, and require further detailed analysis to

assess their impact in this application.

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