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Embedded Systems for Information Technology (ESIT) Ruhr-University Bochum Prof. Dr.-Ing. habil. Michael Hübner A Hardware/Software Co-Design Approach for Control Applications with Static Real-Time Reallocation IPDPS 23-27.5.2016 23rd Reconfigurable Architectures Workshop Benedikt Janßen, Moataz Nasserddin, Michael Hübner

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  • Embedded Systems for Information Technology (ESIT)Ruhr-University Bochum Prof. Dr.-Ing. habil. Michael Hübner

    A Hardware/Software Co-Design Approach for

    Control Applications with Static Real-TimeReallocation

    IPDPS • 23-27.5.201623rd Reconfigurable Architectures Workshop

    Benedikt Janßen, Moataz Nasserddin, Michael Hübner

  • 2Embedded Systems for Information Technology (ESIT)Ruhr-University BochumProf. Dr.-Ing. habil. Michael Hübner

    • Control Sytem Design– Usually done in Mathworks Matlab

    – Critical component that should be fault tolerant

    • Hardware/Software Co-Design for Fault-Tolerant Controller– High-Level Synthesis based development flow approach

    – Seamless control algorithm reallocation between hardware and softwaredomain• Load balacing during run-time

    • Handling of faulty components

    Motivation

  • 3Embedded Systems for Information Technology (ESIT)Ruhr-University BochumProf. Dr.-Ing. habil. Michael Hübner

    Controlled System

    Tank

    Reservoir

    Pump

    FlowSensor

    LevelSensor

  • 4Embedded Systems for Information Technology (ESIT)Ruhr-University BochumProf. Dr.-Ing. habil. Michael Hübner

    Controller and Supervisor

  • 5Embedded Systems for Information Technology (ESIT)Ruhr-University BochumProf. Dr.-Ing. habil. Michael Hübner

    Design Flow

  • 6Embedded Systems for Information Technology (ESIT)Ruhr-University BochumProf. Dr.-Ing. habil. Michael Hübner

    Avnet ZedboardBridgeMPS PA Workstation

    Avnet ZedboardBridgeMPS PA Workstation

    Source: Festo Didactic

    System Architecture

  • 7Embedded Systems for Information Technology (ESIT)Ruhr-University BochumProf. Dr.-Ing. habil. Michael Hübner

    Evaluation

    • Cycle time 100ms Dynamic reallocation during run-time

    • Resource usage PS: ~3% (workload), Slices: 5% , BRAM: 0% , DSP48E1: 2%