NSF ERC for Wireless Integrated MicroSystems (WIMS)NSF ERC for Wireless Integrated MicroSystems (WIMS) 1

A DSP Enabled Microsystem for Cochlear Implants with Hybrid LC Clocking

Register Files

Decode Execute

Memory Management Unit

BootROM

32kBSRAM

USART

Hybrid LC + Ring Clock Source

128k

B E

xter

nal

Mem

ory

X2DSP

LoopCache/Timer

X3SPI

LUT

Fetch

SPIX2

Telemetry coil,RF interface, ADC,voltage regulator

Flexible polyimide

cable

Back-end electronics,

current sources,communication

interface

128-site high density

electrode array

Hermeticvacuumpackage

MicHPF

BPF 1 Rectifier LPFNonlinear

MapEl-1

BPF 2 Rectifier LPFNonlinear

MapEl-2

BPF n Rectifier LPFNonlinear

MapEl-n

BandpassFilters

Envelope DetectionCompression

VolumeControl

PulseModulation

NSF ERC for Wireless Integrated MicroSystems (WIMS)NSF ERC for Wireless Integrated MicroSystems (WIMS) 2

CIS DSP Core

• 16 channels• Expandable

architecture• Reduced datapath

width• 3MHz operation

with 22kHz front-end ADC

• 3,000 pulses per second per channel maximum

• Four operating modes– Programming– Stimulation– Test– Sleep

16

Control Unit

15 8

ADC Data

HP HPReg

BPBPRegBPReg

LP LPRegLP

Reg

LUT

LUTRegLUTReg Vol

VolRegVolReg

ModulatorFSM

addrreset clknew

samplesleep

sleep cascadechannel

Filter Cascade

MCU Interface

writedata

readdata

addr writedata

readdata

addrdata

coeffwe

coeffdata

ADCdata

requestsample

LUTdata

LUTaddr

addr

data

NSF ERC for Wireless Integrated MicroSystems (WIMS)NSF ERC for Wireless Integrated MicroSystems (WIMS) 3

Microsystem Measured Results

• TSMC 0.18m MM/RF bulk CMOS

• 1.79mW from 1.2V is lowest reported DSP power consumption

• Add 22kHz 16-bit ADC in future

3.03mm

45.64 4.97

9.62b

2.46a

7.83

25.73

100MHz

VDD = 1.8V

0.76c

2.46

0.12

1.63

DSP Modea Standby

DSP Modea1MHzStandby

1.67

0.18c

1.14a

0.04

0.31

VDD = 1.2V

1.79

0.18c

1.14

0.03

0.44

0.33

0.18c

0.06

0.03

0.06

1.32

0.76c

0.27

0.12

0.17

Total (mW)

Clock (mW)

DSP (mW)

Memory (mW)

Core (mW)

45.64 4.97

9.62b

2.46a

7.83

25.73

100MHz

VDD = 1.8V

0.76c

2.46

0.12

1.63

DSP Modea Standby

DSP Modea1MHzStandby

1.67

0.18c

1.14a

0.04

0.31

VDD = 1.2V

1.79

0.18c

1.14

0.03

0.44

0.33

0.18c

0.06

0.03

0.06

1.32

0.76c

0.27

0.12

0.17

Total (mW)

Clock (mW)

DSP (mW)

Memory (mW)

Core (mW)

a. DSP is operating at 3MHz. Other components operating at speed necessary to support DSP function.b. LC oscillator is operating, ring oscillator is off.c. Ring oscillator is operating, LC oscillator is off.

Component

OperatingCondition

Component

OperatingCondition