a development of single cycle control low voltage grid

A Development of Single Cycle Control

Low Voltage Grid Connected Inverter

Pramod Ghimire

A thesis submitted in partial fulfilment

of the requirements for the degree of

Master of Engineering

in

Electrical and Computer Engineering

at the

University of Canterbury,

Christchurch, New Zealand.

June 2009

ABSTRACT

The thesis describes a development of simple and low engineering cost Single Cycle Controlledgrid connected inverter. The voltage source current controlled inverter aims to support lowvoltage grid from small scale distributed power sources.

Single Cycle Controller uses real time current to control PWM switching of the inverter. Thecontroller forces output current to have the same phase as an ordered AC signal. The invertersupports the grid at unity power factor if the AC signal is taken directly from the grid. Use of agenerated AC signal is proposed, which allows control over active and reactive current injectionor absorption by the inverter. A new synchronized waveform generation method implementablein a microcontroller is proposed in the thesis.

A number of Single Cycle Control switching strategies for the H-bridge converter are tested.A hybrid pulse width modulation switching strategy is used as it switches only one switch athigh frequency at any time, which reduces switching losses in the bridge and allows easier im-plementation in hardware. The controller limitation near voltage zero crossing in boost mode isillustrated.

Single Cycle Control results in current distortion near voltage zero crossings. Strategies tomanage this are presented.

The inverter is simulated in PSCAD and hardware prototype is built. The prototype resultsare presented for current injection into the grid at unity power factor.

ACKNOWLEDGEMENT

I would like to express my sincere gratitude to my supervisor Dr. Alan Wood. Thank you forencouragement, guidance and support throughout the time, since I have been enrolled at theUniversity. I would like to thank my co-supervisor Dr. Paul Gayner.

I would like to show my gratitude to Assoc Prof Dr. Nevile Watson, Prof Abdul Rahman,Dr. Chris Arnold and Dr. Piet Beukman for their encouragement during course work period.

It is my pleasure to thank all the technical members for being there all time when I needed.Thanks to Late Ron Battersby for taking care at power electronics laboratory, Ken Smart for allthose equipments, Michael Cusdin for helping in Altium design, Dudley Berry for bringing com-ponents, Nick Smith and Scott Lloyd in PCB preparation, David Healy for all mechanical work,Randy Hampton and Philipp Hof for helping with the oscilloscope, drilling, microcontroller etc.

I am very grateful to New Zealand’s International Aid and Agency (NZAID) for offering me ascholarship and providing me supports during my stay in New Zealand, without the scholarshipit would not be possible for me to study at Canterbury University. I owe my deepest gratitude toNZAID financial adviser Adrian Carpinter, NZAID advisor Stephen Harte and the people fromInternational student support Mary Furnari, Jonie, Sarah, and Lawrence for making my life easy.

I really appreciate the support and encouragement from Nepalese community (Nepal NewZealand Friendship Society), Christchurch for making my staying very special and unforgettable.

I am indebted to EPECenter and thanks to Joseph Lawrence and Dr Pat Bodger for givingme a space at the program organized by the center.

I appreciate the help and encouragement from all my colleagues Lance, Jordan, Zeff, Vijaya,Bhaba, Robert, Bob, Ida, Andrew, Nick, David, Simon etc. Thank you to all power systemgroup.

I would like to thank Dr Peter Freere and his family and KAPEG, Nepal members.

Finally, I would like to thank my parents and sisters for everything and believing in me.

CONTENTS

GLOSSARY xvii

CHAPTER 1 INTRODUCTION 11.1 General Introduction 11.2 Research Objectives 21.3 Thesis Outline 2

CHAPTER 2 BACKGROUND 52.1 Introduction 52.2 Distributed Power Sources 52.3 A Review of GCI Topology and Controller Strategy 6

2.3.1 GCI Topology 62.3.2 Current Controller Strategy 92.3.3 Converter Topology 10

2.4 DPS Integration in Electricity Distribution System 112.4.1 Low Voltage Grid 112.4.2 Grid Interconnection Issues and Options 12

2.5 Interaction Between Inverter and Low Voltage Grid 122.5.1 Steady State Conditions 122.5.2 Transient Stability 132.5.3 Voltage Stability 132.5.4 Voltage Waveform Distortion 13

2.6 Power Flow 142.7 Conclusion 14

CHAPTER 3 SINGLE CYCLE CONTROL 173.1 Introduction 173.2 Basics of Single Cycle Control Theory 18

3.2.1 Current Magnitude Control 193.2.2 Current Shape Control 203.2.3 Current Phase Control 21

3.3 Controller 213.3.1 Input Parameter Relation for Current Control 23

3.4 Control Process in Circuit 233.5 Conclusion 25

viii CONTENTS

CHAPTER 4 SWITCHING LOGIC FOR SINGLE CYCLE CONTROL 274.1 Introduction 274.2 Converter Topology 274.3 Converter Switching Strategy 28

4.3.1 Unipolar Pulse Width Modulation 284.3.2 Bipolar Pulse Width Modulation 284.3.3 Hybrid Pulse Width Modulation 28

4.4 Switching Logic Circuit Development 294.4.1 HPWM Switching Strategy 314.4.2 Bipolar Switching Strategy 31

4.5 Selection Criteria of Switching Strategy 324.6 Converter Four Quadrant Operations 33

4.6.1 Buck Mode 344.6.2 Boost Mode 344.6.3 Constraints During Boost Operation 34

4.7 Conclusion 35

CHAPTER 5 SINGLE CYCLE CONTROL CURRENT WAVEFORM 375.1 Introduction 375.2 Current Control 385.3 Zero-Crossing Current 38

5.3.1 HPWM Switching Strategy 395.3.2 Bipolar Switching Strategy 40

5.4 Current Harmonics 415.5 Logic Circuit to Improve Current Waveshape 425.6 Conclusion 43

CHAPTER 6 FOUR QUADRANT POWER CONTROL 456.1 Introduction 456.2 Power Control 45

6.2.1 Controller Strategies 456.2.2 Active Power Control 466.2.3 Reactive Power Control 47

6.3 Voltage Control 476.4 Implementation of New Generated Waveform 49

6.4.1 Phase Synchronization 496.4.2 Lookup Table Development for Angle Measurement 52

6.5 Conclusion 53

CHAPTER 7 SIMULATION, DESIGN AND PROTOTYPEDEVELOPMENT 557.1 Introduction 557.2 Simulation 557.3 Controller Circuit 56

7.3.1 Oscillator 567.3.2 Resettable Integrator 57

7.4 Voltage and Current Detection 58

CONTENTS ix

7.4.1 Zero-Crossing Sensing 597.5 Logic Circuitry 597.6 IGBT Gate Drive Circuitry 597.7 Power Circuit 61

7.7.1 Parasitic Bus Inductance 627.7.2 Stray Inductance Between High Side and Low Side Switch 63

7.8 Filter 647.8.1 Size of Inductor 647.8.2 Selection of Core 65

7.9 Thermal Design 667.9.1 Inverter Board and Heat Sink Estimation 66

7.10 Hardware Construction 677.10.1 GCI Test Rig 687.10.2 Prototype Results and Discussion 68

7.11 Conclusion 71

CHAPTER 8 CONCLUSION 738.1 Conclusion 738.2 Future Work 73

APPENDIX A MICROCONTROLLER 75

APPENDIX B INDUCTOR DESIGN 81

APPENDIX C THERMAL SYSTEM 83C.1 Inverter Board 83

C.1.1 Power loss in IGBT 83C.1.2 Power loss in Diode 84

APPENDIX D PSCAD SIMULATION 87D.1 Single Cycle Controller 87D.2 Logic Circuit 88D.3 Inverter Circuit 89

APPENDIX E HARDWARE DEVELOPMENT 91E.1 Circuit Diagrams 91

APPENDIX F PUBLISHED PAPER 105

REFERENCES 107

LIST OF TABLES

3.1 SR latch truth table 243.2 SCC logic sequence 25

4.1 UPWM switching options 284.2 BPWM switching options 294.3 HPWM switching options 294.4 Logic development rules 304.5 Terminology used in development of Boolean equations 314.6 Boolean equations in first switching method 314.7 Boolean equations in second switching method 324.8 Boolean equations in third switching Method 324.9 Boolean equations in fourth switching method 33

5.1 New truth table after addition of new logic 42

6.1 Logic to find the operating sin θ − cos θ plane 526.2 Logic to find the operating sin θ − cos θ plane 526.3 Phase angle decoupling 53

7.1 Simulation parameters 557.2 Inductor designed paramter 667.3 Bridge operating parameter 667.4 Power loss in power switches 67

LIST OF FIGURES

2.1 Four switch and six switch buck-boost inverter 72.2 Converter with a DC link 72.3 Converter with a Pseudo DC link 82.4 Converter without a DC link 82.5 Hysteresis current controller 92.6 Hysteresis current control 92.7 Ramp comparison current controller with hysteresis 102.8 Predictive current controller 102.9 Grid series impedance 122.10 Inverter grid connection 132.11 Inverter connection to grid 14

3.1 Controller block diagram 173.2 SCC signal flow block 183.3 Single Cycle Control signals 193.4 Current at variable x(t) and fixed v(t) 203.5 Current at fixed x(t) and variable v(t) 203.6 v(t) as leading phase angle 213.7 Single Cycle Controller 213.8 Controller operation waveform 223.9 Current and voltage signals at the input of comparator 233.10 Logic sequence and operation of SCC 24

4.1 Full bridge inverter 274.2 Current lagging waveform 304.3 Current leading waveform 304.4 4Q operation 1.HPWM 2.BPWM 334.5 Equivalent buck circuit for 1. First quadrant 2. Third quadrant 344.6 Equivalent boost circuit for 1. Second quadrant 2. Fourth quadrant 344.7 Current distortion during boost mode 35

5.1 Current control in one switching cycle 375.2 Power circuit 385.3 vL(t), Vg, vo(t) for HPWM first switching method 385.4 Current ripple for HPWM first switching method 39

xiv LIST OF FIGURES

5.5 Grid voltage and output current near zero crossing for 2Q first switching method(HPWM) 39

5.6 Grid voltage and output current near zero crossing for 2Q second switchingmethod (HPWM) 40

5.7 Grid voltage and output current near zero crossing for third switching method(BPWM) 40

5.8 Grid voltage and output current near zero crossing for fourth switching method(BPWM) 41

5.9 Output current harmonics 415.10 Additional logic on SR latch 425.11 SCC controller signals waveform near zero crossing 42

6.1 New waveform generation 466.2 Power control strategy 476.3 Active and reactive power injection into the grid using SCC 476.4 Active power injection into the grid and reactive power absorption from the grid

using SCC 486.5 Inverter connected to grid 486.6 Phaser diagram for 1. reactive power only 2. active power only 486.7 Real and reactive power compensation 496.8 Phase locked loop diagram 496.9 Phase angle detection block diagram 506.10 Continuous integrator 506.11 sin θ and cos θ 516.12 1. tan θ 2. Phase angle 516.13 4Q sin θ − cos θ plane 526.14 ADC register 53

7.1 The SCC control signals 567.2 Grid voltage and output current 567.3 Timer 555 577.4 Resettable integrator 577.5 Analogue switch 587.6 Current and voltage monitoring circuit 597.7 Zero crossing detection 597.8 IGBT switching logic sequence for Q1, Q2, Q3 and Q4 at reactive current injection 607.9 IGBT driver IR2112 logic voltage level 607.10 IGBT driver circuit diagram 617.11 Snubber across IGBT 627.12 DC bus connection at PCB 637.13 Stray inductance 647.14 Inductor core 657.15 Equivalent circuit 1.at 50Hz 2.at 5kHz 657.16 Controller board and test set up 677.17 Inverter test rig layout 68

LIST OF FIGURES xv

7.18 Integrator reset pulse and output 687.19 SCC controller operation 697.20 IGBT switching gate pulse for Q1 697.21 Inverter output voltage 707.22 Scaled AC voltage and current waveforms 707.23 Current harmonic spectrum 71

B.1 Duty cycle at fundamental current peak 81

D.1 Single cycle controller 87D.2 Switching logic circuit 88D.3 Inverter circuit 89

E.1 Circuit 92E.2 Oscillator 93E.3 Voltage detector 94E.4 Voltage and current sensing circuit 95E.5 Single cycle controller unit 96E.6 Logic 97E.7 IGBT driver circuit 98E.8 SCC controller PCB 99E.9 SCC controller PCB upside 100E.10 SCC controller PCB downside 101E.11 SCC controller PCB component layout 102E.12 Laboratory test set up 103

GLOSSARY

Abbreviations

AC Alternating CurrentA/D Analogue to Digital ConverterAPF Active Power FilterBPWM Bipolar Pulse Width ModulationCBS Bootstrap CapacitorCOM GroundCMOS Complementary Metal-Oxide-SemiconductorDC Direct CurrentDG Distributed GenerationDPS Distributed Power SourcesDSP Digital Signal ProcessingEMI Electromagnetic InterferenceEMTDC Electro Magnetic Transient Direct CurrentESR Equivalent Series ResistanceFACTS Flexible AC Transmission SystemsFPGA Field Programmable Gate ArrayFFT Fast Fourier TransformFund FundamentalGCI Grid Connected InverterHPWM Hybrid Pulse Width ModulationIGBT Insulated Gate Bi-polar TransistorMIC Module Integrated ConverterPCC Point of Common CouplingPFC Power Factor ControllerPLL Phase Locked LoopPI Proportional-Integral controllerPSCAD Power System Computer Aided Design - interface for EMTDCpu Per-unitPV Photo VoltaicPCB Printed Circuit BoardPWM Pulse Width ModulationRMS Root Mean SquareSCC Single cycle controllerSPWM Sinusoidal Pulse Width ModulationSS Steady State ConditionSTATCOM Static CompensatorSW SwitchingTHD Total Harmonic Distortion

xviii GLOSSARY

TS Transient StabilityUPWM Unipolar Pulse Width ModulationVS Voltage StabilityVSC Voltage Source ConverterVWS Voltage Waveform Stability4Q Four Quadrant2Q Two Quadrant

Symbols

C DC side CapacitorD1, D2, D3, D4 Diode Switchesio(t) Inverter output currenti(t) Small scaled current in Single cycle controllerP Real powerQ Reactive powerv(t) Scaled AC voltage for current controlvnew(t) New generated current ordered AC signalvo(t) AC supply voltageX DC control signalQ1, Q2, Q3, Q4 IGBT Switches

Chapter 1

INTRODUCTION

1.1 GENERAL INTRODUCTION

Proper use of freely available renewable energy sources is a global need today. There are twomajor global challenges ahead; one is to reduce the carbon emission to mitigate the reductionin global warming and another is to allow easy access to the basic need for power to all humanbeings. The proper use of effective power electronics technology will increase the use of widelydistributed power sources which addresses both above mentioned challenges [1] . Advancedpower electronics also play a vital role to interconnect different types of power sources effi-ciently, increase power transfers and reduce losses, allow flexible transmission of energy, variablespeed operation of electric generators etc [2] . The thesis goal is the development of a simpleand low engineering cost Grid Connected inverter (GCI) which will boost the use of renewableenergy systems in remote and urban locations.

The purpose of this thesis is to develop a cheap and simple inverter system to interconnectsmall scale power generator to the low voltage grid. GCI systems often require a Digital SignalProcessor (DSP) and complex engineering [3]. Depending upon the nature of sources, the inter-connection systems require AC to DC and DC to AC converters. Herein after the AC to DCconverter is called generator side converter and DC to AC converter is called AC side converter.The generator side converters are relatively cheap and available in different standards. Theydirectly connect generator output to the AC side converter through a DC link capacitor. Thework is focused on the development of the AC side converter. The purpose of AC side converteris not only to invert DC into AC voltage, but also to interconnect output power to a utility grid.The GCI systems should be featured with interconnection standards acceptable by the utilitysystems [4].

Generally renewable power sources are connected to a distribution level grid. Penetration ofboth active and reactive power is significantly useful for stability of the grid. Reactive powercontrol might not be very effective to control voltage at the low voltage grid in comparison toa high voltage systems [5]. Nevertheless, reactive power injection is important to support theinductive load and reactive part of grid itself. Use of reactive power control helps to stabilize thegrid voltage to some extent. Optimum active power injection is effective to maintain the voltagelevel in such smaller systems. Generally low voltage systems have a high impedance. The pro-posed inverter system is intended to support the grid at unity power factor during normal gridvoltage. Upon decreasing or increasing the grid voltage level, the inverter system either generatesor absorbs reactive power. The consequence of reactive power compensation from individual sys-tem may be negligible. However, large numbers of such small systems at suitable locations canprovide substantial support for the system stability. This thesis doesn’t outline the rating andnumber required to compensate the reactive power at different voltage level. It does, however,

2 CHAPTER 1 INTRODUCTION

discuss how much the proposed system can compensate reactive power at different voltage levels.

The thesis proposes a GCI system to connect at distribution voltage level from small scalepower generators for a range of 1KW in single phase systems. Single Cycle Control (SCC) [6] isproposed to control the inverter current either in phase with, leading or lagging the grid voltage.The minimum requirements of source voltage and operating characteristics are outlined. SingleCycle Controller is explained and power control methodologies are presented. The logic im-plementation for inverter switching strategies are presented and current zero-crossing problemsare addressed for each strategy. A simulation is performed on PSCAD/EMTDC program. Alaboratory hardware prototype is built. Both simulation and hardware results are presented inthe thesis.

1.2 RESEARCH OBJECTIVES

The objective of this research is to develop a cheap and simple grid connected inverter systemwhich allows the connection of dispersed small scale renewable sources or DC energy storage tothe grid. Available inverters are relatively expensive and uses complex circuitry for the purpose.

The thesis investigates different single cycle logic switching methods for the H-bridge converterto find efficient and less current distorting methods for easier implementation in hardware. Theperformance for different switching methods are investigated through simulation.

The inverter is proposed to support the grid at unity power factor, during healthy networkconditions. However, if the system voltage level changes, it will inject the reactive current tocompensate the reactive loss in the filter impedance and the grid itself.

The converter will be equipped with power control and allows bidirectional flow of both ac-tive and reactive current.

1.3 THESIS OUTLINE

Chapter 2 provides background on renewable energy integration into low voltage grids. Gridconnected inverter topologies are reviewed and interactions of the inverter with low voltage gridare discussed.

Chapter 3 describes Single Cycle Control theory.

Chapter 4 presents switching logic for Single Cycle Control. Three different switching strate-gies are presented and ranges of switching methods are given for switching of full bridge inverter.

Chapter 5 illustrates current performance in Single Cycle Control. Zero crossing performance ofthe current is shown for the ranges of switching methods.

Chapter 6 presents power controller using Single Cycle Control. A waveform generation methodis proposed. A phase synchronization method implementable in microcontroller is proposed inthe chapter.

Chapter 7 provides PSCAD simulation results. Circuit design is presented. A laboratoryprototype development is given and experimental results are presented.

1.3 THESIS OUTLINE 3

Chapter 8 concludes thesis. Future work is recommended for proposed grid connected inverter.

Chapter 2

BACKGROUND

2.1 INTRODUCTION

A number of grid connected inverter topologies and switching strategies have been developeddepending upon the nature of distributed power sources. The aim of the inverter is to transfermaximum available energy to the power network despite having strong interactions during con-nection. An economic and reliable interconnected system is a challenging issue for a weak gridnetwork.

This chapter presents a brief summary of recent work in the field of interconnection of smalldistributed power sources through a inverter into the low voltage network. It contains a brief in-troduction to distributed energy sources, a review on inverter topology and controller strategies,integration of inverter and source into a distribution network and probable interactions betweeninverter and grid for single phase systems.

2.2 DISTRIBUTED POWER SOURCES

Distributed Power Sources (DPS) are defined as ”demand and supply side resources that canbe deployed throughout an electric distribution system (as distinguished from the transmissionsystem) to meet the energy and reliability needs of the customers served by the system. Dis-tributed resources can be installed on either the customer side or the utility side of the meter”[7]. Various kinds of renewable and non renewable distributed power sources exist [8]. Dueto the increasing global crisis in non-renewable energy resources, renewable and green sourceshave been attracting more attention recently. Established distributed energy sources are; micro-hydro, wind, solar power fuel cell, combined heat and power, bio-gas, bio-mass, geothermal anddiesel power.

In order to improve the reliability of the generation and injection of power into the grid duringoverload, several energy storage systems have been investigated and are implemented primar-ily in renewable energy integrated systems. The well developed energy storage systems are;flywheels, hydrogen storage, battery storage, super-capacitors, compressed air energy storage,super-conducting magnetic energy storage and pump hydro-electric storage.

This thesis is concerned with grid connection of a renewable or storage energy sources butdoes not outline its characteristics and nature. Generally the renewable energy sources have astochastic nature and require advanced power electronics control to maintain the power outputas required by the utility standards [4] [9]. In order to be incorporated into the grid certain tech-nical guidelines need to be met before interconnection so that the distributed power sources donot strongly affect the normal operation of network. The proposed system can be implemented

6 CHAPTER 2 BACKGROUND

for any type of energy source which satisfies the general input requirements of the proposedinverter.

2.3 A REVIEW OF GCI TOPOLOGY AND CONTROLLER STRATEGY

The proposed GCI system primarily controls three major parameters; current magnitude, phaseand frequency. Several types of inverter topology and controller strategy have been used for threephase and single phase systems in the past. Synchronization of the systems with the the utilitysupply is a challenging issue. It is often achieved by using DSP or field programmable gate array(FPGA). It adds complexity to the circuit and increases the engineering cost. However, thecomplex digital control ensures a delivery of a good power quality into the grid and intelligentquick controller systems. Various single stage and multi stage GCIs are used. The single stageinverters offer simple structure and low cost but suffer from limited input voltage range, whilethe multi stage inverters are complex, expensive and less efficient [10]. The proposed systemuses a single stage inverter with a full bridge topology and a Single Cycle Controller (SCC)strategy for single phase system.

Several research publications report various topologies and controller strategies for GCI sys-tems. Popular controller strategies implement DQ conversions and real time reference currentregulation. They require a high speed DSP and high performance A/D converters.

A multi functional power electronic converter for DPS has been reported [11]. The convertersystem is assigned to deliver power and acts as an active power compensator in a hybrid com-pensation system for the local network to improve the overall power quality and improve thestability of the power system.

The integration of a STATCOM and battery energy storage has been reported, however, theenergy storage device is small and only able to provide for a short period of time [12]. Thissystem increases flexibility over traditional STATCOM with improved damping capabilities dueto the additional degree of control freedom provided by the active power capabilities.

2.3.1 GCI Topology

In the case of Photo-Voltaic (PV) connected grid systems, inverters are classified into threedifferent families.

1. Central inverter system: This is a single large converter for multiple panels.

2. String inverter system: Multiple inverter connected in series for multiple panels.

3. Module integrated converter system: Each dedicated converter is used for each panel.

Central and string inverter systems are popular at high and medium voltage level with mediumpower capacities up to the ranges of a Megawatt. Module integrated converter (MIC) systemsare used at low power level and offer a plug and play facility for grid connection. The MICconcept provides the potential to connect many dispersed energy sources, but this challengessystem reliability, stability and increases cost.

GCI system topologies can be classified in terms of conversion stages, design specifications andconverter topology. A single stage-inverter is defined as an inverter with only one stage of powerconversion for both stepping up the low DC voltage and modulating the sinusoidal load currentor voltage [10]. Single stage power inverters are classified based on either 4 switch or 6 switch

2.3 A REVIEW OF GCI TOPOLOGY AND CONTROLLER STRATEGY 7

Q1

Q2

Q3

Q4

DC

Q1

Q2

Q3

Q4

Q5

Q6

Figure 2.1 Four switch and six switch buck-boost inverter

topology as shown in Figure 2.1.

Four switch topology is implemented using the DC inputs of two identical boost DC to DCconverters in parallel with the DC source. Each converter is modulated to produce out of phasesinusoidal output with each other [13]. Six switch topology is implementing using two buck-boostDC to DC converters in a four switch bridge with two additional switches used for synchronouscommutation in each half cycle of AC output [14].

A multistage inverter is defined as an inverter with more than one stage of power conversion, inwhich mostly one or more stages accomplish voltage step up or step down or electrical isolationand the last stage performs DC to AC conversion [10].

The MIC topologies have been classified into three different arrangements according to theDC link configuration converter with a DC link, converter with a pseudo DC link and converterwithout a DC link [15].

Converter With a DC Link

The converter system with a DC link has DC to DC and DC to AC power conversion stages asshown in Figure 2.2. The DC side converter is used to control the maximum power from sourceand AC side converter is used to produce AC power with unity power factor. This topology hastwo major disadvantages. The AC side converter requires a PWM control in order to reduce

AC

DC side

Converter

DC Link AC side

Converter

DC Source

Figure 2.2 Converter with a DC link

the harmonic distortion. Both stages of power conversion require high frequency switching ofpower electronics, which increases the switching losses. However, losses can be minimized witha suitable switching topology and for implementing soft switching techniques.


Converter With a Pseudo DC Link

The converter system with a pseudo DC link has a modulated DC to DC converter whichproduces a rectified sinusoidal voltage on the DC link as shown in Figure 2.3. A grid side DC toAC converter with the square wave control converts the link voltage to the AC in unity powerfactor. The major advantage is that the AC side converter operates at the line frequency and asimple low frequency switching can be implemented which reduces high switching losses. Manysingle stage or transformerless GCIs have implemented such topology but they can’t avoid thefollowing drawbacks [16]:

1. The transformerless inverters have limited AC peak voltage that is less than the DCvoltage.

2. The DC voltage range in single stage inverters is more limited than the multiple stageinverters.

3. The dual grounding becomes difficult issue in the transformer less inverters.

AC

DC side

ConverterMains

Frequency

Unfolder

DC Source

Figure 2.3 Converter with a Pseudo DC link

Converter Without a DC Link

The converter system without a DC link has two conversion stages with the DC voltage trans-formed to a higher frequency AC voltage and amplified to a higher level compatible with theAC grid voltage as shown in Figure 2.4. It completely avoids the DC link between conversionstages. This topology requires more sophisticated and higher bandwidth controls as no interme-diate energy storage is present and power conversion can no longer be identified as independentDC to DC and DC to AC conversion stages. This has the advantage of having total powerconversion in two stages only.

AC

Frequency

Converter

DC Source

DC side

Converter

Figure 2.4 Converter without a DC link

2.3 A REVIEW OF GCI TOPOLOGY AND CONTROLLER STRATEGY 9

2.3.2 Current Controller Strategy

In direct grid connected GCI systems, there are generally three types of current controllerproposed in the past; hysteresis current controller, ramp comparison and predictive current con-troller. As the system is directly connected to the grid, the voltage is same as the grid voltage.Hysteresis current control compares load current to the reference current using hysteresis methodas shown in Figure 2.5. This method is simple and robust but the switching frequency dependson the load as shown in Figure 2.6.

Switching

circuit

+-

iordered

imeasured

Q+

Q-

Figure 2.5 Hysteresis current controller

The improved hysteresis controller has been proposed using hysteresis band control methodwhich maintains nearly constant switching frequency, but doesn’t improve the current rip-ples [17].

t

t

i

v

Ton

Toff

Figure 2.6 Hysteresis current control

The ramp comparison controller measures current error and compares to a triangle waveform togenerate switching pulses as shown in Figure 2.7. The PI controller has steady state error andaccurate tuning is hard [18].

The predictive current controller calculates the inverter voltages necessary to force the outputcurrent close to the reference current as shown in Figure 2.8 [19]. But it needs more calculations,a good knowledge of the system parameters as well as a fast DSP.


Switching

circuit

Q+

Q-

iordered

imeasured

+-

-

Figure 2.7 Ramp comparison current controller with hysteresis

HoldSwitching

circuit

Vector to phase

transformation

ierror

K1

K2

iordered

imeasured

+-

-

Q+

Q-

Figure 2.8 Predictive current controller

2.3.3 Converter Topology

Suitable converter topologies include,

1. Half bridge inverter

2. Full bridge inverter

3. Push pull inverter

4. Buck boost converter

5. Flyback converter

6. Cuk converter

7. Zeta converter

8. D2 converter

Half bridge inverters require two equal capacitors in series connection across the DC input witha equal voltage drop across each capacitor. The peak voltage and current ratings of the switchesare same as DC voltage and output AC peak current. This topology is not suitable for highcurrent applications. Full bridge inverters consist of two legs with twice number of switches thanthe half bridge inverter. It gives an output voltage twice than of the half bridge inverter for sameDC voltage input. Thus it is preferred for high power ratings. Push pull converters require atransformer with center tapped primary. The main advantage is that only one switch conductsat any instant of time, which is an advantage for low voltage sources like PV, battery. Thetransformer requires very good magnetic coupling between two half windings in order to reducethe leakage inductance with the two primary windings. For sinusoidal output, the transformermust be designed for fundamental frequency output [20].

2.4 DPS INTEGRATION IN ELECTRICITY DISTRIBUTION SYSTEM 11

The buck-boost topology helps to accommodate wide range of input DC voltages for a sin-gle stage inverter topology. The flyback topology allows electrical isolation. This topology hasthe advantages of being simple and with a small number of switching operations. The flybackhas been used in buck-boost type inverter in several research papers. All CUK, Zeta and D2-converters are fourth order converters and are developed based on the buck-boost convertertopology. The CUK converters require a large reservoir capacitor for high power applicationsto support the full load current. Several topologies have been tried to reduce the size and costof the capacitor in the CUK topology [21]. Zeta converter is made up of two inductors and twocapacitors and is capable of providing continuous current [22]. D2-converter is similar to theCUK converter. Like the CUK and Zeta converters, the D2-converter is capable of producingcontinuous output current, which eases the filter design.

2.4 DPS INTEGRATION IN ELECTRICITY DISTRIBUTION SYSTEM

The GCI is a part of DPS and used for interfacing to the network. The maximum rating of theDPS depends on the voltage level of the distribution networks [23] and short circuit capacityunder maximum fault current condition at the connection points [24].

2.4.1 Low Voltage Grid

The term ”Low voltage grid” generally represents a utility system at distribution level. Thenature of low voltage networks may vary according to the locations, for example rural, urbanand near urban networks. The voltage level in the weaker grid tends to fluctuate more withchanges in load, because loads are connected close to such networks. In comparison with urbanarea networks, rural area networks are more vulnerable to the changes in load. Hence, the lowvoltage networks mainly in rural area described as a weak system. The high voltage and extrahigh voltage networks are considered strong as they pose a smaller impedance and consequentlyare less susceptible to the changes in load.

Generally the system weakness characteristics can be categorized into three different natures.

1. High impedance grid

2. Power impotent grid

3. High harmonics grid

All three characteristics are interrelated. The low voltage grid has high series impedance dueto low voltage level, thinner cable and long transmission as shown in Figure 2.9. In general, itcontains equivalent resistive and reactive components. Upon increasing inductive load, signifi-cant voltage drop occurs in both components of the line. Hence, they require both active andreactive power injection to compensate for the extra voltage drop.

The term ”Power impotent grid” represents a system which is operating at peak load capacity.Any increment in load would result to a drop in frequency and voltage level resulting ultimatelyin a black out.

Weak systems are more vulnerable to high harmonic levels. This will increase energy loss andthe system operating cost. The line voltage distorts due to harmonic current injection fromloads.


E

R jXL

Vgrid

Figure 2.9 Grid series impedance

2.4.2 Grid Interconnection Issues and Options

The integration of small scale GCI at the distribution level may affect network stability andpower quality. Primarily there are three different issues related to DPS interconnections; tech-nical, legal and procedural and tariff issues [26].

Technical issues include safety, power quality, system impacts, islanding etc. The increase inGCIs adds new challenges in electricity distribution networks. Renewable energy technologiespose additional technical challenges. High penetration rates of intermittent GCI poses serioustechnical constraints, which requires some form of back up power or energy storage. Systemstability and reliability of the power supply will be the major issues, which can be addressedwith a suitable injection of reactive and active power to the networks at suitable locations.

2.5 INTERACTION BETWEEN INVERTER AND LOW VOLTAGE GRID

The power grid is a dynamic system. The GCI, while transferring energy to the grid actsdifferently during normal and fault operations of the system. The equivalent circuit of converterconnection to grid is shown in Figure 2.10. Due to inevitable faults like short circuits, generatorislanding etc, the system takes time to regain normal operation. Small scale inverters cannotprovide effective support on a large system during abnormal events, but they need to considerlikely interactions with the design to enable the system stability by the mixed active and reactivepower control. One possible way to analyse the interactions is in terms of time constant, whichcan be divided mainly into four different stabilities.

1. Steady State Conditions (SS)

2. Transient Stability (TS)

3. Voltage Stability (VS)

4. Voltage Waveform Distortion (VWD)

2.5.1 Steady State Conditions

Steady state conditions are a mix real and reactive power flow controls, steady state voltage andpower balance in the system. Droop control helps active and reactive power flow. The proposedinverter features with a mix real and reactive power flow.

2.5 INTERACTION BETWEEN INVERTER AND LOW VOLTAGE GRID 13

R jXL

V 0AC ∟oVinv ∟δ

o

Inverter Grid

Figure 2.10 Inverter grid connection

2.5.2 Transient Stability

Transient stability can be defined as the ability of a power system to recover synchronism afterlarge and sudden disturbances such as a fault, generator and energy storage devices islandingetc. In terms of time constant frame this occurs within a few seconds. The main purpose of TSanalysis is to ensure a return to fundamental frequency during sudden disturbances as quicklyas possible. Upon increasing the number of generators and energy stores into the system, thecomplexity of TS increases. In large power systems, synchronous generator inertial constantsprotect from large variation of frequency on sudden load change or disturbances. The GCIstransferring energy from DC link are inertia-less. However, The power flow controller to regu-late the DC bus voltage will have some degree of filtering and this gives the appearance of ofinertia similar to that seen in a synchronous machine. The GCI can be equipped with extraenergy storage devices such as battery to support the system during TS. Power frequency droopcontrol helps to regain the TS.

The proposed inverter supports active power during underfrequency. The power injection willbe lower from the inverter during overfrequency.

2.5.3 Voltage Stability

Voltage stability is defined as the ability of a power system to maintain steady acceptable volt-ages at all busses in the system under normal operating conditions and after being subjected toa disturbance. The VS mainly occurs in highly inductive network and influences by generatorreactive power and voltage control limitations, load characteristics, system impedance etc. Interms of time constant it occurs for more than half cycle of the fundamental waveform. If thevoltage drop is within limit, a Voltage droop control helps to stabilize the voltage level.

The inverter generates reactive power when AC fundamental voltage is below acceptable leveland absorbs reactive power when high.

2.5.4 Voltage Waveform Distortion

Voltage waveform distortion can be defined as any deviation from the nominal sine waveform ofthe AC line voltage. Harmonic current injection from loadside is a main source of the VWD. Afilter or voltage reinjection circuit can be used to regain a shape of the fundamental waveform.Higher order harmonics due to high frequency switching operation of the inverter may resonatewith the system impedance resulting in voltage distortion. A well designed filter can attenuatehigh frequency components but has an impact on the control bandwidth and the impedance.Various schemes and filter designs have been introduced but a high order filter increases thecomplexity and cost of the overall system [27] [28] [29] .


The proposed GCI uses a generated reference waveform to inject current into the system, thus,even if the system voltage distorted, it injects less harmonic current. This reduces the effect ofharmonics.

The filter impedance is prone to resonate with the dynamic grid capacitance. Hence beforedesigning a filter, it is important to understand dynamic parameters of the network [29]. Largegrid impedance variation in weak systems challenges the control and the grid filter design interms of stability. The impedance variation leads to both dynamic and stability problems in thelow frequency range as well as high frequency range. In the low frequency range, the possiblevariation of the impedance challenges the design of resonance controllers adopted to mitigatethe effect of the grid harmonic voltage distortion on the grid current. In the high frequencyrange the grid impedance influences the frequency characteristics of the filter and the design ofpassive or active damping becomes more difficult [30] [31].

2.6 POWER FLOW

The inverter power capability mainly depends on the DC side voltage, filter impedance andthe grid voltage. The DC side voltage is generally kept constant through a PI controller, con-sequently all the real power coming into the DC link is instantaneously transferred into the grid.

When the generator power increases, the capacitor voltage increases. The GCI should forcemore power to the grid to keep the capacitor voltage level fixed. If the generator power is notenough to charge up the capacitor, the grid supports power to the input side. The proposedsystem is designed to control bi-directional power flow. The proposed inverter connection togrid is shown in Figure 2.11. For unity power factor operation the inverter works in Buck mode.

AC Grid

DC

Sourc

e

Q1

Q2

Q3

Q4

D1D3

D2D4

VAC

50Hz

VgC

jXL

Filter

+

-

Vinv

R

jXLGRG

Figure 2.11 Inverter connection to grid

This requires the DC side voltage to be greater than the peak of the grid voltage.

During non unity power factor operation, the inverter operates in both buck and boost mode.During boost mode, the AC voltage supplies current to the DC side. This is possible due tofour quadrant operation of the inverter.

2.7 CONCLUSION

The integration of distributed power sources into a weak distribution network is challengingin order to maintain stability and power quality. The chapter gives a brief overview of thedevelopment in the converter and its classifications, distributed power sources and problemsrelated to the energy integration into power grid. A number of inverter topologies are presented

2.7 CONCLUSION 15

and classified according to applications, power conversion stages, power level etc. Low powerconverters with plug and play facility at residential mains voltage level are increasing rapidly.Power qualities issues such as poor voltage regulation, harmonic distortions and voltage dip arecommon in the low voltage networks. More research is required on the low power scale converterto augment the performance of weak networks with the maximum utilization of distributedpower sources.

Chapter 3

SINGLE CYCLE CONTROL

3.1 INTRODUCTION

Single Cycle Control (SCC) is a dynamic switching technique employed in a power electronicsconverter for voltage or current control using Pulse Width Modulation (PWM) [6]. This is ageneral method based on integration of a voltage or current in order to force its average valueto some control reference signal. It has been identified as a simple technique for current con-trol and has already been proposed as a potential technique for control of converters in gridinterconnection applications [32]. The control theory has already been tested for controllingthree phase PFCs, APFs, STATCOMs [33]. It avoids the use of complex circuitry and digitalsignal processors for control applications which not only reduces complexity but also makes itcheaper and faster. It is easier to implement in hardware and requires few analogue and logiccomponents. With simple engineering, it can be implemented anywhere with locally availablecomponents at a fairly cheap price. The controller is used to control the inverter output current

DC

signal

Resettable

integratorAdder

Current

control

signal

ComparatorLatch

logicPower

switch

control

Reset

integrator

Current

Figure 3.1 Controller block diagram

at constant switching frequency and the method forces the output current waveform to matchthe reference voltage. This makes it easy to synchronize with the grid at unity power factor. TheSingle Cycle Controller method is also implemented for reactive current control in the proposedinverter. A block diagram for the Single Cycle Controller is shown in Figure 3.2

This chapter explains the Single Cycle Controller and presents output current magnitude, shapeand phase control methods. The basics of Single Cycle Control theory is explained in section3.1. The implementation of the controller for constant switching frequency and the controlleroperation are introduced in sections 3.3 and 3.4.

18 CHAPTER 3 SINGLE CYCLE CONTROL

3.2 BASICS OF SINGLE CYCLE CONTROL THEORY

The aim of Single Cycle Control is to adjust the duty ratio of the power switches in real timesuch that the average value of the current waveform at the switch is exactly equal to the controlreference on each switching cycle. This switching method can be implemented for constant ontime switching, constant off time switching, constant frequency switching and variable switch-ing frequency for power converter applications [6]. Constant frequency switching is chosen.

The SCC requires two instantaneous reference signals at two stages as shown in Figure 3.2.The first reference signal is taken from grid voltage or equivalent generated signal v(t) which hasa similar shape as and is synchronized with the grid voltage. The shape of the reference voltagesignal v(t) will define the shape of the output current io(t) injected into the grid. The secondreference signal is taken from real time output current which is flowing through the inductor inseries with the inverter output. The measured reference current i(t) signal is scaled for a givenpower level.

i(t)

+

+

XLogic output

to latch

-vm(t)

|v(t)|

v(t)

|i(t)|

y(t)

Reset

Figure 3.2 SCC signal flow block

Let the input signal X be steady as shown in Figure 3.3. Assume that the X is integratedand reset at much higher frequency than the grid fundamental frequency. The real time in-tegrator starts working exactly at the time when a power switch is turned on. The real timeintegrated output is −vm(t). The negative sign represents vm(t) is falling. The −vm(t) is addedto the absolute scaled AC voltage signal v(t). Suppose the effective time varying output afteraddition is y(t). The y(t) is compared with the scaled absolute inverter output current i(t) inreal time. At the instant when the added signal meets the current signal, the switch is turnedoff . At the same time, the controller resets the integrator and the process will repeat in thenext switching cycle. Any perturbations in control signal X or reference signal v(t), will changethe output current instantly in each cycle.

Let ton, toff and D(t) be turn on, turn off time and duty cycle respectively for a total switchingperiod T . Hence, ton = D(t)× T

y(t) = v(t)− 1T

∫ t

0x(t)dt (3.1)

The output y(t) is compared with the reference signal i(t) instantaneously. In each switchingcycle, the switch turn off instant is based on signals y(t) and i(t). The switch is off when

y(t) = i(t) (3.2)

3.2 BASICS OF SINGLE CYCLE CONTROL THEORY 19

X

- (t)νm

| |ν(t)

| |i(t)

y(t)

Switching

logic

t

t

t

t

t

t

| |i(t)

Figure 3.3 Single Cycle Control signals

Equation 3.2 shows that the output current is function of the reference voltage signal v(t) andthe input control signal X for a constant load. The power switches are controlled so that theyturn on at the start of the integration period. The current i(t) rises and the calculated y(t)falls, and the switches turn off when the signals are equal. In this way, the current magnitudetracks the same shape as the voltage v(t), but to a smaller value dependent on the slope of theintegrator X.

3.2.1 Current Magnitude Control

The slope of the integrator output depends on the amplitude of signal X. Any perturbations insignal X would change the real time slope of the integrator output −vm(t). A higher value ofX increases the slope of the −vm(t), which reduces the peak current in each switching cycle.

Suppose reference signal v(t) is fixed for a switching period T , and the input DC signal X1

has slope −X1 as shown in Figure 3.4. When the input signal increases from X1 to X2, the cor-responding slope increases from −X1 to −X2 and the inductive current rises for a shorter time,reducing the average output current. Let Ioav1 and Ioav2 be average output currents for inputsignals X1 and X2 respectively. Hence, the average output current Ioav reduces in proportion tothe integrator input signal X, assuming other parameters constant.

Ioav ∝ (1−X(t)) (3.3)


Ioav1

Vo

Ioav2

T0

X1

X2

t

i(t)

Figure 3.4 Current at variable x(t) and fixed v(t)

3.2.2 Current Shape Control

The reference voltage signal v(t) provides the starting point for the −vm(t). A high amplitudeof v(t) allows more time for the current rise before y(t) = v(t)− vm(t) meets i(t) and the powerswitch turns off. The output current magnitude is directly proportional to the magnitude ofv(t), which adjusts the converter current shape.

Ioav2

Ioav1

vo2

vo1

T0

X2

X1

t

i(t)

Figure 3.5 Current at fixed x(t) and variable v(t)

Suppose X is fixed for a switching period T , the reference voltage signal v(t) is reduces fromvo1(t) to vo2(t) as shown in Figure 3.5. The integrator slope is the same but the current rise timedecreases, reducing the average output current. Let, Ioav1 and Ioav2 be average output currentfor input vo1(t) and vo2(t) respectively. Hence, the average output current Ioav is proportional

3.3 CONTROLLER 21

to the reference voltage v(t) assuming remaining parameters are constant.

Ioav ∝ v(t) (3.4)

3.2.3 Current Phase Control

As the current shape is proportional to the v(t), with a suitable phase reference, the outputcurrent phase can be adjusted with respect to the grid voltage as shown in Figure 3.6. A newreference waveform is generated synchronized with the grid voltage with a capability of phaseand magnitude variation. The phase angle is adjusted according to the need of reactive currentinjection or absorption by the inverter. The maximum reactive current injection has a limit, asit supports active power at the same time.

Grid voltage

Grid injected current

Phase

angle

v(t)

Figure 3.6 v(t) as leading phase angle

3.3 CONTROLLER

The SCC controller is mainly comprised of a resettable integrator, adder, comparator and SRlatch as shown in Figure 3.7.

X

|v(t)| |i(t)|

Comparator

Oscillator

Driving signal

R1

C1

Adder

Resettable

integrator

Switch

SR latch

Figure 3.7 Single Cycle Controller

Here, vo(t) = inverter output voltage, D(t) = duty ratio.

The control signals are v(t) = k × vo(t) and i(t) = Rs × io(t).

k represents AC voltage scaling factor and Rs represents a current sensing resistance which


is used to scale the output current for control purposes.

The converter has a average output voltage over a single switching period,

vo(t) = Vg ×D(t) (3.5)

Here Vg is the inverter input DC voltage. During turn on time, the maximum voltage that the

Ton

T

R i (t)s* o

k*v (t) - v (t)o m

-vmax

-v (t)m

t

t

switchingpulses

Figure 3.8 Controller operation waveform

integrator output voltage can fall, vmax, can be written as Equation 3.6.

vmax =X

R1 × C1× T (3.6)

Where T is a total switching period. The integrator time constant, R1 × C1 ≤ T .

Referring to Figure 3.8, the measured output current flowing through the current sensing resistorRs, is compared with the (k ∗ vo(t) − vm(t)) in each switching cycle. The Equation 3.7 is thecondition to turn off the power switch. Then current starts falling until next cycle.

Rs × io(t) = k × vo(t)− vm(t) (3.7)

Where k is a constant and vm(t) is the voltage fall before the integrator is reset. As shown inFigure 3.8, vmax is the maximum voltage that can fall in each cycle. Thus vm(t) from equationcan be described by Equations 3.8 and 3.9.

vm(t) = −vmax × t

Tfor t ≤ D(t)T (3.8)

vm(t) = 0 for t ≥ D(t)T (3.9)

3.4 CONTROL PROCESS IN CIRCUIT 23

3.3.1 Input Parameter Relation for Current Control

X can be controlled to adjust peak of the output current io(t). Equation 3.7 can be used toadjust the controller parameters for regulating the peak current. The output current has ripple,hence the peak doesn’t give the true power flow into the grid. But by reducing the ripple,the power flow can be regulated optimally by satisfying Equation 3.7. The ripple depends oneffective switching frequency of the converter, inductor and integrator time constant. Mainlythere are two ways to control the peak of current magnitude.

1. The control signal X.

2. Active and reactive current control by adjusting the phase and amplitude of the v(t).

Referring to Equation 3.7, the output current peak in each switching cycle can be written asEquation 3.10.

io(t) =1Rs

(k × vo(t)− vmax ×D(t)) (3.10)

Smaller ripple gives higher power for the same peak current. The instantaneous power at unitypower factor can be estimated by the Equation 3.11 for very low current ripple.

Po(t) = vo(t)× io(t) =vo(t)Rs

(k× vo(t)− vmax×D(t)) =vo(t)Rs

(k× vo(t)− X × T

R1 × C1

vo(t)Vg

) (3.11)

Referring Equation 3.5, 3.6 and 3.11, the output power can be represented by Equation 3.12.

Po(t) =v2o(t)Rs

(k − T

R1 × C1

X

Vg) (3.12)

k controls the maximum power flow. Upon increasing X, the power level decreases. When Vg

increases, the current magnitude increases again. Hence the DC control signal X is a functionof DC voltage, while increasing Vg, the control signal X should be decreasing to increase thepower injection into the grid.

1

v(t)

i(t)

t

Figure 3.9 Current and voltage signals at the input of comparator

3.4 CONTROL PROCESS IN CIRCUIT

The integrated voltage output −vm(t) Equation 3.9 is added to the absolute reference AC volt-age v(t). The result (k × vo(t)− vm(t)) is now compared with the absolute measured referencecurrent signal i(t) as shown in Figure 3.9. While current is smaller, the switches are such thatconverter current is rising. Similarly, for higher current level, integrator resets and power switch


turned off . The stored inductive energy decays with negative current slope on each switchingcycle. The simulated voltage and current waveforms are shown in Figure 3.10.

Increasing X will increase the slope of −vm(t) and reduces the current io(t) rise time beforeit meets (k× vo(t)− vm(t)), which lowers the average output current and ultimately reduces thepower flow.

0.071 0.073 0.075 0.077

Integrator output

Integrator

reset

Driver

control

Latch

reset

Oscillator

1

1

1

1

1

0

0

0

0

Time (sec)

0

Figure 3.10 Logic sequence and operation of SCC

The comparator and oscillator output are given to the Reset and Set pin of the SR latchas shown in Figure 3.7. The truth table for the SR latch is shown in Table 3.1. The output of

Reset (R) Set (S) Q Q′

0 0 Don’t Care Don’t Care0 1 1 01 0 0 11 1 unknown unknown

Table 3.1 SR latch truth table

latch (Q) is used to drive the power switches. The inverting output of Q i.e. Q′ is used to resetthe integrator. Hence, whenever the IGBT is turned off the integrator resets instantly.

The whole process for the Single Cycle Controller can be realized as shown in Table 3.2. Herei(t) is absolute measured value of current (Rs × io(t)) and (k × vo(t) − vm(t)) is the differencebetween absolute reference voltage signal and integrator output voltage on each cycle.

3.5 CONCLUSION 25

Comparator R S Q Q′ Integratori(t)<(k × vo(t)− vm(t)) 0 0 Don’t Care Don’t Care Continue (Integration or Reset)i(t)<(k × vo(t)− vm(t)) 0 1 1 0 Integratingi(t)>(k × vo(t)− vm(t)) 1 0 0 1 Reseti(t)>(k × vo(t)− vm(t)) 1 1 Not used Not used Not used

Table 3.2 SCC logic sequence

3.5 CONCLUSION

The Single Cycle Controller is an easy switching technique and suits for the power electronicsconverter control particularly for the grid connected applications. It can synchronize with thegrid voltage as it forces the inverter output current to follow the reference voltage waveform. Asthe controller uses real time current for switch control, it increases the transient response of thecircuit. The basis of Single Cycle Controller and its implementation in the circuit are explained.The simulation of the controller shows promising results from a handful of components avoidingany complex circuitry and numerical calculations.

Chapter 4

SWITCHING LOGIC FOR SINGLE CYCLE CONTROL

4.1 INTRODUCTION

A current controlled voltage source inverter is used. The inverter is directly connected to thegrid. Different switching strategies for a full bridge inverter are given. The development ofswitching logic and Boolean equations are presented. Full bridge operation in the four quadrantvoltage-current plane is described. A limitation for the Single Cycle Controlled H-bridge duringboost mode is discussed.

4.2 CONVERTER TOPOLOGY

A simple single phase H-bridge inverter switch topology is used as shown in Figure 4.1. It iscapable of driving high current at low voltage, hence is popular in medium power and photo-voltaic (PV) applications. It has high efficiency. The other desirable features are high powerdensity, high reliability and low electromagnetic interference (EMI) [36]. This topology allowsflexibility to use the inverter in both two-quadrant (2Q) and four-quadrant (4Q) operation inthe output voltage-current plane. 4Q operation allows bidirectional power flow and offers morecontrollability over the output voltage and current. This topology is implemented in hardwarebecause of its simple structure and simple controllability.

Q1

Q2

Q3

Q4

D1D3

D2D4

v (t)o

50Hz

+

-v (t)inv

jXLR

CVg

+

-

Figure 4.1 Full bridge inverter

The drawback for the simple H-bridge topology is that it operates with hard switching, whichreduces its efficiency at high switching frequency. Soft switching techniques such as zero voltageswitching and zero current switching can be used to reduce the switching losses. However, theseadd more passive components and increase the complexity. To keep it simple, the switchingstrategy is designed in such a way that minimizes the switching losses, which will be describedlater.

28 CHAPTER 4 SWITCHING LOGIC FOR SINGLE CYCLE CONTROL

IGBTs are chosen as the power switches, which have a low conduction loss at high powercapability and operate best at less than 100KHz switching frequency. The switching frequencyis chosen to be much higher than the fundamental frequency.

4.3 CONVERTER SWITCHING STRATEGY

The proposed switching strategy aims to increase the efficiency of the inverter with a simple logicimplementation. There are three pulse width modulation (PWM) methods based on a switchingfrequency triangular waveform are popularly being used for the switching of full bridge inverter.

1. Unipolar Pulse Width Modulation (UPWM)

2. Bipolar Pulse Width Modulation (BPWM)

3. Hybrid Pulse Width Modulation (HPWM)

4.3.1 Unipolar Pulse Width Modulation

UPWM controls the two legs of the single phase inverter independently. The switching PWMsignals are generated by comparing a switching frequency triangular waveform with two controlvoltage signals for the two legs of the inverter. The advantage of UPWM is that the effectiveswitching frequency of the output voltage is doubled, which reduces the ripple of the outputcurrent. The prospective inverter output voltage after UPWM is given in Table 4.1 for differentswitch states. The switches operating at high frequency switching are referred as SW frequencyin the table.

High side Low side Prospective voltageQ1 Q3 Q2 Q4 Vinv

SWfrequency SWfrequency SWfrequency SWfrequency

on off off on +Vg

off on on off -Vg

on on off off 0off off on on 0

Table 4.1 UPWM switching options

4.3.2 Bipolar Pulse Width Modulation

BPWM controls the switches of the two legs simultaneously. The switching PWM signals aregenerated by comparing a switching frequency triangular waveform with one control voltageand one of the switch pairs always remains on in each leg. The effective switching frequency ofthe output voltage is same as the triangular waveform. Hence, the ripple of the output currentis higher than the UPWM switching strategy. The inverter prospective output voltage for theBPWM is given in Table 4.2 for different switch states.

4.3.3 Hybrid Pulse Width Modulation

HPWM controls the two switches connected to the negative rail at the fundamental frequency,and selectively controls one or other of the switches connected to the positive rail at the switch-ing frequency. Only one switch is ever switched at the switching frequency at any time. For

4.4 SWITCHING LOGIC CIRCUIT DEVELOPMENT 29


SWfrequency SWfrequency SWfrequency SWfrequency

on off off on +Vg

off on on off −Vg

Table 4.2 BPWM switching options

example, one switch pair Q1 and Q4 are on at positive half cycle and another switch pair Q3

and Q2 are on at negative half cycle. Moreover, only one of the switch pairs operates at theswitching frequency and the another is controlled at the fundamental frequency [37], whereasboth the UPWM and BPWM control all switches at the switching frequency. This methodreduces the high frequency switching losses, which offer some benefits for the hard switchingfull bridge inverter. It offers another advantage that the prospective output voltage is similar tothe UPWM switching strategy, however it loses the frequency doubling effect of the UPWM. Asimilar strategy is also called UPWM switching because the HPWM and UPWM generate theidentical output voltage [38]. The inverter prospective output voltage for the HPWM is givenin Table 4.3 for different switch states. The switches operating at fundamental frequency arereferred as Fund frequency in the table.


SW frequency SW frequency Fund frequency Fund frequencyon off off on +Vg

off on on off -Vg

on on off off 0off off on on 0

Table 4.3 HPWM switching options

The UPWM has less Total Harmonic Distortion (THD) and a lower distortion factor thanthe BPWM for single phase voltage source inverter [35]. The HPWM is chosen for hardwareimplementation because of its identical wave shape of inverter output voltage with the UPWMand lower switching losses.

4.4 SWITCHING LOGIC CIRCUIT DEVELOPMENT

Simple digital logic has been developed to implement a switching strategy in the controllercircuit. The parameters used for the logic development are the voltage polarity, current directionand switching states. The voltage polarity and PWM switching states are used for the switchinglogic development in 2Q operation while current direction is also considered for the 4Q switchingoperation. The voltage polarity and current direction for 4Q operation are considered as shownin Figure 4.2 and 4.3 respectively.Decision making conditions for the logic circuits are defined as listed below.

1. Positive voltage, positive current


t

+ v(t), - i (t)o - v(t), + i (t)o

+ v(t), + i (t)o

- v(t), - i (t)o

Figure 4.2 Current lagging waveform

t

+ v(t), - i (t)o - v(t), + i (t)o

+ v(t), + i (t)o

- v(t), - i (t)o

Figure 4.3 Current leading waveform

2. Negative voltage, negative current

3. Positive voltage, negative current

4. Negative voltage, positive current

The logic used for the voltage polarity, current direction and switching states of the powerswitches is summarized in Table 4.4.

Voltage polarity Logic representationv+ve 1v−ve 0Current direction Logici+ve 1i−ve 0Switch state Logicon 1off 0

Table 4.4 Logic development rules

Boolean equations are developed for each different switching strategy and implemented in thePSCAD simulation. The terminology used in the development of Boolean equations is definedin Table 4.5.

4.4 SWITCHING LOGIC CIRCUIT DEVELOPMENT 31

Terminology DefinitionSW On/Off at high switching frequencyon Stay On for half cycleoff Stay OFF for half cyclev AC voltagevg DC voltagei Inverter output current

Table 4.5 Terminology used in development of Boolean equations

4.4.1 HPWM Switching Strategy

First and second switching methods tested in HPWM switching strategy for 2Q and 4Q opera-tion.

First Switching Method

Only one switch operates at switching frequency at any time. During positive half cycle Q1 isswitching, Q4 is on and Q3, Q2 are off . During negative half cycle, Q3 is switching, Q2 is onand Q1, Q4 are off .

First switching logic (HPWM)Two quadrant operation Four quadrant operation Prospective voltage

Boolean equations: Boolean equations:Q1 = v × SW Q1 = v × i× SW

+Vg, 0, − VgQ2 = v Q2 = v × i× SW

Q3 = v × SW Q3 = v + i× SWQ4 = v Q4 = v + i× SW

Table 4.6 Boolean equations in first switching method

In 4Q operation during positive voltage and negative current Q2 is switching, Q4 is on andQ1, Q3 are off . During negative voltage and positive current Q4 is switching, Q2 is on and Q1,Q3 are off . The Boolean equations for switching are given in Table 4.6.

Second Switching Method

Second switching method only provides 2Q operation. Only two switches are operating atswitching frequency in each half cycle. During positive half cycle Q1 and Q2 are operatingalternatively at the switching frequency, Q4 is on and Q3 is off . During negative half cycle,Q3 and Q4 are operating alternatively at the switching frequency, Q2 is on and Q1 is off . Theswitching Boolean equations are given in Table 4.7.

4.4.2 Bipolar Switching Strategy

The third and fourth switching methods are BPWM switching strategy.


Second switching logic (HPWM)Two quadrant operation Prospective voltage

Boolean equations:Q1 = v × SW

+Vg, 0, − VgQ2 = v + SWQ3 = v × SW

Q4 = v + SW

Table 4.7 Boolean equations in second switching method

Third Switching Method

All four switches operate at switching frequency diagonally but only two at a time. When Q1,Q4 are switching, Q3, Q2 are off . When Q3, Q2 are switching, Q1, Q4 are off . The Booleanequations for third switching method are given in Table 4.8.

Third switching logic (BPWM)Four quadrant Operation Prospective voltage

Boolean equations:Q1 = v × SW + v × SW

+Vg, − VgQ2 = v × SW + v × SW

Q3 = v × SW + v × SW

Q4 = v × SW + v × SW

Table 4.8 Boolean equations in third switching Method

Fourth Switching Method

Only two switches operate at switching frequency at each half cycle diagonally in this switchingmethod. In both 2Q and 4Q operations, during the positive half cycle Q1, Q4 operate at switch-ing frequency and Q3 Q2 are off . During the negative half cycle Q3, Q2 operate at switchingfrequency and Q1, Q4 are off .

In 4Q operation, during positive voltage and negative current Q2, Q4 operate at switchingfrequency and Q1, Q3 are off . During negative voltage and positive current Q4, Q2 are oper-ating at switching frequency and Q1, Q3 are off . The switching Boolean equations for eachswitch are given in Table 4.9.

4.5 SELECTION CRITERIA OF SWITCHING STRATEGY

The switching strategy selection depends on various criteria. The primary criteria consideredfor the proposed inverter are listed as follows.

1. To improve the current performance during zero-crossings.

4.6 CONVERTER FOUR QUADRANT OPERATIONS 33

Fourth switching logic (BPWM)Two Quadrant Operation Four Quadrant Operation Prospective voltage

Boolean equations: Boolean equations:Q1 = v × SW Q1 = v × i× SW

+Vg, − VgQ2 = v × SW Q2 = i× SWQ3 = v × SW Q3 = v × i× SWQ4 = v × SW Q4 = i× SW

Table 4.9 Boolean equations in fourth switching method

2. To reduce the switching losses.

3. To enable bidirectional power flow.

4. To ease implementation in the circuit.

The HPWM first switching method decreases switching losses due to only one switch operatingat high frequency at any time. Current zero crossing performance for each strategy is comparedin Chapter 5. The current is less distorted during zero crossings in this strategy. Thus theHPWM first switching strategy is implemented in hardware.

Q Switching1Q Switching2

Q Switching3 Q Switching4

Q on4Q on4

Q on2 Q on2

Q , Q off2 3Q , Q off1 3

Q , Q off1 3Q , Q off1 4

III

III IV

v (t)o

i (t)o

III

III IV

v (t)o

i (t)o

Q Switching1

Q Switching4

Q , Q off2 3

Q Switching2

Q Switching4

Q , Q off1 3

Q Switching3

Q Switching2

Q , Q off1 4

Q Switching4

Q Switching2

Q , Q off1 3

Figure 4.4 4Q operation 1.HPWM 2.BPWM

4.6 CONVERTER FOUR QUADRANT OPERATIONS

The H-bridge inverter from Figure 4.2 can be decoupled into four different circuits representingdifferent quadrants operation of the voltage-current plane. Figure 4.4 shows 4Q switching forHPWM and BPWM. The inverter operates in buck mode during first and third quadrants, thusthe voltage polarity and current direction will always be the same. It operates in boost modeduring second and third quadrant operations. The 4Q operation as shown in Figure 4.4 allowsmore options for control of the voltage and current. With little additional logic 4Q can beimplemented.


4.6.1 Buck Mode

The inverter works in buck mode during first and third quadrants operation. Figure 4.5 showsequivalent circuit for buck mode operation. The current flows from DC side to AC.

The AC voltage polarity is positive in first quadrant. Q1 is switching, Q4 is on and diodeD2 is active. The voltage polarity is negative in third quadrant. Q3 is switching, Q2 and D4 areon.

v (t)o

i (t)oR L

D2

Q1

Vg

v (t)o

i (t)oLR

D4

Q3

Vg

Figure 4.5 Equivalent buck circuit for 1. First quadrant 2. Third quadrant

4.6.2 Boost Mode

The inverter works in boost mode during second and fourth quadrant operation of voltage cur-rent plane. Figure 4.6 shows equivalent circuit for boost mode operation. The current flowsfrom AC voltage to DC side.

The voltage polarity is positive during the second quadrant. Q2 is switching, Q4, D4 andD1 are on. The voltage polarity is negative during the fourth quadrant. Q4 is switching, Q2,D2 and D3 are on.

Q2v (t)o

i (t)oRL

D1

Vg

v (t)o

i (t)oLR

D3

Q4

Vg

Figure 4.6 Equivalent boost circuit for 1. Second quadrant 2. Fourth quadrant

4.6.3 Constraints During Boost Operation

During buck mode, the H-bridge operates in continuous current conduction. During boost mode,near zero crossing of voltage waveform, the inverter operates in discontinuous current conduction,as the inductor can not store enough energy during the on period and the inductor de-energizestoo quickly during the off period.

Prior to disruption of the SCC in boost mode, the latch set and reset occur at the same time.The switch is turned off and the current ramps down for longer (at 0.069s in Figure 4.7), as the

4.7 CONCLUSION 35

falling integrator output is unable to meet current within a cycle. Then the integrator is reset (at0.0695s) after two complete switching cycles. Consequently switching frequency appears halvedduring the period and distorts the output current for few switching cycles. After the few switch-ing cycles , the controller regains its control. The logic to avoid the same level state in set andreset does not improve the disturbance in boost mode. The logic needs to be extended to resetthe integrator using an external signal during disrupted cycles only. The distorted current andmissed switching logic during the discontinuous operation of the inverter is shown in Figure 4.7.

0.5

00.0685 0.069 0.0695 0.07 0.0705

1

0

0.0685 0.069 0.0695 0.07 0.0705

1

00.0685 0.069 0.0695 0.07 0.0705

Time (sec)

Latc

h s

et

QReset pulse Control signal Current

Figure 4.7 Current distortion during boost mode

The current waveform can be improved by increasing the inductor size or increasing a timeconstant of the integrator. The increasing of inductor size is not practicable. The inverter cur-rent is tested at different integrator time constants during buck and boost mode operations. Ithelps to regain the current waveform during boost mode at larger time constants of the integra-tor, but the time constant is always smaller than the switching frequency.

Another possibility is to change the inverter topology to augment the performance during boostmode. Finding a suitable inverter topology could be considered for future work.

4.7 CONCLUSION

A simple H-bridge inverter topology is used. Different switching strategies and their logic de-velopment for the full bridge inverter are described. The hybrid PWM switching is suitableto reduce switching losses and increase the inverter efficiency. The current direction and volt-age polarity are used to develop the logic sequence for the inverter switching in four quadrantoperation. The inverter operation in each quadrants is described. The Single Cycle Controllermalfunctions during reactive current flow due to discontinuous current operation of the H-bridge.This requires more study to develop a better topology or switching or Single Cycle Control strat-egy to improve the current performance during boost mode. Finally, the hybrid PWM switchingstrategy (first switching method) for 4Q operation is implemented in the hardware.

Chapter 5

SINGLE CYCLE CONTROL CURRENT WAVEFORM

5.1 INTRODUCTION

Single Cycle Controlled output current waveform depends upon various factors, for exampleshape of the current ordered AC signal, integrator slope, inductance, DC and grid voltages.The real time inductor current is used to control the duty cycle of the power switches.

The Single Cycle Controlled current has zero crossing distortion. However, a switching strategywith minimum distortion is used in hardware. An optimum approach is described to operatethe inverter in unipolar mode for most of the AC cycle and to operate in bipolar mode nearzero crossings [38]. Unipolar PWM and bipolar PWM switching strategies are not used in theproposed inverter due to high switching losses in compare to hybrid PWM.

This chapter describes the current zero-crossing wave shape for different hybrid PWM andbipolar PWM switching strategies. The current harmonic spectrum is presented. Finally, alogic circuit is presented to fix this issue.

i (t)rip

(V -g v (t))/Lo

Ioav

v(t) = k × v (t)o

t = 0

-x1

i (t)min1

i (t)min2

i (t)max

D(t)T (1-D(t))T

T

-v (t)/Lo

Figure 5.1 Current control in one switching cycle

38 CHAPTER 5 SINGLE CYCLE CONTROL CURRENT WAVEFORM

5.2 CURRENT CONTROL

Figure 5.1 illustrates current control using the SCC for one switching cycle. Suppose Vg andvo(t) are DC source and AC supply voltage respectively. When the switch turns on, the currentstarts from imin1(t) with a slope of Vg−vo(t)

L until the integrator is reset. When the switch turnsoff , the current falls from imax(t) to imin2(t) with a slope of −vo(t)

L . The current level imin1(t)and imin2(t) are different. The shape of average current ioav is expected to be close to that ofv(t). Peak to peak ripple current irip(t) depends on the voltage difference between Vg and vo(t),which is bigger when vo(t) is low and smaller when vo(t) is high.

5.3 ZERO-CROSSING CURRENT

The voltage across the inductor vL(t) in the circuit shown in Figure 5.2 is the difference betweenVg and vo(t).

L

v (t)o

50Hz

v (t)L

i (t)o

+

-

Vg

Sw

itch

es

Figure 5.2 Power circuit

The waveforms for Vg, vo(t) and vL(t) are shown in Figure 5.3 for the HPWM first switch-ing method.

Vgv (t)o

v (t)L

s

-v (t)o

Figure 5.3 vL(t), Vg, vo(t) for HPWM first switching method

vL(t) defines the change in current with respect to time, diodt , flowing through the inductor.

Figure 5.4 illustrates that during beginning of the fundamental cycle, when vo(t) is low, the risein output current dio

dt through the inductor is high. Similarly, when vo(t) is high, the rise ininductor current is small. For half fundamental cycle, the switch duty cycle increases from 0o

to 90o and falls from 90o to 180o. Hence the dio,rise

dt is high and dio,fall

dt is slow around the AC

voltage zero-crossings and the dio,rise

dt is slow and dio,fall

dt is high around the voltage peak.

5.3 ZERO-CROSSING CURRENT 39

di /dto,rise

0.061

di /dt >o,fall di /dto,risedi /dt <o,fall

Time (sec)

0.062 0.063 0.064 0.065 0.066 0.067 0.068 0.0690

3.5

Curr

ent,

A

Figure 5.4 Current ripple for HPWM first switching method

The current falls slowly when vo(t) is near zero. Consequently the current falls more slowlythan the voltage and the zero-crossing is delayed.

The current performance for different switching strategies is summarized in each subsection.The switches Q1, Q2, Q3, Q4 and diodes D1, D2, D3, D4 mentioned in subsections are referredto the bridge inverter as shown in Figure 4.2.

5.3.1 HPWM Switching Strategy

The switching operation is already descibed in Chapter 4. The current performance for eachmethod is given.

First Switching Method

The current shape is identical in 2Q and 4Q operation. AC supply voltage and current wave-forms near zero crossing are shown in Figure 5.5. In the positive half cycle, this provides inverterterminal voltages of +Vg and 0. In the negative half cycle, this provides inverter terminal volt-ages of −Vg and 0.

Current scale = 0.1

Voltage scale = 1

Voltage zero

Current zero

10

0

-10

Outp

ut

Volt

age (

V),

Curr

ent

(A)

Time (Sec)

0.0685 0.069 0.0695 0.07 0.0705 0.071 0.0715

Figure 5.5 Grid voltage and output current near zero crossing for 2Q first switching method (HPWM)

Prior to the zero crossing of positive half voltage and current, the switch Q1 is turn off . Butinductor current keeps flowing through the switch Q4 and diode D2 with an exponential decayand delays the current zero. As soon as the negative voltage starts, current drops to zero steeplyand flows through the switches Q3 and Q2.


Second Switching Method

In the positive half cycle, this provides inverter terminal voltages of +Vg and 0. In the negativehalf cycle, this provides the terminal voltages of −Vg and 0. The output current and voltage

0.069 0.0695 0.07 0.0705 0.071 0.0715

Time (sec)

-10

Voltage zero

Current zero

Current scale = 0.1

Voltage scale = 1

Ou

tpu

tV

olt

ag

e (

V),

Cu

rren

t (A

)

0.0685

-20

0

10

20

Figure 5.6 Grid voltage and output current near zero crossing for 2Q second switching method (HPWM)

waveforms during zero crossing are shown in Figure 5.6. It has worse current waveform duringthe zero crossings. The current fall is slower than the voltage. When the switches Q3 and Q2 areoff , the positive current flows through the switch Q4 and diode D2. After the negative cyclestarts, the positive current keep flowing through the switch Q4 and diode D2 instead of goingto the negative direction. It requires extra logic to turn off the Q4 or Q2 immediately beforethe next cycle starts to fix the problem.

5.3.2 Bipolar Switching Strategy

The inverter operation in bipolar switching strategy is described in chapter 4.

Third Switching Method

For full cycle, the switches Q1, Q4 and Q3, Q2 operate at the PWM switching frequency diago-nally. In both half cycles, this provides inverter terminal voltages of +Vg and −Vg.

0.07

Time (sec)

-4

Voltage zero

Current zero

Ou

tpu

tV

olt

ag

e (

V),

Cu

rren

t (A

)

0.0685 0.069 0.0695 0.0705

Current zero

0.071

-2

0

2

4 Voltage scale = 1

Current scale = 0.1

Figure 5.7 Grid voltage and output current near zero crossing for third switching method (BPWM)

This allows reduction of stored inductor energy quickly. Prior to zero crossing of the volt-age, negative current flows through the inductor. The controller senses the absolute value ofcurrent. When the negative half cycle starts, the switches Q3 and Q2 are on, which add morenegative current resulting undesirable high current for a short period. The output current andvoltage waveforms during zero crossing are shown in Figure 5.7.

5.4 CURRENT HARMONICS 41

Fourth Switching Method

The current shape is similar in 2Q and 4Q operation near zero crossings. The output current and

0.0685 0.069 0.0695 0.07 0.0705 0.071 0.0715

Time (sec)

Current zero Voltage zero

Current zero

Outp

ut

Volt

age (

V),

Curr

ent

(A)

-5

0

5 Current scale = 0.1

Voltage scale = 1

Figure 5.8 Grid voltage and output current near zero crossing for fourth switching method (BPWM)

voltage waveforms during zero crossing are shown in Figure 5.8. Even though the prospectivevoltages goes from +Vg to −Vg, the current fall near zero crossing has an exponential decay.The switch Q4 turns off prior to zero crossing of the voltage waveform and the output currentreaches zero ahead of the voltage with the exponential decay. Similarly, the current delays tostart in the next half cycle. The current waveform is symmetric with the voltage, but containshigh order harmonics.

Cu

rren

t (A

)

6050403020100

1

2

3

Harmonic order

THD = 3.6%

Figure 5.9 Output current harmonics

5.4 CURRENT HARMONICS

The SCC controlled inverter current contains odd harmonics. Figure 5.9 illustrates the magni-tude of the fundamental and harmonic currents. The harmonic spectrum is measured for theinverter operating in 4Q operation and the first switching method as described in Chapter 4.High frequency harmonics in the order of switching frequency are also observed, which can beminimized with a application of filter.

The current Total Harmonic Distortion (THD) for the shown spectrum is calculated as 3.6%,which compliances the Australian Standard 4777.2 (Grid connected of energy system via invert-ers) is an acceptable level to inject into the grid. Increasing the fundamental current magnitudereduces the THD. The harmonic distortion is due to the switching frequency ripple and SingleCycle Control loss of control near waveform zero-crossing.


5.5 LOGIC CIRCUIT TO IMPROVE CURRENT WAVESHAPE

A SR latch is used in the SCC to reset the integrator after a certain time period. The latchenables the controller to operate at fixed frequency and preserves the SCC principle. As the realtime current is taken for the controller, any distortion in the output will affect it. The natureof current distortion at zero-crossing at various switching strategies is shown in section 5.3. Alogic circuit is used to minimize the effect of the distortions.

R SW SW1 SW2

0 0 1 00 1 1 11 0 1 01 1 0 0

Table 5.1 New truth table after addition of new logic

As shown in truth table of the SR latch Table 3.1, the 1-1 input state is unknown for itsoutput. If the current fall is slower than the voltage, the latch can be in the unknown statenear the zero crossings. A logic circuit is used to avoid the unknown states. Using NAND,AND and NAND − latch as shown in Figure 5.10, the circuit is able to force both the outputstate low. The set and reset input for the NAND − latch are active low, thus a NOT is addedat the input of the latch. The truth table after addition of logic is obtained as shown in Table 5.1.

Q

QSET

CLR

S

R

Oscillator

(SW)

Reset (R) SW1

SW2

NANDAND

NOT

Figure 5.10 Additional logic on SR latch

However, the problem at zero crossings still persist even if the latch closes the switch, be-cause the rising current signal is higher than the falling integrator output. The current nearzero crossing flows continuously until the next cycle starts as shown in Figure 5.11.

0.0698 0.07 0.0702

Time (sec)

Volt

age a

nd C

urr

ent

0.0704 0.07060.06960.06940.0692

0

0.02

0.1Exponential decaying

of inductor current

Figure 5.11 SCC controller signals waveform near zero crossing

5.6 CONCLUSION 43

5.6 CONCLUSION

The Single Cycle Controlled inverter current performance is presented for ranges of switchingstrategies. The current depends on the shape and magnitude of the current ordered AC signal,the integrator DC signal and the DC source and grid voltages.

The zero crossing performance and the current waveform distortion for various switching strate-gies has been presented. It can be minimized by switching at high frequency near zero cross-ing and using bipolar switching strategy. After implementing a new logic circuit, the currentdistortion level reduces. As the distortion is less and occurs for a short period of time nearzero-crossings, it has less effect. The converter current Total Harmonic Distortion has found bysimulation to be 3.6% at rated current.

Chapter 6

FOUR QUADRANT POWER CONTROL

6.1 INTRODUCTION

The inverter power capability mainly depends on the DC side voltage, filter impedance andthe grid RMS voltage [39]. The power rating of the inverter is also limited by rating of thepower switches, filter etc. The inverter peak current control using integrator slope is discussedin Chapter 3. Another possibility to control active and reactive current injection is varyingmagnitude and phase of the current ordered AC signal in Single Cycle Control.

The proposed current controlled inverter is featured with bidirectional power flow capability.It is proposed to independently control active and reactive current injection. This enables reac-tive power compensation into low voltage grid from small power sources.

Voltage stability is of key importance in low voltage grids, and can be achieved by mixed realand reactive current support from inverters at suitable locations in the grid. The inverter isproposed to inject or absorb reactive current depending on the AC supply voltage.

The proposed inverter needs a new reference waveform to generate suitable active or reactivecurrent. A new AC waveform generation method is discussed. A novel synchronized waveformgeneration method implementable in a microcontroller is proposed.

6.2 POWER CONTROL

The inverter current waveform normally follows the AC signal used in the SCC. Reactive currentcontrol can not be implemented if the signal is directly taken from AC supply voltage.

Key advantages of using a new generated AC signal vnew(t) are listed as follows.

1. Less sensitivity to grid voltage distortion.

2. Independent active and reactive power control.

6.2.1 Controller Strategies

The signal vnew(t) can be decoupled into in-phase and out-of-phase components. Independentvariations of the in-phase and out-of-phase components give magnitude and phase variations ofthe control signal vnew(t). Magnitude of the in-phase and out-of-phase signals depend upon theDC source and AC supply voltage. Two multiplying factors are introduced whose magnitudesvary according to the voltages. Each component is multiplied by the factors and summed to get

46 CHAPTER 6 FOUR QUADRANT POWER CONTROL

the vnew(t).

Suppose kp and kq are multiplying factors for in phase and out of phase components. kp ≤ 1,kq ≤ 1.

Figure 6.1 illustrates vnew(t) as the summation of two independently variable waveforms.

0.0660.06 0.062 0.064 0.0760.068 0.07 0.072 0.074 0.078

0.06 0.062 0.064 0.066 0.068 0.07 0.072 0.074 0.076 0.078

Time (sec)

Time (sec)

1

0

-1

1

0.5

0

-0.5

-1

Volt

Volt

In phase × 1

Out of phase × 0.6

v (t)new

Figure 6.1 New waveform generation

vnew(t) = kp × sin(wt) + kq × cos(wt) (6.1)

If, kp = km × cosφ and kq = km × sinφ

Then vnew(t) can be written as equation 6.2.

vnew(t) = km × sin(wt + φ) (6.2)

Figure 6.2 shows a block diagram of the independent active and reactive power control strategy.DC side voltage is measured across the capacitor and compared with ordered DC voltage foractive power control. Similarly, absolute measured AC supply voltage is compared with orderedAC voltage for reactive power control. Proportional control is used in both to respond to themeasured voltage deviation from ordered value and assign multiplying factors for synchronizedin phase and out of phase components. This strategy requires that two waveforms, synchronisedwith the grid voltage and 90o separated be available. Generation of these waveforms discussedin section 6.4.

6.2.2 Active Power Control

Increasing magnitude of the in-phase component Equation 6.1 increases the amount of activepower injection into the grid. The decision is made based on the DC side voltage. If the voltagetends to go high the inverter injects more active current, which acts to reduce DC side voltage.Similarly, when DC voltage goes low, the active current reduces, which eventually helps to boostthe DC side voltage. For small DC voltage, the inverter absorbs reactive power from the grid.Protection system should be implemented for the DC side voltage for higher or smaller than the

6.3 VOLTAGE CONTROL 47

sin cos

P

+

-

+

-

Synchronization

(In phase)

Synchronization

(Out of phase)

Error Error

Vg

Measured

Vg

Ordered

|Vac|

Measured

|Vac|

Ordered

vnew(t)

Active power Reactive power

P

+ +* *

Figure 6.2 Power control strategy

overvoltage and undervoltage limit. Figure 6.3 shows a simulation of active and reactive powerinjection into grid from proposed inverter.

P(W

), Q

(V

ar)

0 0.150.05 0.1

Time (sec)

0.2 0.25

-500

0

500

1000 P

Q

Figure 6.3 Active and reactive power injection into the grid using SCC

6.2.3 Reactive Power Control

Changing magnitude of the out-of-phase component in Equation 6.1 mainly changes the phaseof the vnew(t) if the reactive power component is small compared to the real power component.It helps to achieve leading or lagging inverter current with respect to the grid voltage. The gridvoltage magnitude is taken as a reference to decide phase for vnew(t). If the grid voltage tendsto drop, by whatever reason, the controller shifts the vnew(t) to lead the grid voltage, so that itsupplies reactive power to the grid. If the grid voltage tends to go high, the converter absorbsreactive power from the grid. Figure 6.4 shows a dynamic simulation of reactive power absorbedby the inverter while supporting active power into grid.

6.3 VOLTAGE CONTROL

The converter connection to the low voltage grid is shown in Figure 6.5. The resistance of thelow voltage grid Rgrid cannot be neglected. When the load draws current from the grid, the


0 0.05 0.1 0.15 0.2 0.25-1000

-500

0

500

1000

P

Q

Time (sec)

P(W

), Q

(V

ar)

Figure 6.4 Active power injection into the grid and reactive power absorption from the grid using SCC

terminal voltage Vo drops below the fundamental voltage magnitude. The voltage drop dependson load current, grid impedance and auxiliary grid support at the connection point.

Grid Inverter

Xinv

Vo

+ ++

---

E Vinv

Rgrid Xgrid

VzgridVzinv

I

Igrid

Figure 6.5 Inverter connected to grid

The inverter should compensate the voltage drop due to grid impedance and loads. This requiresboth active and reactive current injection.

The filter impedance between inverter and grid is highly inductive. The inverter voltage magni-tude controls the reactive power flow into the grid. Similarly, the angle between the converter

Vinv Vzinv

Vo

I

δ

Vinv

Vo

Vzinv

I

Figure 6.6 Phaser diagram for 1. reactive power only 2. active power only

and grid voltage controls the active power flow. Figure 6.6 shows phasor diagrams for indepen-dent reactive and active power flow.

The proposed inverter aims to modulate real and reactive current injection for voltage con-trol. Figure 6.7 shows the phasor diagram for real and reactive compensation for the low voltagegrid. It shows that the injected current should be phase shifted from the voltage by the systemcharacteristic impedance angle for the best voltage compensation.

6.4 IMPLEMENTATION OF NEW GENERATED WAVEFORM 49

45o

45o

I

Igrid

E

Vo VzgridVzinv

Figure 6.7 Real and reactive power compensation

6.4 IMPLEMENTATION OF NEW GENERATED WAVEFORM

A 32-bit microcontroller STM32F103RB [42] is used to generate the new AC signal vnew(t).STM32 has 16-bit timers featured with PWM or pulse counter. PWM output at variable dutycycle is generated using look up table. C-programming code for waveform generation is givenin Appendix A [43]. The look up table consists of 296 elements, which gives the duty cycle foreach pulse and is varied sinusoidally to get sinusoidal waveform. Frequency of PWM is definedby value assigned in auto reload register and it can be updated during controller operation.A simple first order RC high pass filter is used to remove the 2.5V DC offset output frommicrocontroller output and get 50Hz AC reference wave. Two waveforms are generated with90o phase difference and added to get the control signal vnew(t) as given in Equation 6.3. Thewaveforms are synchronized with the grid fundamental voltage. Any frequency changes in thegrid will update the time period to update to synchronize the frequency of the signal vnew(t).

6.4.1 Phase Synchronization

Phase synchronization is a challenging issue in weak power systems. Phase locked loops aremainly used for three phase systems, whereas zero crossing detection is used for single phasesystems. Due to distortion during zero crossings, peak detection method is used in some work.But it is strongly affected by harmonics and wave shapes. Phase detection is the main task forthe synchronization. A novel method implementable in microcontroller is proposed for phasesynchronization in a single phase system.

Vo(t)P

I1/s

Look-up

table

Angle

detect+

-+

sin cos

θm

θestim

Figure 6.8 Phase locked loop diagram

Figure 6.8 shows block diagram for proposed PLL based phase synchronization method. The


phase detection block is used to measure phase angle θm of the AC voltage. The angle is com-pared with θestim from the look up table used for waveform generation. A PI controller is usedto respond to the error between the measured angle and the estimated angle. The PI correctedoutput needs another integrator to convert into angle which gives desired phase angle for sin θand cos θ wave generation. If the integrator output gives angle greater than 360o, it is reset tozero.

Phase Detection

Zero-crossing detection gives unreliable results during voltage distortions.

ωo/s

cosθ

sinθ

|tanθ|

|sinθ|/|cosθ|Look up

table

v (t)oθ

Figure 6.9 Phase angle detection block diagram

The α − β transformation reduces 3-phase waveforms to orthogonal components, from whichphase angle can be directly calculated. The proposed method integrates the voltage waveformto deduce an orthogonal component, from which phase angle be directly calculated. It is impor-tant that the integrator gain is chosen so that the resultant waveform is the same magnitude asthe measured voltage at the nominal frequency and the integrator needs to forget informationmore than a few cycles old so that any DC offset is forgotten. Integration rather than differen-tiation is chosen due to its relative insensitivity to waveform distortion.

The final phase calculation is implemented through a look-up table as shown in Figure 6.9.

Integrator Design

The integrator output depends on phase and magnitude of input AC signal. The requirementsare the output must be in similar amplitude and 90o phase difference to the input signal. Theintegrator filter is important to keep the same amplitude and maintain the phase difference.

Vin

Vout

R1

R2

C1

+

-

Rb

Figure 6.10 Continuous integrator

6.4 IMPLEMENTATION OF NEW GENERATED WAVEFORM 51

Figure 6.10 shows an integrator. The addition of large value of resistor R2 across capacitorC1 gives the circuit characteristics of an inverting amplifier with finite closed loop gain of R2

R1at

low frequencies while acting as an integrator at high frequencies. Any initial DC offset is lost.

vin(t) = Vm cos 2πft (6.3)

After integration, the output voltage will be

vout(t) =1

RC

∫vindt =

Vm

RC

∫cos 2πftdt

vout(t) ==Vm

2πfRCsin 2πft + C (6.4)

Where, C is the initial offset voltage. The gain can be calculated with 12πfRC . The RC time

constant is 0.01.

Hence, C = 0.01µF , R2 = 100K, R1 = 31K. Rb = 22K (Bias resistance).

Phase Angle Calculation

Figure 6.11 shows input cos θ and integrated output sin θ. tan θ and prospective angle in eachquadrants is shown in Figure 6.12. The phase angle can be realized in four quadrants of thesin θ− cos θ plane for a fundamental cycle as shown in Figure 6.13. The operating quadrant of

sinθ

cosθ

Time (sec)0.0880.0860.0840.0820.080.0780.0760.0740.072

0

1

-1

Figure 6.11 sin θ and cos θ

|tan

θ|

5

10

00.072 0.076 0.08 0.084 0.088

Time (sec)

0.072 0.076 0.08Time (sec)

0.084 0.088

Angle

(|θ|)

0

90o

Figure 6.12 1. tan θ 2. Phase angle

the rotating angle vector can be decoupled using the logic representation in Table 6.1. A lookup table is required to find angle for inverse of tan θ. The table can be built for first quadrantonly, for different quadrants angle vector the angle is added to the measured angle as shown inTable 6.2.


Function Direction Logic representationsin θ +ve 1sin θ −ve 0cos θ +ve 1cos θ −ve 0

Table 6.1 Logic to find the operating sin θ − cos θ plane

sin θ cos θ Phase angle(φ)1 1 φ = θ + 00

1 0 φ = θ + 900

0 0 φ = θ + 1800

0 1 φ = θ + 2700

Table 6.2 Logic to find the operating sin θ − cos θ plane

6.4.2 Lookup Table Development for Angle Measurement

The microcontroller is not featured with inverse tan θ function calculation. A look up tablemethod is proposed to detect phase angle in each quadrant of sin θ − cos θ plane. The anglevector is rotating in all quadrants for complete cycle, but using absolute value and detectingdirection of sin θ − cos θ helps to reduce the size of the table for inverse tan θ function.

The microcontroller has a 12-bit resolution analogue to digital converter (ADC). The lowestsignificance 5-bit can be neglected to read angle for each quadrant. Remaining the most signifi-cant 7-bit records angle for 128 different values as shown in Figure 6.14. After each conversion,the A/D converted value used to look up the estimated angle from the table.

Each ADC converted value represents phase angle in each quadrant. Table 6.3 computes the an-gle for each converted value. After detecting tan θ and its quadrant, the angle can be decoupled.The table is computed for one quadrant and depending upon operating quadrants of rotatingvector, corresponding angle is added as shown in Table 6.2.

The look up table for waveform generation consists of 296 elements for complete cycle 2π.

cosθ

sinθ

III

IVIII

cos +veθsin +veθ

cos -veθsin +veθ

cos -veθsin -veθ

cos +veθsin -veθ

0o

90o

180o

270o

Figure 6.13 4Q sin θ − cos θ plane

6.5 CONCLUSION 53

01234567891011

2 = 1287 Don’t care

Figure 6.14 ADC register

ADC converted value Phase angle(Hex value) (Degree)

0 0. .. .

20 22. .. .

40 45. .. .

60 68. .. .7f 90

Table 6.3 Phase angle decoupling

Angle for xth element is decoupled by

Angle = x× 2π

296× 57.29 (in degree) (6.5)

The measured angle is compared with the estimated angle from the waveform generation ta-ble continuously.

6.5 CONCLUSION

An extended power control strategy for the Single Cycle Controller is proposed. PSCAD sim-ulated results are presented for active and reactive power control. It requires new generatedcurrent ordered AC signal. Major advantages of using new current ordered waveform are lesscurrent distortion and independent control over active and reactive current. It is proposed touse microcontroller for new waveform generation featured with independent phase and magni-tude control. The proposed technique allows the inverter for independent active and reactivecurrent injection into grid. A novel idea for synchronization of new generated single phase waveimplementable in microcontroller is proposed.

Chapter 7

SIMULATION, DESIGN AND PROTOTYPE DEVELOPMENT

7.1 INTRODUCTION

The proposed grid connected inverter is simulated in PSCAD/EMTDC. The system includesa Single Cycle Controller, inverter, DC source and low voltage grid. The grid voltage is assumedideal for the simulation.

An analogue controller circuit is designed taking reference from the simulation. The controllerboard is built using surface mount components on four layer printed circuit board. InsulatedGate Bipolar Transistors (IGBTs) are used and built on a double layer printed circuit board forthe inverter. A test rig is prepared.

This chapter explains the simulation and hardware design considerations. A controller circuitdesign is presented. Finally, the prototype development and experimental results are presented.

7.2 SIMULATION

The aim of simulation is to find out controller performance and transient behavior of the singlephase inverter during grid connection. It is used to study output current distortion, inverteroperation for different switching strategies , power flow etc. The parameters used in simulationare tabulated in Table 7.1.

DC side ParameterDC Source 400VCapacitor 150µFSingle phase grid

Line Voltage 230VFrequency 50HzAC side parameterInductor 40mH

Series resistance 0.1ΩController parameters

Switching Frequency 5KHzIntegrator time constant 0.5µs

Table 7.1 Simulation parameters

56 CHAPTER 7 SIMULATION, DESIGN AND PROTOTYPE DEVELOPMENT

The time constant for the resettable integrator is smaller than the switching frequency to ensurethat the integrator is reset before the start of the next switching cycle. The controller loses itsprinciple of operation, if integrator cannot reset within the switching time period. The selectionof time constants also depends on inductance of the inverter output filter.

IGBTs with reverse diodes and snubbers are used for the inverter simulation. The grid voltageis considered as an ideal source, but it is not possible to get an ideal source in practice. Thegrid has its own impedance. Initially, the current ordered AC signal for the controller is takendirectly from the grid. The advantage is that the controller forces the current to have the samephase as the grid voltage. However, if grid voltage is distorted, it contributes to a poor currentwaveform. Thus, to make the current less vulnerable to the grid distortion and to enable reac-tive current injection, a generated AC signal is used to control the current. This enables thecontroller to inject a good current waveshape and consequently improve grid voltage distortionby increasing a fundamental component. The simulated controller signals are shown in Figure7.1 and the grid voltage and output current are shown in Figure 7.2.

Current controlled signal

Scaled real time current

5V

0

0.062 0.064 0.066 0.068 0.07 0.072 0.074 0.076 0.078

Time (sec)

Figure 7.1 The SCC control signals

32.5

-32.5

0

0.062 0.064 0.066 0.068 0.07 0.072 0.074 0.076 0.078

Time (sec)

V scale: 0.1x

I scale: 10xVoltage (V)

Current (A)

Figure 7.2 Grid voltage and output current

7.3 CONTROLLER CIRCUIT

The controller circuit comprises a resettable integrator, oscillator, adder, SR latch, logic, com-parator and current detection module as shown in Figure 3.7.

7.3.1 Oscillator

An oscillator is used to generate a switching frequency which enables the latch and sets a con-stant frequency for the inverter switching. The oscillator frequency is chosen at 5kHz. Thefrequency is good for IGBT switching operation. Lower frequency reduces switching losses andincreases efficiency of the inverter but increases the AC current distortion. Universally accessible

7.3 CONTROLLER CIRCUIT 57

timer 555 is used as an oscillator. The timer output has a 5% duty cycle square wave. Onlya narrow pulse is required to set the latch, thus a small duty cycle is chosen. High frequencyback to back diodes are used to set the different time constants during charging and discharg-ing to get 5% duty cycle output as shown in Figure 7.3. The circuit parameters for the timer are;

Vcc

Disc

Trig

Thr

CvoltGnd

Out

Rst

R2

R1

C

Figure 7.3 Timer 555

R1 = 1.4K, R2 = 28K, C = 0.01µF.

7.3.2 Resettable Integrator

A resettable integrator is an important part of the SCC to control the PWM for inverter switch-ing. An op-amp TL074 is used to make an analogue integrator as shown in Figure 7.4. A

-

+

CVdc

R

Analogue switch

Vout

Reset pulse

Figure 7.4 Resettable integrator

capacitor is connected at the feedback from output to an inverting input pin. The initial voltageat the inverting input pin is zero, because the non-inverting pin is grounded. Whenever the DCvoltage is applied at the input of the integrator, the capacitor charges from 0V to −Vcc at thedesigned time constant. When the integrator is reset, it goes from −Vcc to 0V quickly. Thus,the voltage across capacitor is varied from 0V and −Vcc.

A CMOS analogue switch (ADG619) is used to reset the integrator. The circuit diagram andlogic representation for the switch is shown in Figure 7.5. When the latch output Q goes high,the switch S2 is on, and the capacitor discharges quickly through series resistance connected inthe switch. The series resistance is small and used to limit the current during transient voltage


switching across the integrator. As the turn on resistance for the switch is very small, the ca-pacitor discharges very quickly and the reset the integrator.

2.2nF 10.0Ω

0.01uF

0.01uFD

1

S12

GND3

VDD4

VL5

IN6

VEE7

S28

Latch output Q

ADG619

+5V

-5V

Across integrator

Latch output Q Switch S2

01

offon

Logic representation for ADG619

Figure 7.5 Analogue switch

The integrator parameters are designed from the measured frequency and duty cycle. Theintegrator time constant must be smaller than the switching frequency.

Let, maximum fall in integrator slope = −4V

Measured switching frequency = 5.4kHz

Switching period = 185µsec

Hence, change in voltage with respect to time is, = 4V185µs = 21.62 V

ms

So, for capacitor (C)= 2.2nF

Current(i) = C dVdt = 2.2nF × 21.62 V

ms = 47.56µA

Resistance (R) = 84.1kΩ Thus, the integrator parameter are chosen as C = 2.2nF andR = 100kΩ.

7.4 VOLTAGE AND CURRENT DETECTION

A HCPL788j [45] isolated differential amplifier is used to detect the AC voltage and inverteroutput current. The amplifier has an analogue rectified output (ABSVAl) as required in theSCC. A resistive divider circuit is used to scaled down the grid voltage peak to 5V level for thecontroller purposes.

The maximum recommended input voltage to the amplifier is ±200mV . The output voltagegain is nearly 10 for 5V supply and reference voltage input to the amplifier. A 0.02Ω seriesresistor is used in series with inverter output for current detection purposes up to a peak ratingof 10A. Two separate isolation amplifiers are used for the voltage and current as shown in Figure7.6, and the output of each is passed through buffer amplifiers.

The AC voltage output has a 2.5V DC offset. An RC high pass filter is used to avoid theoffset level in the controller circuit.

7.5 LOGIC CIRCUITRY 59

Gnd216

Vdd215

Fault14

ABSVAL13

Vout12

Vref11

Vdd210

Gnd29

Gnd18

Vdd17

VLed+6

Vdd15

CL4

CH3

Vin-2

Vin+1

0.1uF

0.1uF

0.1uF

0.1uF

+5V

470pF

+5isolated

39.0Ω

AC GND

AC GND

i (t)o

To amplifier

0.04Ω

HCPL 788j

0

Gnd216

Vdd215

Fault14

ABSVAL13

Vout12

Vref11

Vdd210

Gnd29

Gnd18

Vdd17

VLed+6

Vdd15

CL4

CH3

Vin-2

Vin+1

0.1uF

0.1uF

0.1uF

0.1uF

+5V

470pF

+5isolated

39.0Ω

AC GND

AC GND

v(t)

To filter

HCPL 788j

2.5V

Figure 7.6 Current and voltage monitoring circuit

7.4.1 Zero-Crossing Sensing

An ultra-fast comparator (TL3116) is used to detect polarity of grid voltage and current wave-forms as shown in Figure 7.7. There are two comparators used in the circuit to enable fourquadrant inverter operation. The sensing circuitry is isolated from grid.

-

+

V or I

Figure 7.7 Zero crossing detection

7.5 LOGIC CIRCUITRY

A few logic components are added to the SCC to reduce current distortion at zero-crossingsand enable 4Q operation. A SR latch is used to set the constant switching frequency and resetthe integrator. A circuit to avoid the zero-crossing distortion is explained in Chapter 5. Acombination of logic AND, OR and NAND gates are implemented in the circuit to implementswitching strategy. The logic circuit is given in Appendix E.1. Boolean equations for the logicimplementation are mentioned in Chapter 4. Figure 7.8 shows a switching sequence for Q1, Q2,Q3 and Q4.

7.6 IGBT GATE DRIVE CIRCUITRY

Gate drive circuitry is used to perform a high quality IGBT switching. A number of gate drivecircuits can be used. For example, pulse transformer, charge pump, floating gate driver supplyand bootstrap circuits are popular.

A high and low side driver IR2112 is chosen for IGBT switching, which has 600V floatingchannel. It operates on the bootstrap principle, which is popular in switching applications forfrequency ranges in tens of Hertz to few hundreds of kHz. The gate drive voltage ranges from10V to 20V and the chip is compatible with 3.3V logic input. The switching frequency is 5kHz.Duty cycle will vary from 0 to nearly 100%. The gate driver must be able to provide enoughpower at the gate of IGBT to turn it on properly.

Gate capacitance Energy, (W) = 12 ×∆Qg ×∆Vge = 0.5× 142nC × 8V = 0.568µJoule

The required output power from the driver = W × fsw = 0.568µJoule× 5kHz = 2.84mWatt


1

0

Q1

1

Q2

0

1

Q3

0

1

Q4

0

0.06 0.062 0.064 0.066 0.068 0.07 0.072 0.074 0.076 0.078

Time (sec)

Figure 7.8 IGBT switching logic sequence for Q1, Q2, Q3 and Q4 at reactive current injection

The major task in designing the driver is the selection of the bootstrap capacitor value. Theinput voltage level is 5V . The logic voltage level at input and output of the driver IR2112 areshown in Figure 7.9.

3.7V

5V

Logic 1

0V

1.8V

Logic 0

9.5V

15V

Logic 1

0V

6V

Logic 0

uncertain uncertain

Input logic voltage

level

Output logic voltage

level

Figure 7.9 IGBT driver IR2112 logic voltage level

The minimum bootstrap capacitor value can be calculated from the following equation takenfrom IR application note [40].

C ≥2[2Qg + Iqbs(max)

f + QLs + ILbs(Leak)f ]

Vcc − Vf − VLs − Vmin(7.1)

WhereGate charge of high side IGBT (Qg) = 142nCMaximum VBS quiescent current (Iqbs (max)) = 230µALevel shift charged required per cycle (QLS) = 5nC (typical value)

7.7 POWER CIRCUIT 61

Bootstrap capacitor leakage current (Icbs (Leak)) can be neglected for ceramic capacitor.Logic section voltage source (Vcc) = 15VForward voltage drop across bootstrap diode (Vf ) = 1.0VMinimum voltage between VB and VS (Vmin) = 0V

Using Equation 7.1, the capacitor value found to be greater than 0.047µF.

As shown in Figure 7.10, the bootstrap capacitor (CBS) is the only source to turn on and

D2

Q2

Q1

D1

Vdc

Rbs

Dbs

Figure 7.10 IGBT driver circuit diagram

off of Q1. When Q2 is on, the lower pin of the CBS is connected to the ground potential andcharges from 15V supply through a diode in series. When the Q2 is off , the capacitor currentcan not flow through the reverse bias diode. This floating charged voltage will be applied at thegate of the high side switch. The high side channel of the drive is connected to the high side ofinverter where voltage swings between two rails. The voltage at Q1 varies from Vdc (400V ) toground potential, so the gate voltage should be 415V to turn on. Thus, output side terminalof the driver is isolated from the input terminals. The minimum required capacitor value iscalculated from the Equation 7.1, and its time constant should be one tenth or less than theswitching period. Q1 gate pulse has variable duty cycle. During higher duty cycle the CBScharges for small period, when output current is flowing through D2 during Q1, Q2 off . Hence,the capacitor should store enough energy to turn it on for long discharging period. Finally,the CBS value is chosen at 1µF in parallel with a small decoupling capacitor 0.01µF . Bothcapacitors are ceramic multi-layers.

Special care is required while selecting bootstrap diode, which is connected in series with asmall resistance and the CBS. The diode should be able to block high rail voltage, which is400V and should be fast recovery to minimize the charge flowing back to the Vcc from the CBS.The resistor is used to limit the transient current during switchings, but maintain a short ca-pacitor charging time constant.

Another low equivalent series resistance (ESR) ceramic capacitor is used on the low side chan-nel from Vcc to COM (ground). As this capacitor supports both output buffer and bootstraprecharge, it is chosen 10 times bigger than the bootstrap capacitor which is 10µF [40].

7.7 POWER CIRCUIT

The power circuit board is vulnerable to overvoltage due to the high frequency switching ofhigh voltage and current. The single phase full bridge inverter is built using n-type IGBT


(T0 − 247) package. Careful PCB layout is important to reduce parasitic bus inductance andstray inductance between the high side and low side of the switching devices.

7.7.1 Parasitic Bus Inductance

The parasitic bus inductance appears due to a separation between bus plate and connections.The inductance causes high transient voltage during IGBT switching. The snubber circuit acrossIGBT is used to protect from the transients as shown in Figure 7.11. When Q1 is off , parasiticbus inductance causes a transient voltage across Q1. The snubber diode is forward biased anddiverts the transient energy into the snubber capacitor. The capacitor voltage discharges throughthe snubber resistance and releases stored energy when Q1 turns on. During turn on the snubbercapacitor discharges through snubber resistance whose time constant is smaller than on state ofthe IGBT and the resistance is selected to limit the high discharging current. The snubbers areprimarily useful to:

1. Limit switch di/dt or dv/dt.

2. Shape the load line to keep it within safe operating area.

3. Reduce total switching losses.

4. Transfer power dissipation from the switching device to resistor.

L

R =220s Ω

C =27pFs

Parasitic series inductance

Snubber

Q1

Figure 7.11 Snubber across IGBT

The H-bridge is constructed on 1mm thick board with 2 ounce thickness of copper on doublesided PCB. The negative voltage rail is constructed underneath the positive voltage rail of thePCB as shown in Figure 7.12. The cross sectional area of the positive bus is similar to thenegative bus. A high voltage electrolytic capacitor is connected across the positive and negativebus as close as possible to avoid the lead-inductance due to the capacitor connection. Usuallysome low ESR ceramic capacitors are added. The parasitic inductance due to the bus connectionand snubber capacitors for peak 10A fundamental current are calculated as follows.

Length of flux path (l) = 90mm

Distance between positive and negative bus (d) = 1mm

Wide of the bus (b) = 30mm

Surface area of flux path (A) = 30mm2

7.7 POWER CIRCUIT 63

Flu

xpath

l=

90m

m

1mm

Positive Bus

Negative Bus

i

A

30mm

Figure 7.12 DC bus connection at PCB

Assuming free space in between two bus, Permeability (µ) = 4π × 10−7N/A2

Reluctance of the bus can be approximated by, < = lµ×A = 2387.32M(Amp−turns

Weber )

Hence, the parasitic inductance can be calculated by,

Inductance (L) = N2

< = 1< = 0.42nH

Energy stored in the parasitic inductance at peak current of 10A can be calculated as follows.

WL = 12LI2 = 21nJ

Power stored at 5KHz frequency can be estimated as follows.

Power = 20.9µJ × 5KHz = 0.105mW

A snubber capacitor can be estimated using energy equations.

Energy dissipation in capacitor = Energy stored in parasitic inductance

12CsV

2 = 21nJ

for V = 400V, Cs ∼ 27pF

Snubber resistance, Rs = 220Ω

7.7.2 Stray Inductance Between High Side and Low Side Switch

Additional stray inductance occurs due to wiring in the AC path connections. The AC pathstray inductance occurs in between high side and low side of the IGBT terminals as shown inFigure 7.13. This inductance can not be compensated for using any external components. Theeffect can be reduced by connecting emitter of the high side IGBT very close to collector ofthe low side IGBT. Moreover, it is intended to avoid a loop and uses thick track in betweenconnecting legs. The IGBTs are connected as close as possible. The di

dt effect can be reduced byusing a gate resistor which reduces the switching speed.


L

L

Q1

Q2

str

ay inducta

nce

Figure 7.13 Stray inductance

7.8 FILTER

The inverter is directly coupled to grid through a series inductor, which acts as a filter. Thefilter removes high frequency harmonic contents of output current caused by high frequencyswitching operations. Its attenuation is 20dB/decade over the whole range of frequency. Forhardware implementation, the inductor value is chosen from simulation. Design of the filterinductor involves the following aspects.

1. Selection of core

2. Wire selection

3. Air gap calculation

4. Number of winding calculation

7.8.1 Size of Inductor

Small inductance reduces size of inductor but increases current ripple and speeds up the circuit.The percentage of ripple current with respect to rated current determines the size of the inductor.The inductor is designed to meet high peak current with low ripple. It is designed for continuouscurrent. The discontinuous current operation distorts Single Cycle Controlled current output.There are few parameters considered to select the size of inductor.

1. Switching Frequency

2. Maximum input and grid voltage

3. Duty cycle

4. Maximum ripple current

7.8 FILTER 65

7.8.2 Selection of Core

Selection of core depends on core loss due to high frequency ripple current and saturation limitof the core at peak fundamental current. A larger E size ferrite core is used as shown in Figure7.14. The inductor is designed to operate at switching frequency and it is verified that it doesnot saturate at peak fundamental current.

10.4cm

1.1cm

4.2cm

Figure 7.14 Inductor core

The core experiences two different frequencies of current for this application. The inverteris switching at 5kHz frequency, whereas the fundamental current is at 50Hz. The circuit canbe realized into two equivalents at two different frequency responses. At 50Hz current, theinverter output experiences the grid voltage as shown in Figure 7.15(1). At 5kHz, the grid canbe considered as short circuit as shown in Figure 7.15(2).

VconvVo

50Hz

L

Vconv

L

Figure 7.15 Equivalent circuit 1.at 50Hz 2.at 5kHz

Air gap volume stores energy and help to make the inductor less dependent on the core properties.It widens the current range and makes effective permeability less dependent on core temperature.

Considering 1KW output power from the inverter, the peak current at fundamental frequencyis nearly 6A. The maximum ripple current is 500mA. The air gap is created with 1mm thicksheet of plastic composite material. Number of windings and wire size are calculated for fun-damental peak current. The flux density appears on the core at peak current is estimated fromthe calculation. The detail inductor design calculation is given in Appendix B. The designedresults are tabulated in Table 7.2.


Parameter ValueInductance 40mH

Number of winding 50 turnsWire size 2mmAir gap 1mm

Peak flux density at 5kHz 0.24TPeak flux density at 50Hz 0.188TTotal peak flux density 0.428T

Table 7.2 Inductor designed paramter

7.9 THERMAL DESIGN

The thermal design relates to heat sink, layout and packaging of the inverter. Extreme op-erating conditions of power devices for conduction and switching losses, junction and ambienttemperatures are considered.

7.9.1 Inverter Board and Heat Sink Estimation

Out of four IGBT switches, only two are switching at high frequency alternatively in every halfcycle. During positive half cycle, Q1 and Q4 are on, while Q3 and Q2 are off . Q1 will beswitching at 5kHz PWM signal, while Q4 remains on. For negative half cycle, Q3 and Q2 areon, while Q1 and Q4 are off . During this period, Q3 will be switching at 5kHz PWM signal,while Q2 remains on and the same process will repeat for next cycle. Schottky diodes are con-nected across the IGBT switches.

The IGBTs have substantial switching losses, which can be reduced by adequate gate drivecircuitry. High speed IGBT selection helps to minimize the switching losses. The diodes D1,D2, D3 and D4 carry almost similar amount of energy, hence noticeable energy loss can beexperienced in the diodes. The bridge operating parameters are tabulated in Table 7.3.

Parameter ValueLine frequency 50Hz, 50% duty cycle

Switching frequency 5kHz, PWMDC side voltage 400V

Maximum current 10A(rms)

Table 7.3 Bridge operating parameter

The detail calculations for power loss and heat sink estimation for are given in Appendix C.

The thermal loss should be dissipated to keep junction temperature below its maximum level.Larger size of heat sink can be used. It is a trade-off between the size and cost of the heatsink selection. The larger size heat sink dissipates heat quicker, but it increases the invertercost. The heat sink size is chosen by estimating switching devices surface to ambient thermalresistance.

7.10 HARDWARE CONSTRUCTION 67

IGBTsSwitch Types of loss Power loss per switch Total loss

Q1 and Q3Conduction loss 8.59W 17.18WSwitching loss 1.5W 3W

Q2 and Q4Conduction loss 13.5W 27WSwitching loss 0.015W 0.03W

Total loss at IGBTs switches 47.21WDiodes

D1, D2, D3 and D4Conduction loss 7W 28WRecovery loss 0.5W 2W

Total loss at diodes 30W

Table 7.4 Power loss in power switches

A total switching and conduction losses estimation for each IGBT and reverse diode are tab-ulated in Table 7.4. Considering maximum operating junction temperature 125oC [44], thethermal resistance from heat sink to ambient is found as 0.98oC/W .

Similarly, for the diodes, the thermal resistance from heat sink to ambient is found as 7.2oC/W .

7.10 HARDWARE CONSTRUCTION

Four layer PCB for controller circuit is designed in Altium designer 6 package. The functioningcontroller board and test set up is shown in Figure 7.16.

DCsignal

±15V

±5V

Isolated5V

Isolated5V

Currentsignal

AC Voltagesignal

IGBTswitchingpulses

DC ground and SCC controller

(Isolated)

IGBT driver circuitry

Logic circuitry

Voltage and current

monitoring section

(AC ground isolated)

IGBTs mounted on heat sink

Diodes mounted on heat sink

DC

sid

e c

ap

acit

or

Figure 7.16 Controller board and test set up

A separate power board is prepared for high power switches. The IGBTs and diodes are mounted


on heat sinks. The DC side capacitor is connected as close as possible to avoid the parasiticeffect as discussed in Section 2.7.

7.10.1 GCI Test Rig

A laboratory test rig was prepared. A variable voltage transformer is used and rectified to getvariable DC voltage source. Another AC variable transformer is used to test the connection ata lower voltage level. The iron core variable transformer has high impedance and it is changingat different tap positions. This distorts the current and voltage waveforms.

230V,

50Hz

230V,

50Hz

LR

Q1

Q2

Q3

Q4

C

Figure 7.17 Inverter test rig layout

Finally, a variable AC voltage generator (Chroma AC source 61504) is used to get the cur-rent ordered AC signal. A circuit layout for the laboratory test rig is shown in Figure 7.17.

7.10.2 Prototype Results and Discussion

Single Cycle Controlled grid connected inverter results are shown for the current ordered signaltaken directly from grid voltage. The results are measured for small scale voltage level main-taining DC source voltage at 50V .

Figure 7.18 shows measured integrator reset signal and the integrator output falling signal forfundamental half cycle. Near zero-crossing, due to an unwanted switching in reset pulse, thetransient integrator output rises above zero.

Transient due

to unwanted

switching

Unwanted

multiple

switching

Figure 7.18 Integrator reset pulse and output

Figure 7.19 shows the SCC controller signals. The controller signals illustrate the current dis-tortion near zero crossings. The current rises above than the controls signals for short period

7.10 HARDWARE CONSTRUCTION 69

due to a small phase difference between mains voltage and scaled waveform. The phase shiftoccurs due to high pass filter used to remove 2.5V DC offset in scaled waveform which is theoutput from isolated amplifier HCPL− 788j. The isolated amplifier is used in the voltage andcurrent waveform sensing circuit as mentioned in section 2.4.

Scaled real time current

Flat topped

supply voltage

ACControl signal

Zero crossing

distortion

Figure 7.19 SCC controller operation

Figure 7.20 shows the switching gate pulse of IGBT Q1 for single switching cycle. IGBT gateto emitter voltage is switching from 0V to 15V . Small undershoot transient voltage is observedduring turn off of the gate pulse, but the transient amplitude is small.

Undershoot transient

Figure 7.20 IGBT switching gate pulse for Q1

The inverter output voltage is shown in Figure 7.21. The switches are turned off becausethe current becomes higher than the control signal near the zero-crossing as explained in Chap-ter 5. The new logic turned off the switches to limit the higher rise in the current.

The grid voltage (which is scaled to control the current waveform) and output current waveformsare shown in Figure 7.22. The laboratory voltage waveform is flat topped due to heavy switchmode power supplied load. The small rising current around zero crossings can be removed byclearing the small phase shift between scaled and mains voltage waveform. The proper selectionof filter capacitor in the voltage sensor circuitry or using 2.5V reference in the comparator forvoltage detection would improve the inverter current waveform from Figure 7.22.


Switch turned

during current

rises as shown

in Figure 7.19

due to small phase

shift between

scaled and mains

voltage waveform

from the voltage

sensor circuitry.

off

Figure 7.21 Inverter output voltage

Current rises due

to small phase

shift between

scaled voltage

waveform and

mains voltage

waveform from

the voltage

sensor circuitry.

Figure 7.22 Scaled AC voltage and current waveforms

The measured current harmonic spectrum at small current is shown in Figure 7.23. The mea-sured current THD is 14.1%. The higher current THD is resulted is due to distorted voltage atthe laboratory itself. The mains voltage THD is 14%. Fluke 41 Power Harmonic Analyzer isused to measure the harmonic spectrum.

Discussion

As shown in Figure 7.18, the integrator output falling slope is a function of the DC signal appliedat the integrator and integrator time constant. The falling slope controls the peak of outputcurrent. As discussed in Single Cycle Control theory Chapter 3, the controller forces the currentwaveform to have a similar shape to the AC signal applied at the SCC. Figure 2.19 shows theAC signal shape is important to inject the good current waveform into grid.

The output current distortion near zero crossing, even when the switches are forced to turnoff is shown in Figure 7.22. The peaky rise or fall of the measured current near zero crossingis not observed in simulation. This occurs due to small phase shift between scaled and mainsvoltage waveform. The phase shift occurs from RC filter, which can be removed by properselection of capacitor in future. The zero-crossing current distortions are discussed in Chapter5. The observed unwanted high frequency transients are generated due to noises from test probe

7.11 CONCLUSION 71

1 3 5 7 9 11 13 15

% F

50

100

Harmonic order

Frequency = 50Hz, Phase = 0o

Current RMS = 0.51A, THD = 14.1%

Figure 7.23 Current harmonic spectrum

and and meters and high EMI.

The current THD is nearly similar to voltage THD. Hence the distorted grid voltage will distortthe current output for the SCC controlled GCI, if the current ordered signal is directly takenfrom the grid. The performance of the SCC controlled GCI can be improved by implementinga new current ordered waveform as proposed in Chapter 6.

7.11 CONCLUSION

The controller circuit design is added by studying its performance in PSCAD. The designedparameters for each block is illustrated. The controller is constructed on a four layer printedcircuit board to remove high frequency noise due to switching operation. The power board isseparated from the controller board. The prototype test rig is prepared using voltage variableautotransformer and tested at different voltage levels. As the laboratory voltage waveform isheavily distorted, the current shape also distorted and increases the Total Harmonic Distortionof the measured current. The converter current follows the current ordered AC signal and zerocrossing distortion is observed as expected from the simulation. The distortion in measuredcurrent also occurs due to small phase shift between scaled and mains voltage waveform, whichcan be improved in future application. In spite of mains voltage distortion and high frequencynoise, the inverter performance found satisfactory for small scale power application.

Chapter 8

CONCLUSION

8.1 CONCLUSION

A simple voltage source current controlled grid connected inverter is developed. The inverteruses Single Cycle Controller and has shown tremendous opportunity for low voltage grid supportfrom small scale power sources. The controller method is simple and is effective for direct lowvoltage grid connected applications.

The Single Cycle Controller controls the inverter current to have the same phase as the cur-rent ordered waveform. The controller uses real time current and therefore has a good transientresponse.

A hybrid PWM first switching strategy helps to increase H-bridge inverter efficiency by switch-ing only one switch at high frequency at any time. The switching method allows bidirectionalcurrent flow and easy implementation in hardware with few logic components.

The current output of the Single Cycle Controlled inverter contains zero-crossing distortionfor this simple switching method. The measured current waveform has more distortion due toadditional voltage distortion in the laboratory. However, the simulated output current THDcompliances the Australian Standard 4777.2 (Grid connection of energy system via inverters) toinject into grid. The experimental current will be improved for less distorted mains voltage.

Additional phase and magnitude control of the signal allows independent control over activeand reactive current injection. Using of a synchronized waveform increases the inverter powercontroller capability and voltage stability using distributed power sources for weak grid. Amethod for generating this waveform is proposed, and tested by simulation.

A handful of universally available components and simple engineering not only reduces theinverter price but also makes it robust, portable and repairable. Application of the proposedinverter can be expected to increase integration of distributed power sources in low voltage gridin remote and urban areas.

8.2 FUTURE WORK

The controller board needs accessories isolated (+5V ) and common ground (±15V and +5V )DC voltage supplies. The prototype uses external DC power supplies. The power supply circuitcan be integrated into the prototype for future use.

Protection of the proposed Single Cycle Controlled grid connected inverter during grid faults

74 CHAPTER 8 CONCLUSION

is not discussed in the thesis. It must be designed before implementing the inverter into realsystem. The inverter does not regulate the output voltage during islanding mode. The controllersystem is designed to operate in direct grid connection mode. It is necessary to shut down thesystem during islanding. If a control waveform is artificially generated, the controller systemcan be updated to operate during islanding.

The existing Single Cycle Controlled inverter injects a current that is rich in harmonics. This ispartly due to the distortion inherent in the supply voltage waveform, partly due to the switch-ing frequency ripple, and partly due to the Single Cycle Control loss of control near waveformzero-crossing. These issues could be addressed by,

1. artificially generating the current reference waveform.

2. increasing the switching frequency.

3. changing the switching strategy near zero crossings.

The hard switched H-bridge inverter is used. Though the proposed hybrid PWM switchingstrategy minimizes switching losses, soft switching techniques can be implemented to increaseits efficiency.

During bidirectional power flow, the inverter operates both in buck and boost mode. Dur-ing boost mode, the H-bridge has limitations, the inverter operates in discontinuous currentmode while the grid voltage is low. The Single Cycle Controller is unable to reset within theswitching period due to discontinuous current operation. The current waveform can be improvedwith appropriate switching or inverter topology.

The current distortion can be minimized by applying high frequency bipolar switching nearzero-crossing.

Use of a new current ordered AC signal is proposed in Chapter 6. The proposed work isunfinished due to time limitations. The new signal need to be synchronized to the grid voltage.The proposed synchronized waveform generation method is novel. The proposed method shouldimprove waveform Total Harmonic Distortion and allow real-reactive power flow.

The inverter strongly interacts with low voltage network mainly in rural area. One futurepossibility is to study the effect of large numbers of grid connected inverter at different locationsof network. With suitable active and reactive power injection, the performance of a weak gridcan be augmented.

Appendix A

MICROCONTROLLER

C-PROGRAMMING CODE FOR STM32 MICROCONTROLLER

/*******************************************************************************File Name : newwave.c********************************************************************************/#include "stm32f10x_lib.h"#include "stm32f10x_tim.h"#include "stm32f10x_gpio.h"

#define ADC1_DR_Address ((u32)0x4001244C)

GPIO_InitTypeDef GPIO_InitStructure;TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;TIM_OCInitTypeDef TIM_OCInitStructure;NVIC_InitTypeDef NVIC_InitStructure;ADC_InitTypeDef ADC_InitStructure;DMA_InitTypeDef DMA_InitStructure;u16 ADC1_ConvertedVal=0;u16 ADC_Val=0;u16 CCR1_Val = 0;u16 CCR2_Val = 0;u16 CCR3_Val = 0;u16 CCR4_Val = 0;u16 TIM_Pulse=0;

u16 n[296]=171, 188, 205, 222, 239, 256, 272, 289, 305, 322, 338, 354, 370, 386, 402,418, 433, 449, 464, 479, 495, 509, 524, 539, 553, 567, 581, 595, 609, 623, 636, 649, 662,675, 687, 700, 712, 724, 735, 747, 758, 769, 780, 790, 800, 810, 820, 830, 839, 848, 857,865, 874, 882, 897, 904, 911, 917, 924, 930, 936, 941, 946, 951, 956, 960, 964, 968, 971,974, 980, 982, 984, 986, 987, 988, 989, 989, 990, 990, 889, 989, 988, 987, 986, 984, 982,974, 971, 968, 964, 960, 956, 951, 946, 941, 936, 930, 924, 917, 911, 904, 897, 882, 874,865, 857, 848, 839, 830, 820, 810, 800, 790, 780, 769, 758, 747, 735, 724, 712, 700, 687,675, 662, 649, 636, 623, 609, 595, 581, 567, 553, 539, 524, 509, 495, 479, 464, 449, 433,418, 402, 386, 370, 354, 338, 322, 305, 289, 272, 256, 239, 222, 205, 188, 171, 154, 150,145, 140, 139, 138, 137, 136, 135, 130, 128, 126, 124, 122, 120, 103, 86, 85, 84, 83, 82,81, 80, 79, 78, 77, 76, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 103, 105, 108, 110,111, 115, 118, 120, 122, 124, 126, 128, 130, 135, 136, 137, 138, 139, 140, 145, 150, 154,171, 188, 205, 222, 239, 256, 272, 289, 305, 322, 338, 354, 370, 386, 402, 418, 433, 449,464, 479, 495, 509, 524, 539, 553, 567, 581, 595, 609, 623, 636, 649, 662, 675, 687, 700,712, 724, 735, 747, 758, 769, 780, 790, 800, 810, 820, 830, 839, 848, 857, 865, 874, 882,897, 904, 911, 917, 924, 930, 936, 941, 946, 951, 956, 960, 964, 968, 971, 974, 980, 982,984, 986, 987, 988, 989, 989, 990;ErrorStatus HSEStartUpStatus;

void RCC_Configuration(void);void GPIO_Configuration(void);void NVIC_Configuration(void);void Delay(vu32 ncount);

76 APPENDIX A MICROCONTROLLER

/*******************************************************************************

* Function Name : main

* Description : Main program

*******************************************************************************/

int main(void)

#ifdef DEBUG

debug();

#endif

RCC_Configuration();

NVIC_Configuration();

GPIO_Configuration();

DMA_DeInit(DMA_Channel1);

DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;

DMA_InitStructure.DMA_MemoryBaseAddr = (u32)&ADC1_ConvertedVal;

DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;

DMA_InitStructure.DMA_BufferSize = 1;

DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;

DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;

DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;

DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;

DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;

DMA_InitStructure.DMA_Priority = DMA_Priority_High;

DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;

DMA_Init(DMA_Channel1, &DMA_InitStructure);

DMA_Cmd(DMA_Channel1, ENABLE);

ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;

ADC_InitStructure.ADC_ScanConvMode = ENABLE;

ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;

ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;

ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;

ADC_InitStructure.ADC_NbrOfChannel = 1;

ADC_Init(ADC1, &ADC_InitStructure);

// ADC1 regular channel14 configuration

ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_7Cycles5);

ADC_DMACmd(ADC1, ENABLE);

ADC_Cmd(ADC1, ENABLE);

ADC_ResetCalibration(ADC1);

while(ADC_GetResetCalibrationStatus(ADC1));

ADC_StartCalibration(ADC1);

while(ADC_GetCalibrationStatus(ADC1));

// System Clocks Configuration

//NVIC Configuration

// GPIO Configuration

//DMA Configuration

//ADC1 Configuration

// Enable ADC1 reset calibration register

// Check the end of ADC1 reset calibration register

// Start ADC1 calibration

// Check the end of ADC1 calibration

77

ADC_SoftwareStartConvCmd(ADC1, ENABLE);

ADC_Cmd(ADC1, ENABLE);

ADC_Val=ADC_GetConversionValue(ADC1);

TIM_TimeBaseStructure.TIM_Period = 1512;

TIM_TimeBaseStructure.TIM_Prescaler = 0;

TIM_TimeBaseStructure.TIM_ClockDivision = 0;

TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);

TIM_Cmd(TIM4, ENABLE);

TIM_ARRPreloadConfig(TIM4, DISABLE);

while(1)

int I, j, k;

double AMP;

for(i=0; i<=217; i++)

CCR3_Val=n[i];

j=i;

j=j+77;

k=i+j;

CCR2_Val=n[j];

AMP=(ADC_Val*0.000244);

CCR4_Val=(((n[i]-533)*1)+533)+(((n[j]-533)*0.1)+533);

CCR1_Val= AMP*CCR2_Val;

TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;

TIM_OCInitStructure.TIM_Channel = TIM_Channel_3;

TIM_OCInitStructure.TIM_Pulse=CCR3_Val;

TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;

TIM_OCInit(TIM4, &TIM_OCInitStructure);

TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable);













/*******************************************************************************

* Function Name : RCC_Configuration

* Description : Configures the different system clocks.

*******************************************************************************/

void RCC_Configuration(void)

// Start ADC1 Software Conversion

// Time base configuration

78 APPENDIX A MICROCONTROLLER

RCC_DeInit();

RCC_HSEConfig(RCC_HSE_ON);

HSEStartUpStatus = RCC_WaitForHSEStartUp();if(HSEStartUpStatus == SUCCESS)

RCC_HCLKConfig(RCC_SYSCLK_Div1);

RCC_PCLK2Config(RCC_HCLK_Div1);

RCC_PCLK1Config(RCC_HCLK_Div8);

FLASH_SetLatency(FLASH_Latency_0);

FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /

/* PLLCLK = 8MHz * 9 = 72 MHz */RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_2);

RCC_PLLCmd(ENABLE);

while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)

RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

while(RCC_GetSYSCLKSource() != 0x08)

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);

// GPIOA and GPIOB clock enableRCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOC|RCC_APB2Periph_GPIOB,

ENABLE);

/******************************************************************************** Function Name : GPIO_Configuration* Description : Configure the TIM3 Ouput Channels.*******************************************************************************/void GPIO_Configuration(void)GPIO_InitTypeDef GPIO_InitStructure;

//GPIOB Configuration: TIM4 channel 3 and 4GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;GPIO_Init(GPIOB, &GPIO_InitStructure);

/* Configure PC.04 (ADC Channel14) as analog input -------------------------*/GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;

// RCC system reset (for debug purpose)

// Enable HSE

// Wait till HSE is ready

// HCLK = SYSCLK

// PCLK2 = HCLK

// PCLK1 = HCLK/4

// Flash 2 wait state

/ Enable Prefetch Buffer

// Enable PLL

// Wait till PLL is ready

// Select PLL as system clock source

// Wait till PLL is used as system clock source

// TIM3 clock enable

79

GPIO_Init(GPIOC, &GPIO_InitStructure);

/******************************************************************************** Function Name : NVIC_Configuration* Description : Configures Vector Table base location.*******************************************************************************/

void NVIC_Configuration(void)#ifdef VECT_TAB_RAM//Set the Vector Table base location at 0x20000000NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);

#else //VECT_TAB_FLASH//Set the Vector Table base location at 0x08000000NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);

#endif

NVIC_InitStructure.NVIC_IRQChannel=ADC_IRQChannel;NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=0;NVIC_InitStructure.NVIC_IRQChannelSubPriority=0;NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;NVIC_Init(&NVIC_InitStructure);

#ifdef DEBUGvoid assert_failed(u8* file, u32 line)

while(1)

#endif

void Delay(vu32 nCount)

for(; nCount!= 0; nCount--);

/************************************* **********************************************/END OF FILE

Appendix B

INDUCTOR DESIGN

Considering, 1KW output power from the converter, the peak current at line frequency is nearly6A. The maximum ripple current is 500mA.

As the current peak is small skewed than the voltage peak, the current peak is obtained at

400VDC

0

0.2ms

300VAC

t

Figure B.1 Duty cycle at fundamental current peak

300V peak. The duty cycle is 75%. Calculating flux φripple at the peak current;

φripple = 1N

∫V dt

= 1N

∫ DT0 100dT = 1

N × 100DT = 1N × 100× 0.75× 2× 10−4 = 1

N ∗ 0.015Wb

Where, N is number of turns, V is the voltage experienced in the core during turn on time.

Flux density Bripple due to ripple can be calculated as;

Bripple = V DTNA = 0.015

N × 1A

Diameter of core (D)= 4cm = 0.04m

Area (A) = 0.001256m2=1.25 × 10−3m2

Considering number of turns, (N) = 50 turns

Bripple = 0.01550×1.25×10−3 = 0.24T

The inductor from simulation is = 40mH=4 × 10−2H

Air gap length (lg)= 1mm

Air gap reluctance < can be calculated as follows.

82 APPENDIX B INDUCTOR DESIGN

< = lgµoAc = 2×lg

4Π×10−7×1.25×10−3 = 0.127 × 107 AT/Wb

Now, flux at 50Hz can be estimated as follows.

φ50Hz = mmf< = NI

< = N×5<

Bpfixed = ΦA = NI

<A = 50×60.127×107×1.25×10−3 = 0.188T

Hence, total flux density at current peak Bp is

Bp = (0.24 + 0.188)T = 0.428T .

Appendix C

THERMAL SYSTEM

C.1 INVERTER BOARD

C.1.1 Power loss in IGBT

The switching gate pulse for Q1 and Q3 switches are shown in Figure 7.8. Average Duty Cycle(Dav) for Q1 and Q3 during half cycle can be calculated as follows.

Dav = 12×Π

∫ π0 sinwt d(wt) = 1

2×π [2] = 1π

Power loss at Q1 and Q3 can be calculated as follows.

Conduction loss(Pd),

Pd = Ic × Vce(sat) ×Dav = 10A× 2.7V × 1π = 8.59W

For two switches,Pd = 2× 8.59W = 17.18W

where Ic is collector current, Vce(sat) is the collector to emitter saturation voltage. Switchingloss (Psw) at switches Q1 and Q3 can be calculated as follows.

Turn-on energy loss, Eon = 200uJ [44]

Turn-off Energy loss, Eoff = 100uJ

Switching Loss, Psw = Fsw × (Eon + Eoff ) = 5000 ∗ 300uJ = 1.5W

Where Fsw is the switching frequency.

For two switches,

Psw = 2× 1.5W = 3.0W

Similarly, Power loss at switches Q2 and Q4 can be calculated as follows.

Conduction loss (Pd),

Pd = Ic × Vce(Sat) ×D = 10A× 2.7V × 0.5 = 13.5W

84 APPENDIX C THERMAL SYSTEM

Total conduction loss at both switches,

Pd = 2× 13.5W = 27W

Switching loss (Psw)

Psw = 50Hz × 300µ, J = 0.015W

Total Switching loss at Q2 and Q4 is,

Psw = 0.03W

Hence, Total Power loss at four switches in one full cycle found as,

Ploss = (17.18 + 3.0 + 27 + 0.03)W = 47.21W

Heat sink estimation for IGBT

Operating maximum junction temperature, Tj=125 [44]

Thermal resistance junction to case for T0247 (From datasheet, Rθj−c = 0.43

Thermal case to heat sink thermal resistance for T0-247 package, Rθc−s = 0.6 (Referring IR Ar-ticle)

Ambient temperature, Ta = 30

Neglecting normalized thermal response,

Tj = Ta + Pd(Rθj−c + Rθc−s + Rθs−a)

125 = 30 + 47.21(0.43 + 0.6 + Rθs−a)

Rθs−a × 47.21 = 95− 48.62

Rθs−a = 0.98 C/W

C.1.2 Power loss in Diode

Average switching duty cycle for diode D1, D2, D3 and D4 are same as switches Q1 and Q3 = 1/π.

Power Loss can be calculated as follows.

Conduction loss,Pd = Vf × Id ×Dav = 2.2× 10× 1/π = 7W

Where Vf is forward voltage drop and Id is diode conducting current.

Recovery loss per diode, Prr = 0.125× Irr × trr × Vce(p) × fsw

C.1 INVERTER BOARD 85

= 0.125× 3A× 22ns× 600V × 5KHz

= 0.0247W ' 0.5W

Where Irr is reverse recovery current, trr is reverse recovery time and Vce(p) diode breakdownvoltage. Hence, total Power loss across four diodes are,

Diode loss = 4×(Pd + Prr)=4 ×(7+0.5)W = 30W

Heat sink estimation for diode

Normalized thermal response Zθj−c = 0.3 C/W ,

Tj = Ta + Pd(Rθj−c + Rθc−s + Rθs−a)× Zθj−c

125 = 30 + 30 (1.3+2+ Rθs− a) × 0.3

Rθs−a × 30 × 0.3 = 95-29.7

Rθs−a = 7.2 C/W

Appendix D

PSCAD SIMULATION

D.1 SINGLE CYCLE CONTROLLER

A

B Compar-ator

Clear

1sT

Q

QC

S

R

D-

F

+

| X |Io

*1

*.0001

SW

[Inverter] VgVg

[Inverter] IoIo

swsw

[Inverter] VoVo

new_ref1new_ref1

Vcomp

RsIo

RsIoRsIo

VcompVcomp

I

P

D+

F

-

0.4

Vd

[Inverter] VcVc

Phase

Freq

MagCos

0.0

50.0

D+

F

+

|X

|

new_ref

new_ref1

[Inverter] VgridVgrid

new_refnew_ref

Vd

Vc

Vo

new_ref

Vo*

0.0153| X |

Phase

Freq

MagSin

0.0

50.0Vq

[Inverter] Vac_mVac_m

I

P

D+

F

-0.23

Vq

Vac_m

Voabs

new_ref

RMSVo

Single Phase RMS Meter

Vorms

0.613

Vc

[Inverter] PmPm

[Inverter] QmQm

Vorms

1.0

1.0

*

*

D-

F

+

0.2

2

Figure D.1 Single cycle controller

88 APPENDIX D PSCAD SIMULATION

D.2 LOGIC CIRCUIT

A

B Compar-ator

Vo

0.0

A

B Compar-ator0.0

Vo_out

Vo1_out

Vo_out

Vo1_out

SW

SW

Vo1_out

Vo_out

Vo_out

SW

Vo1_out

Vo_out

Vo1_out

SW

1.0

1.0

1.0

1.0

Q1

Q2

Q3

Q4

[Inverter] VoVo

[SCC] swsw

Q1Q1

Q2Q2

Q3Q3

Q4Q4

[SCC] new_ref1new_ref1

new_ref1

Figure D.2 Switching logic circuit

D.3 INVERTER CIRCUIT 89

D.3 INVERTER CIRCUIT

I

I

I

I

VoR=

0

0.05[H]

Io

D D

DD

Vin 0.1 [ohm]

Vg_control

Q3

Q2 Q4

Vd1

Vd2

Vd3

Vd4

Vd

Vl

VgVg

VoVo

IoIo

[Logic] Q1Q1

[Logic] Q2Q2

[Logic] Q3Q3

[Logic] Q4Q4

VdVd

Vd1Vd1

Vd3Vd3

VcVc

Id1

Id2 Id4

Iq1

Iq2

Vgrid

Id3

Iq4

[SCC] new_refnew_ref

[SCC] new_ref1new_ref1

VgridVgrid

1.0

[oh

m]

Vf

Idc

Vg

Vg_control

47

0[u

F]

Ic1 V

A

Vc

Vac_mVac_m

Q1

D

D

D

D

50

.0

*Io

Vo

Sin *

RMS

RMS

Cos

*

A Phase

B

XOR PhaseDifference

Low pass

Butterwth

Order = 6

Vo

Io*

180.0 ph

ph

ph

Qm

Pm

PmPm

QmQm

Inver...

0.45

0.38

Vg control

0.393651

Figure D.3 Inverter circuit

Appendix E

HARDWARE DEVELOPMENT

E.1 CIRCUIT DIAGRAMS

92 APPENDIX E HARDWARE DEVELOPMENT

1 1

2 2

3 3

4 4

DD

CC

BB

AA

1

******

Grid

Connecte

d In

verte

r

1*

10/1

/2008

5:2

4:5

9 PM

C:\P

ram

od\G

CI_

PC

B\G

CI_

top_sheet1

.SchD

oc

Title

Siz

e:

Num

ber:

Date

:File

:

Revis

ion:

Sheet

of

Tim

e:

A4

Vo

1V

cm

p1

Vcm

p2

Vzero

_cro

ssin

g_dete

cto

rV

zero

_cro

ssin

g_dete

cto

r.SchD

oc

oscilla

tor

Vcm

p1

driv

er2

_H

IN

Vcm

p2

driv

er2

_LIN

driv

er1

_H

IN

driv

er1

_LIN

V_I_

cm

p

ff_outp

ut_

Qnot

logic

logic

.SchD

oc

Io_out

Vo

Vo

1

V_I_

monito

ring_ckt

V_I_

monito

ring.S

chD

oc

Vo

Io_out

V_I_

cm

p

ff_outp

ut_

Qnot

Inte

gra

tor_

adder_

compa

rato

rin

t_add_cmp

.Sch

Do

c

driv

er2

_H

IN

driv

er2

_LIN

driv

er1

_H

IN

leg

1_

HO

leg1_LO

driv

er1

_LIN

leg

2_

HO

leg2_LO

IGB

Tdrive

rIG

BT

_drive

r.Sch

Do

c

1 2 3

J2

+-5

V0.1

uF

C3

8

0.1

uF

C3

6

10uF

C3

7

10uF

C3

5

1 2 3

J1

+-1

5V

0.1

uF

C4

2

0.1

uF

C4

0

10uF

C4

1

10uF

C3

9

-15

+1

5+5

-5

1 2

J7

+5is

oc_

gn

d+

5is

o

1 2

J5

Isense

c_

gn

d

oscilla

tor

oscilla

tor

oscilla

tor.S

chD

oc

1 2 3

J3

22

0V

ac

AC

GN

D

1 2

J8

+5is

o1

Ac_

gn

d+

5is

o1

leg

1_

HO

leg1_LO

leg

2_

HO

leg2_LO

IGB

T_outp

ut_

port

IGB

T_

op

_p

ort.S

ch

Do

c

Iac

Va

c

1 2

J6

He

ad

er 2

Vd

c

Fig

ure

E.1

Circu

it

E.1 CIRCUIT DIAGRAMS 93

11

22

33

44

DD

CC

BB

AA

2

* * * * **

Oscill

ato

r

2*

10/1

/2008

5:2

4:5

9 PM

C:\

Pra

mod\G

CI_

PC

B\o

scill

ato

r.S

chD

oc

Title

Siz

e:

Num

ber:

Date

:File

:

Revisio

n:

Sheet

of

Tim

e:

A4

oscill

ato

r

0.0

1uF

C2

0.0

1uF

C3

Cap S

emi

R1

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Appendix F

PUBLISHED PAPER

The following paper has been published in conjunction with the work described in the thesis.

1. P. Ghimire, A. R. Wood. An ultra-cheap grid connected inverter for small scale gridconnection. 3rd International Solar Energy Society Conference, Asia Pacific Region and46th ANZSES Annual Conference, Nov. 2008.

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a development of single cycle control low voltage grid

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