a cost-driven lithographic correction methodology based on off-the-shelf sizing tools

A Cost-Driven Lithographic A Cost-Driven Lithographic

Correction Methodology Correction Methodology Based on Off-the-Shelf Based on Off-the-Shelf

Sizing ToolsSizing Tools




Puneet GuptaPuneet Gupta Andrew B. Kahng Andrew B. KahngUniv. of California, San Diego Univ. of California, San Diego

Dennis Sylvester Jie YangDennis Sylvester Jie YangUniv. of Michigan, Ann Arbor Univ. of Michigan, Ann Arbor

Work partially supported by MARCO GSRC and SRC

OutlineOutlineOutlineOutline

Trends in Mask CostTrends in Mask Cost

Design for ValueDesign for Value

MinCorr: The Cost of Correction ProblemMinCorr: The Cost of Correction Problem

Generic Cost of Correction MethodologyGeneric Cost of Correction Methodology

MinCorr: Parallels to Gate SizingMinCorr: Parallels to Gate Sizing

Experiments and ResultsExperiments and Results

Conclusions and Ongoing WorkConclusions and Ongoing Work

Stringent CD RequirementsStringent CD RequirementsStringent CD RequirementsStringent CD Requirements

ITRS predicts aggressive CD ITRS predicts aggressive CD control as a critical issuecontrol as a critical issue

Resolution Enhancement Resolution Enhancement Techniques (RETs) such as Techniques (RETs) such as Optical Proximity Correction Optical Proximity Correction (OPC) and Phase Shift Mask (OPC) and Phase Shift Mask (PSM) used(PSM) used

YearYear 20012001 20042004 20072007

Technology NodeTechnology Node

MPU Gate LengthMPU Gate Length

Gate CD Control(3Gate CD Control(3))

130nm130nm

90nm90nm

5.3nm5.3nm

90nm90nm

37nm37nm

3.0nm3.0nm

65nm65nm

25nm25nm

2.0nm2.0nm

Mask Cost ComponentsMask Cost ComponentsMask Cost ComponentsMask Cost Components

Writing-Optical or e-beam

Defect Inspection

Defect Repair

Data Prep.-OPC conversion/e-beam file

Materials

Others

0 10 20 30 40

Weight in Mask Cost (%)

Mask Data VolumeMask Data VolumeMask Data VolumeMask Data Volume

180nm 130nm 90nm 70nm0

50

100

150

200

250

300

350M

EB

ES

Da

ta V

olu

me

(G

B)

MEBES Data Volume vs. Technology Node

Large data volume Long mask write times Increase in mask cost

Trends in Mask CostTrends in Mask CostTrends in Mask CostTrends in Mask Cost

RETs increase mask feature complexities and hence mask RETs increase mask feature complexities and hence mask costscosts

No. of line edges increase by 4-8X after OPC No. of line edges increase by 4-8X after OPC (for vector scanning) increased mask write time(for vector scanning) increased mask write time

““Million dollar mask set” in 90nm (Sematech, 2000)Million dollar mask set” in 90nm (Sematech, 2000)

Average mask set produces only 570 wafers Average mask set produces only 570 wafers amortization of mask cost is difficultamortization of mask cost is difficult

Mask writers work equally hard to perfect critical and non-Mask writers work equally hard to perfect critical and non-critical shapescritical shapes

Errors found in either during mask inspection will cause the Errors found in either during mask inspection will cause the mask to be discardedmask to be discarded

RET and mask write are function-oblivious!RET and mask write are function-oblivious!


Trends in Mask CostTrends in Mask Cost

Design for ValueDesign for Value






Design for ValueDesign for Value**Design for ValueDesign for Value**

Mask cost trends Mask cost trends Design for Value (DFV)Design for Value (DFV) methodologies methodologies

Design for Value Problem:Design for Value Problem:

GivenGivenPerformance measure Performance measure ff

Value function Value function v(f)v(f)

Selling points Selling points ffii corresponding to various values of corresponding to various values of ff

Yield function Yield function y(f)y(f)

Maximize Maximize Total Design Value = Total Design Value = ii y(f y(fii)*v(f)*v(fii))

[or,[or, Minimize Minimize Total Cost]Total Cost]

Probabilistic optimization regimeProbabilistic optimization regime* * See See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", IEEE ASIC/SoC IEEE ASIC/SoC

ConferenceConference, September 2002, pp. 411-415., September 2002, pp. 411-415.

DFV At Process LevelDFV At Process LevelDFV At Process LevelDFV At Process LevelInject concept of function into mask flowInject concept of function into mask flow

Selective OPCSelective OPCVarious levels of OPC depending on timing Various levels of OPC depending on timing and yield criticality of featuresand yield criticality of featuresObtain desired level of parametric yieldObtain desired level of parametric yield

Printability: some min level of OPC is requiredPrintability: some min level of OPC is required

No OPC Medium OPC Aggressive OPC* Figure courtesy: Kurt Wampler, ASML Mask Tools, Inc.


Trends in Mask CostTrends in Mask Cost Design for ValueDesign for Value






Performance Measure = DelayPerformance Measure = DelayPerformance Measure = DelayPerformance Measure = Delay

Selling point delaySelling point delay = circuit delay which achieves = circuit delay which achieves desired level (say 99%) of parametric yielddesired level (say 99%) of parametric yield

Goal: Achieve selling point delay with minimum Goal: Achieve selling point delay with minimum cost of RET’s (OPC)cost of RET’s (OPC)

MinCorr: The Cost of Correction MinCorr: The Cost of Correction DFV ProblemDFV Problem

MinCorr: The Cost of Correction MinCorr: The Cost of Correction DFV ProblemDFV Problem

GivenGiven: : Admissible levels of correction for each Admissible levels of correction for each layout feature and the corresponding layout feature and the corresponding delay impact (mean and variance)delay impact (mean and variance)

FindFind: : Level of correction for each layout feature Level of correction for each layout feature such that a prescribed selling point such that a prescribed selling point delay is attaineddelay is attained

ObjectiveObjective:: Minimize total cost of corrections Minimize total cost of corrections


Trends in Mask CostTrends in Mask Cost Design for ValueDesign for Value MinCorr: The Cost of Correction ProblemMinCorr: The Cost of Correction Problem





Statistical Timing AnalysisStatistical Timing AnalysisStatistical Timing AnalysisStatistical Timing Analysis

Statistical STA (SSTA) provides PDFs of arrival Statistical STA (SSTA) provides PDFs of arrival times at all nodestimes at all nodes

A

BArrivaltime

C

Gate delay

Arrivaltime

Propagate arrival time distribution

Variation Aware Library ModelVariation Aware Library ModelVariation Aware Library ModelVariation Aware Library Model

Capacitance and delay values replaced by (Capacitance and delay values replaced by (,,) pair) pair

Sample variation aware .libSample variation aware .lib

pin(A) {pin(A) {

direction : input;direction : input;

capacitance : (0.002361,0.0003);capacitance : (0.002361,0.0003);

}}

… …

timing() {timing() {

related_pin : "A";related_pin : "A";

timing_sense : positive_unate;timing_sense : positive_unate;

cell_rise(delay_template_7x7) {cell_rise(delay_template_7x7) {

index_1 ("0.028, 0.044, 0.076");index_1 ("0.028, 0.044, 0.076");

index_2 ("0.00158, 0.004108, 0.00948");index_2 ("0.00158, 0.004108, 0.00948");

values ( \values ( \

“ “(0.04918,0.001), (0.05482,0.0015), (0.06499,0.002)", (0.04918,0.001), (0.05482,0.0015), (0.06499,0.002)",

……..

Generic Cost of Correction Generic Cost of Correction MethodologyMethodology


Statistical STA (SSTA) Statistical STA (SSTA) provides PDFs of arrival provides PDFs of arrival times at all nodestimes at all nodes

Assume variation aware Assume variation aware library models (for library models (for delay) are availabledelay) are available

SSTA

Nominally Correct SP&R Netlist

Min. CorrectedLibrary

Yield Target

met?

EXIT

CorrectionAlgorithm

SSTA

All CorrectionLibraries


Y

N



Statistical STA (SSTA) Statistical STA (SSTA) provides PDFs of arrival provides PDFs of arrival times at all nodestimes at all nodes

Assume variation aware Assume variation aware library models (for library models (for delay) are availabledelay) are available

Statistical STA currently Statistical STA currently has runtime and has runtime and scalability issuesscalability issues

SSTA

Nominally Correct SP&R Netlist

Min. CorrectedLibrary

Yield Target

met?

EXIT

CorrectionAlgorithm

SSTA



Y

N


Trends in Mask CostTrends in Mask Cost Design for ValueDesign for Value MinCorr: The Cost of Correction ProblemMinCorr: The Cost of Correction Problem Generic Cost of Correction MethodologyGeneric Cost of Correction Methodology




MinCorr: Parallels to MinCorr: Parallels to Gate SizingGate Sizing


AssumeAssumeGaussian-ness of distributions prevailsGaussian-ness of distributions prevails + 3+ 3 corresponds to 99% yield corresponds to 99% yield

Perfect correlation of variation along all paths Perfect correlation of variation along all paths Die-to-Die variationDie-to-Die variation 1+21+2 + 3 + 31+21+2 = = 1 1 + 3+ 311 + + 22 + 3 + 322

Resulting linearity allows propagation of (Resulting linearity allows propagation of (+3+3) or ) or 99% (selling point) delay to primary outputs using 99% (selling point) delay to primary outputs using standard Static Timing Analysis (STA) toolsstandard Static Timing Analysis (STA) tools



Gate SizingGate Sizing MinCorrMinCorr

Cell AreaCell Area Cost of correctionCost of correction

Nominal DelayNominal Delay Delay (Delay (+k+k) )

Cycle TimeCycle Time Selling point delaySelling point delay

Die AreaDie Area Total cost of OPCTotal cost of OPC

Gate Sizing Problem:

Given allowed areas and corresponding delays of each cell,

minimize total die area subject to a cycle time constraint

costs of correctioncosts of correction delay (delay (+k+k))

cost of OPCcost of OPC selling point delayselling point delay

MinCorr

Components of MinCorr SizingComponents of MinCorr SizingComponents of MinCorr SizingComponents of MinCorr Sizing

A yield-aware library that capturesA yield-aware library that captures

Delay mean and variance for each library Delay mean and variance for each library master for each level of correctionmaster for each level of correction

Relative cost of OPC for each master Relative cost of OPC for each master corresponding to each level of correctioncorresponding to each level of correction

Use standard off-the-shelf logic synthesis tool to Use standard off-the-shelf logic synthesis tool to perform sizingperform sizing

Can use well-tested sizing methodsCan use well-tested sizing methods

Practical runtimesPractical runtimes

Can handle interesting variants, e.g., Can handle interesting variants, e.g., cost-constrained selling point delay minimizationcost-constrained selling point delay minimization

MinCorr: Yield Aware Library MinCorr: Yield Aware Library CharacterizationCharacterization

MinCorr: Yield Aware Library MinCorr: Yield Aware Library CharacterizationCharacterization

Mask cost is assumed proportional to number of layout Mask cost is assumed proportional to number of layout featuresfeatures

Monte-Carlo simulations, coupled with linear interpolation, Monte-Carlo simulations, coupled with linear interpolation, are used to estimate delay variance given the CD variationare used to estimate delay variance given the CD variation

We generate a library similar to Synopsys .lib with (We generate a library similar to Synopsys .lib with (+3+3) ) delay values for various output loadsdelay values for various output loads

Cost modeled by relative figure count multiplied by the Cost modeled by relative figure count multiplied by the number of transistors in the cellnumber of transistors in the cell

Gate input capacitance variation with CD consideredGate input capacitance variation with CD considered


Trends in Mask CostTrends in Mask Cost Design for ValueDesign for Value MinCorr: The Cost of Correction ProblemMinCorr: The Cost of Correction Problem Generic Cost of Correction MethodologyGeneric Cost of Correction Methodology MinCorr: Parallels to Gate SizingMinCorr: Parallels to Gate Sizing



Experiments and ResultsExperiments and ResultsExperiments and ResultsExperiments and Results

Synopsys Design Compiler used as the synthesis tool to perform Synopsys Design Compiler used as the synthesis tool to perform “gate sizing”“gate sizing”

Figure counts, critical dimension (CD) variations derived from Figure counts, critical dimension (CD) variations derived from Numerical Technologies OPC toolNumerical Technologies OPC tool**

Use a restricted TSMC 0.13 Use a restricted TSMC 0.13 m librarym library7 cell masters: BUF, INV, NAND, NOR7 cell masters: BUF, INV, NAND, NOR

Approach tested on small combinational circuits Approach tested on small combinational circuits alu128: 8064 cellsalu128: 8064 cells

c7552: 2081 cell ISCAS85 circuitc7552: 2081 cell ISCAS85 circuit

c6288: 2769 cell ISCAS85 circuit c6288: 2769 cell ISCAS85 circuit

**Courtesy Dipu Pramanik, NTICourtesy Dipu Pramanik, NTI

Emulating An SSTA ToolEmulating An SSTA ToolEmulating An SSTA ToolEmulating An SSTA Tool

1.1. Generate 500 random delay values for each Generate 500 random delay values for each library master from the Gaussian distribution library master from the Gaussian distribution N(N(,,))

2.2. Generate 500 random input capacitance values Generate 500 random input capacitance values perfectly correlated with corresponding random perfectly correlated with corresponding random delay valuesdelay values

3.3. Generate 500 .libs having these random delay Generate 500 .libs having these random delay and capacitance valuesand capacitance values

4.4. Monte Carlo PrimetimeMonte Carlo Primetime: Run STA tool 500 : Run STA tool 500 times, each time with a different .lib to obtain a times, each time with a different .lib to obtain a delay distributiondelay distribution

Comparison With SSTAComparison With SSTAComparison With SSTAComparison With SSTA

SSTA emulated by running Synopsys Primetime SSTA emulated by running Synopsys Primetime 500 times with 500 randomly generated .libs500 times with 500 randomly generated .libs

Monte Carlo Primetime is run with Monte Carlo Primetime is run with independently independently varying library masters but all instances of same varying library masters but all instances of same master perfectly correlated master perfectly correlated Die-to-Die (DTD) Die-to-Die (DTD) with some component of Within-Die (WID) with some component of Within-Die (WID) variation modeledvariation modeled

Our (Our (+3+3) propagation approach is accurate for ) propagation approach is accurate for DTD variation but pessimistic in presence of DTD variation but pessimistic in presence of WID variationWID variation

Comparison With SSTAComparison With SSTAComparison With SSTAComparison With SSTA

TestcaseTestcase OPC LevelOPC Level SSTA SSTA ((+3+3) (ps)) (ps)

Our Approach (Our Approach (+3+3) ) (ps)(ps)

alu128alu128

c7552c7552

c6288c6288

AggressiveAggressive

MediumMedium

NoNo


MediumMedium

NoNo


MediumMedium

NoNo

5.0835.083

5.1165.116

5.1815.181

2.4142.414

2.4362.436

2.4772.477

5.1135.113

5.1505.150

5.2215.221

5.285.28

5.365.36

5.575.57

2.492.49

2.542.54

2.642.64

5.295.29

5.385.38

5.585.58

Note: pessimism and fidelity

Yield Library GenerationYield Library GenerationYield Library GenerationYield Library Generation

Three levels of OPC consideredThree levels of OPC considered

Input slew dependence ignoredInput slew dependence ignored

Interconnect variation ignoredInterconnect variation ignored

Type of OPCType of OPC Ldrawn Ldrawn (nm)(nm)

33 of of LdrawnLdrawn

Figure Figure CountCount

Delay (Delay (, 3, 3) for ) for NAND2X2NAND2X2

AggressiveAggressive 130130 5%5% 5X5X (64.82, 2.14)(64.82, 2.14)

MediumMedium 130130 6.5%6.5% 4X4X (64.82, 2.80)(64.82, 2.80)

No OPCNo OPC 130130 10%10% 1X1X (64.82, 4.33)(64.82, 4.33)

Sample Result of Library Generation

Cost Savings with MinCorr SizingCost Savings with MinCorr SizingCost Savings with MinCorr SizingCost Savings with MinCorr SizingDesignDesign Normalized CostNormalized Cost Normalized Selling Point Normalized Selling Point

DelayDelay

alu128alu128 5.0 (Aggressive OPC)5.0 (Aggressive OPC) 0.96440.9644

4.0 (Medium OPC)4.0 (Medium OPC) 0.97390.9739

1.0 (No OPC)1.0 (No OPC) 1.00001.0000

1.06571.0657 0.96440.9644

1.01191.0119 0.99760.9976

c7552c7552 5.05.0 0.94320.9432

4.04.0 0.96210.9621

1.01.0 1.00001.0000

1.46391.4639 0.94320.9432

1.20791.2079 0.98480.9848

c6288c6288 5.05.0 0.94800.9480

4.04.0 0.96420.9642

1.01.0 1.00001.0000

4.15304.1530 0.94800.9480

Cost Savings with MinCorr SizingCost Savings with MinCorr SizingCost Savings with MinCorr SizingCost Savings with MinCorr Sizing

Small (Small (~~5%) selling point delay variation 5%) selling point delay variation between max- and min-corrected versions of between max- and min-corrected versions of design (5X difference in cost)design (5X difference in cost)

Sizing-based optimization achieves 17-79% Sizing-based optimization achieves 17-79% reduction in OPC cost without sacrificing reduction in OPC cost without sacrificing parametric yieldparametric yield


Trends in Mask CostTrends in Mask Cost Design for ValueDesign for Value MinCorr: The Cost of Correction ProblemMinCorr: The Cost of Correction Problem Generic Cost of Correction MethodologyGeneric Cost of Correction Methodology MinCorr: Parallels to Gate SizingMinCorr: Parallels to Gate Sizing Experiments and ResultsExperiments and Results


ConclusionsConclusionsConclusionsConclusions

Function-aware OPC can reduce total cost of OPC while Function-aware OPC can reduce total cost of OPC while still meeting cycle time and yield constraintsstill meeting cycle time and yield constraints

Can modify conventional performance optimization Can modify conventional performance optimization methods to solve the methods to solve the MinCorrMinCorr problem; problem;

We use an off-the-shelf synthesis tool to achieve up to 79% We use an off-the-shelf synthesis tool to achieve up to 79% cost reduction compared to aggressive OPC, without cost reduction compared to aggressive OPC, without increasing selling point delayincreasing selling point delay

Small change in yield going from no to aggressive OPC Small change in yield going from no to aggressive OPC suggests that OPC may be a manufacturability issue suggests that OPC may be a manufacturability issue rather than yield issue rather than yield issue

Ongoing WorkOngoing WorkOngoing WorkOngoing Work

SSTA based correction flowSSTA based correction flow

Apply selective OPC at granularities other than Apply selective OPC at granularities other than gate-level (incl. radius of influence effects)gate-level (incl. radius of influence effects)

Alternative MinCorr solution approaches based Alternative MinCorr solution approaches based on transistor sizing and cost-based delay on transistor sizing and cost-based delay budgeting methodsbudgeting methods

Include interconnect variation in the analysisInclude interconnect variation in the analysis

Make the yield library input slew time awareMake the yield library input slew time aware

Ongoing WorkOngoing WorkOngoing WorkOngoing Work

Current sizing approach models Die-to-Die Current sizing approach models Die-to-Die variation accurately but ignores Within-Die variation accurately but ignores Within-Die (WID) component(WID) component

SSTA with WIDSSTA with WID

Randomly perturbed SDF filesRandomly perturbed SDF files

Monte Carlo PrimetimeMonte Carlo Primetime

Ability to model arbitrary distributions of Ability to model arbitrary distributions of variations variations







Puneet Gupta (Puneet Gupta ([email protected]@ucsd.edu) Andrew B. Kahng ) Andrew B. Kahng

Dennis Sylvester Dennis Sylvester Jie YangJie Yang

Trends in Mask CostTrends in Mask CostTrends in Mask CostTrends in Mask Cost

“$1M mask set” in 100nm

OPC OverheadOPC OverheadOPC OverheadOPC Overhead

OPC increases figure count and mask OPC increases figure count and mask complexitycomplexity

No. of line edges increase by 4-8X after OPCNo. of line edges increase by 4-8X after OPC (for vector scanning) increase in mask write (for vector scanning) increase in mask write

timetime

Rule Based OPCRule Based OPCAll rectangles identically correctedAll rectangles identically corrected

Model Based OPCModel Based OPCEnhancement to a feature made based on its Enhancement to a feature made based on its geometry and local environmentgeometry and local environment

OPC fracturing tools view layout as OPC fracturing tools view layout as function-oblivious GDSII function-oblivious GDSII overcorrectionovercorrection

Toward A Min Cost of Correction Toward A Min Cost of Correction MethodologyMethodology

Toward A Min Cost of Correction Toward A Min Cost of Correction MethodologyMethodology

Many layout features not timing critical Many layout features not timing critical they can tolerate more process variation they can tolerate more process variation

Less-aggressive OPC Less-aggressive OPC lower costs (reduced lower costs (reduced figure counts, shorter mask write times, higher figure counts, shorter mask write times, higher yields)yields)

Printability Printability certain min level of OPC is required certain min level of OPC is required

Selling point delaySelling point delay = circuit delay which achieves = circuit delay which achieves desired level (say 99%) of parametric yielddesired level (say 99%) of parametric yield

a cost-driven lithographic correction methodology based on off-the-shelf sizing tools

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