a cmos field-programmable

8/9/2019 A CMOS Field-Programmable

1/8

1860

IEEE JOURNAL OF SOLID-STATE CIRCUITS,

VOL.

26 N O .

12,

DECEMBER 1991

A

CMOS

Field-Programmable

Analog Array

Edward K. F.

Lee

and P. Glenn Gulak, Member, ZEEE

bstract

-The design details and test results of a f ield-pro-

grammable analog array

(FPAA)

prototype chip in 1.2-pm

CMOS are presented. The analog array i s based on subthresh-

old circuit techniques and consists of a collection of homoge-

neous conf igurable analog blocks (CABS) and a n interconnec-

tion network. Interconnections between CABs and the analog

functions to be implemented in each block are defined by a set

of configuration bits loaded serially into an on-board shift

register by the user. Macro mod els are develop ed for the analog

functions in order to simulate various neural network applica-

t ions on the f ie ld-programmable analog array.

I. INTRODUCTION

IELD-programmable gate arrays for prototyping digi-

F

al circuits are now commercially available from sev-

eral vendors (as in [l]). Conspicuously absent in th e

literature is a field-programmable analog array (FPAA)

and perhaps for good reason-many more challenges

must be addressed such as bandwidth, linearity, signal-

to-noise ratio, frequency response, etc. Noteworthy, how-

ever, are several recent commercial products and publica-

tions in the literature that offer fixed topologies and

programmable coefficients. For example, most single-

chip analog neural network implementations are designed

for a fixed network topology even though the synaptic

weights are programmable [41, 191, [121, [131.

As

pointed

out by Sivilotti [14], it would be advantageous t o devise an

IC strategy whereby various analog networks can be real-

ized, as determined by the user, in some type of reusable

generic prototyping medium. The approach taken in this

paper is to focus on a small number of specialized analog

functions that are realized using subthreshold techniques.

Furthermore, differential circuitry is used for noise immu-

nity, and current-mode signaling provides addition and

subtraction operations. In addition, memory functions

such as integrators, coefficient storage, and sampled ana-

log delay lines are also supported.

As manufacturability and cost consciousness has grown

among circuit designers, an awareness of the importance

of testability has also increased. But, testing of analog

circuits is a difficult task. The FPAA concept provides an

Manu script received M ay 14, 1991; revised July 16, 1991. This work

was supported by an operating grant from NSERC and Micronet .

The authors are with the

VLSI

Research Group, Department

of

Electrical Engineering, University

of

Toronto, Toronto, Canada M5S

1A4.

I E E E Log Number 9103054.

interesting approach to the testing of analog ICs. Since

the circuits in every programmable block are identical,

and since the input and output of each block are accessi-

ble through the routing network, the FPAA provides good

controllability and observability, such that each pro-

grammable analog function can be tested exhaustively.

In addressing these challenging requirements, this pa-

per presents a novel FPAA and associated test results. In

Section 11, we outline various functional requirements for

the implementation of neural networks. Section I11 pre-

sents the design of a configurable analog block (CAB).

Section IV presents the strategy for interconnecting

CABs. Section V discusses the implementation of the

prototype chip and the procedure for loading the coeffi-

cients and for configuration of the array. The experimen-

tal results for the prototype chip are also presented in this

section. The simulation of neural network applications,

using macromodels of the circuits discussed in Section 11,

are discussed in Section VI. Finally, the conclusions are

presented in Section VII.

11.

FUNCTIONAL

EQUIREMENTS

The functions required to implement most neural net-

works are addition, threshold operation, coefficient multi-

plication, and signal multiplication (used in high-order

neural networks). In networks capable of learning, the

coefficient of the coefficient multiplier is often required

to be adjustable. In order to realize these functions in

CMOS technology, a subthreshold circuit technique is

used, offering the advantage of low power dissipation.

Since a neural network usually has many neurons and

synaptic weights, the required circuits must be simple to

permit several functional blocks to be implemented in the

same die. In the following, circuits for realization of the

required functions are presented. These circuits utilize

both differential current-mode and differential voltage-

mode signals. The swing of the voltage-mode signals is

kept small (except for the case of the threshold operation)

to maximize the speed of operation. The operation of

addition among signals is obtained by representing the

signals in current mode and then adding the currents at

the corresponding nodes.

The threshold operation is similar to the behavior of an

analog comparator. It has two states (low and high states)

and a gain region, which is required for the transition

0018-9200/91/ 1200-1860 01

OO

01991 IEEE


2/8

I

I

LEE AND

GULAK CM O S FIELD-PROGRAMMABLE

ANALOG

ARRAY

X

Fig.

1.

Schematic diagram of the current comparator.

I

X

Fig. 2.

Schematic diagram of the signal m ultiplier.

between the two states. Fig. 1shows a simple current

comparator. If there is a difference in current at the input

terminals X , node 1will have a large voltage swing due to

the high impedance at this node. The differential pair

M 3 and M4 ) will act as a voltage-to-current converter,

which converts the input voltage difference at terminal X

to current outputs at terminal

Y The current mirrors

formed by

M 7

and

M 8

together with transistors in the

multiplier take the input differential current defined by

I ,

and

Z,

and mirror it to the specified multiplier differen-

tial input.

The schematic for the signal multiplier is shown in Fig.

2.

This circuit is a classic realization of a four-quadrant

Gilbert multiplier in subthreshold CMOS technology. The

1861

differential output current Y defined by Z, and

Z4

is the

product of the two differential voltage mode inputs

and

2

Furthermore, the coefficient multiplier can be

obtained by removing the

2

input stage (indicated by

dotted lines) and connecting the input

S

of the multiplier

core to a voltage difference stored on a pair of capacitors.

The stored voltage can be refreshed as discussed in [61.

Although the multipliers and the comparators can be

cascaded together, direct connection

of

the multipliers is

not possible. Since this structure is usually desired in

high-order neural networks, a current buffer is designed

for this purpose. The buffer can be obtained by connect-

ing the gate to the drain of M1 in Fig. 1instead of

connecting it to the gate

of M2 .

Since this circuit also

utilizes the translinear technique, the transfer characteris-

tic between the input and output current is very linear.

111. CONFIGURABLENALOG LOCK

A typical [l] field-programmable gate array

(FPGA)

consists of configurable logic blocks (CLBs) that perform

the required logic function and an interconnection net-

work to provide connections between CLBs. The FPAA

presented in this paper is modeled on a similar strategy,

although there are many issues unique to analog circuits

that must be accommodated. The analog functions will be

grouped into CABs and the interconnection network will

connect them together. One important observation, how-

ever, is that the circuit topologies for different functions

are similar. Therefore, different functions can be conve-

niently obtained by configuring the circuit primitives

(Table I(a)> with a few transistors that act as analog

switches (Table I(b)).

The design of the CAB is shown in Fig. 3.The configu-

ration of the CAB is determined by a local 3-b shift

register. Each bit of the shift register controls various

switches and/or multiplexors within the CAB itself. For

example, when the shift register contains the bit pattern

001,

the CAB is configured as a four-quadrant multiplier

with X and

Y

as inputs and

2

as output. Table

I1

shows

all the configurations inside the CAB.

Though various specialized types

of

CABs could be

defined in the same manner, controlling the level of

granularity of the CAB is critical to minimizing the num-

ber of 1 / 0 lines that ultimately must be accommodated

by the interconnection network.

IV. INTERCONNECTIONNETWORK

Interconnection networks can usually be categorized

into two types: crossbar and multistage (hierarchical). The

crossbar interconnection network provides full intercon-

nection capability between any two connected elements,

which is known as nonblocking. It also provides less delay

on da ta transfer. However, the crossbar approach exhibits

an area growth rate of

O ( N 2 )

or connecting N inputs to

N outputs. On the other hand, hierarchical interconnec-

tion networks evolve with slower cost growth. Examples

of

this type of network include Banyan [3],omega [5] ,and


3/8

1862

IEEE JOURNAL OF SOLID-STATECIRCUITS VOL. 26, NO. 12, DECEMBER

1991

Buffer from

X

to

Y

Z = X W

X+AY

Z

1 1 0

TABLE I

D ~ S C R I P T I O N SF (a) THE CIRCUITRIMITIVESND (b) THE SWITCHES

Prlmitive Element

Buffer from X to Y

Z = W

Comparator from X to

Y

Z = X W

X

1.0

+z

1 0

x s:

1 1

Comparator from x to Y

x ~ - > Y _

0 1 1 1 0 *z

z = w

V OL

Loading weight

W

from

GI

and G2

Loaded at AM as -3V and stored

as

w= 3V

1 0 0

Switch Element

Circuit Diagram

K

I

I

K

D*E

Difkrentiml D and E

delta

[ll].

These networks have a cost growth

of

O(N1ogN) at the expense of longer delay between in-

puts and outputs. For the design of the array, the idea of

using a hierarchical network will be appropriate because

of the area requirement. The delay of the network is

acceptable since the CABs utilize current-mode and

small-swing voltage-mode signals which minimize the de-

lay. However, those hierarchical networks mentioned

above are designed for data transfer

or

routing between

two layers of elements. They do not allow connections

between elements in the same layer. Therefore, the ele-

I l l ,

)D V4

I ~

X

V S S l v 5

I

GND

Fig. 3.

Schematic diagram for the CAB.

TABLE I

C ON F I GU R A T I ON S

F THE

CAB

Description Symbol

Signal multiplier

O

O I Y - x * z

I l l I

Signal multiplier (buffered)

2

x

Y = X Z

I

Constant multiplier

Y

=

x W(Z)

ments are not capable of being fully connected. Further-

more, as the CABs are increased, the dimension of the

array will be proportional to

N

x log

N

and the layout of

the array will be rectangular. However, a layout with an

aspect ratio of one is usually desired in a VLSI design.

Consequently, the network mentioned above may not be

suitable for the design of the array.

From a VLSI point of view, the area of the layout is of

most concern. Therefore, the interconnection network

must have the property of area universality

[SI.

A

network that is area universal is a network that, for a

given area, can efficiently embed any circuit whose size is

only slightly smaller. One such area-universal network is a


4/8

I1

LEE AND GULAK CMOS FIELD-PROGRAMMABLE ANALOG ARRAY

1863

W U i

A 0

C

D E

z

Y

Y

The coefficients required by the coefficient multiplier

are loaded before the actual configuration of the entire

array. The bit pattern 100 for the CAB is dedicated to

Fig. 4

~n area-universal fat tree (the

dotted box indicated by

this operation. During the coefficient loading cycle, the

control unit will shift a ONE followed by ZEROS into the

ighlights the motohme imdementation).

_ .

array. When the shift registers of a particular CAB con-

fat tree [8] shown in Fig. 4, which is also a hierarchical

network. In fact, Leiserson

[7]

showed that the fat tree

was near optimum in terms of the number of elements,

required area (or volume), data transfer delay, and growth

rate of routing channel size. Based on this network, the

FPAA

is designed with the CABS (as the leaves of the fat

tree) connected by switch blocks (SBs) in different levels

of the fat tree. The switch blocks can be realized by using

crossbar switches. However, the switch blocks can be

simplified by constraining the number of allowable con-

nections. With this in mind, the switch blocks just above

the leaves are designed as shown in Fig.

5.

The connec-

tions made by this SB will be determined by the contents

of a local 10-b shift register, which is specified by the

user.

The SB also allows for polarity changes of the

differential signals. Therefore, addition or subtraction

among current-mode signals is possible. The overall struc-

ture of the SBs in different levels is designed by repeat-

edly embedding different netlists of various types of cir-

cuits (e.g., a Hopfield network) to the fat-tree network

and appropriately locating the ON/OFF switches to fit

these systems onto the network.

V. IMPLEMENTATIONND PROGRAMMINGF THE

PROTOTYPEESIGN

In order to demonstrate the feasibility of the circuits, a

prototype containing the portion inside the dotted box

(Fig. 4) was designed, which consists of two CABS and an

SB. The shift registers of the SB and the shift registers of

the CAB are connected together as a chain. The configu-

ration bits a re set by shifting the bits into the chip serially.

A control unit is needed to determine the required bit

patterns for the configuration cycles as well as the clock

phases of the shift registers to control the begin and end

of the different cycles.

tain the pattern 100, the global write signal

w

s set low

by the control unit and the required coefficient value will

be loaded to this CAB through the global wires G1 and

G2

with an external differential voltagesource. Before

the next ZERO is shifted into the array,

W

will be reset

high. Since only the first bit is a logic ONE, exactly one

CAB will be in the coefficient loading mode. Therefore,

the coefficients will be loaded into the corresponding

CABs sequentially.

After the coefficient loading cycle, the control unit will

shift a specified bit pattern into the chip. This bit pattern

will determine the operations of the CABS and the

connections bztween CABS. During this cycle, the global

write signal W will always be high in order to prevent

disturbance of the coefficient values. At the end of this

cycle, the clock phases for the shift registers will be kept

low and the analog array is now configured and ready to

operate.

The experimental prototype is fabricated in 1.2-pm

CMOS technology. Some specifications of the CAB and

the SB are shown in Table 111.The die photo of the

prototype chip is shown in Fig. 6.When testing the chip,

one of the

CABs

was configured as a signal multiplier

and the other

one

was configured as a current buffer.

Internal interconnections between the CABs themselves

and the external connections from the chip were through

the SB. The configuration bits were shifted into the chip

by an auxiliary off-chip control circuit. Since inputs to the

signal multiplier require a differential voltage-mode sig-

nal, two external variable voltage sources were used for

one input to the multiplier. The other differential input to

the multiplier was obtained from the output of the cur-

rent buffer. Since the circuits operate in the subthreshold

region, the differential output current is in the nanoam-

pere range. In order to measure current in this range, two

electrometers were used. The dc characteristic of the


5/8

1864

IEEE JOURNAL

OF

SOLID-STATE CIRCUITS,

VOL. 26,

NO.

12,

DECEMBER 1991

TABLE 111

SPECIFICATIONSF THE CAE3 AND

SB

Item Size No . of transistors

of

area for shift registers

CAB

192

p m x 176 p m 98

SB

202

m 1 X 1 9 7 wm

148

=

30

75

Differential

output

current

InAI

Fig. 7.

Fig. 6. Die photo of the prototype chip.

600

400

2

0

200

.

-400

.

. . . . . . . . .

-600

I

-200 -100 0

100

200

Differential input current

[nA]

DC

measurement

of the

output was measured by varying the two current sources

with different fixed voltages at the inputs of the multi-

plier. The results are shown in Fig. 7.The output differ-

ential current was fairly linear with respect to the input

differential current . The worst-case percentage er ror over

the -100- to 100-nA range of the input differential

current was about

2%.

The reduction in the observed

nonlinearity is most likely due to the nonlinearities in the

buffer. Since the MOSFETs in the buffer may not oper-

ate inside the subthreshold region, it may violate the

four-quadrant Gilbert multiplier.

exponential Z

V

characteristic required for the

translinear circuit technique. The output offset current is

about 20 nA, which is

3.5

of the maximum output

current. The noise of the array was measured by taking

samples at a rate of 50 samples/min at the output termi-

nals for an extended period

of

time

(20

mi d. The root

mean square value of the noise was less than

1

nA.

Another experiment involved the use of the current

comparator by configuring one of the CABSwith the bit

pattern

011.

The connections between the

CABS

and the


6/8

I m i

LEE AND GULAK CMOS FIELD-PROGRAMMABLEANALOG ARRAY

1865

1

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . .

Differential

output

current

[nAl

120go

-100 -50

0

SO

100

Differential input current [nA]

Fig. 8.

DC

measurement for the comparator in cascade with the Gilbert multiplier.

Fig.

9.

Model of the current buffer. (Note that Ri

1

MR/number

of fan-ins.)

instruments were the same as the previous example.Fig.

8

shows the experimental results, which were compared

with the HSPICE simulations. The experimental results

had an offset current

of

about 30 nA.

VI. SIMULATIONS

S I N G

ACROMODELS

In this section, the analog operations discussed above

are modeled by a set of simple circuit models. These

models are then used in the simulation of the neural

networks to reduce the computational requirements.

A Macromodels of the Circuits

The macromodels are developed by first simulating the

dc and ac characteristics of the analog operations and

then modeling the operations with sets

of

resistors, capac-

itors, and dependent sources according to the simulation

results derived from the extracted layout. As an illustra-

tion, the schematic diagram of the model for the current

buffer is shown in Fig.

9.

The models of other analog

functions can be obtained using the same procedures.

Different values of the resistors, capacitors, and depen-

dent sources may be obtained if different processes are

used. During the simulation of the circuits, the biasing

current is set to 100 nA. The dc and ac characteristics of

the models and the actual circuits are well matched.

Nevertheless, the settling time of the actual circuit is

longer than that of the model since the impedance of the

actual circuit is varying as a function of the input differen-

tial current while the model has constant impedance over

the entire input range. However, the model still provides

a lower bound for the settling time. The model

of

the

constant multiplier is the same as the signal multiplier

with one of the inputs set to a constant differential

voltage. Since the loading of the voltages to the analog

memories is not involved in the simulations, the model of

this operation is omitted. The model for the interconnec-

tion switches is modeled by an RC network. The esti-

mated wiring capacitance is also included in the model.

B.

Neural Network Simulation Using the Macromodels

Based on the models developed, the multilayer feedfor-

ward network and the Hopfield network are simulated to

illustrate the application of the FPAA in this area. Fig. 10

shows the schematic diagram of a single-layer neural

network realized by the circuits discussed above. Four

switches are assumed in each connection between differ-

ent functions. The weights of the network were obtained

by training the network with the delta rule [ 2 ] .The input

differential voltage values of the multiplier models a re set

according to the resulting normalized weight values. The

input and output patterns used during training are shown

in

Table IV. T he response of the network is correct and

shown in Fig. 11.

The behavior of the networks due to the offset errors of

the circuit is also studied and simulated with the use of a

multilayer network to solve the classic

EXCLUSIVE-OR

problem. Table V shows the corresponding input and

output patterns. The simulation results are shown in Fig.

12 with the values of the constant differential current

sources randomly disturbed in the range of

-2.5

to

2.5


7/8

1866

m u m n

Input

IEEE JOURNAL

OF

SOLID-STATE CIRCUITS, VOL. 26, NO. 12, DECEMBER 1991

ourput

Fig.

10.

Schematic diagram of the single-layer network.

TABLE IV

INPUT

AND

OUTPUT

A-ITERNSOR

THE SINGLE-LAYER NETWORK

Input pattern Output pattern

~ ~ ~~~~

-

1,

+

1,

,

1,

1)

+

1,

1,

+ 1, ,

1)

( + l ,

1, , - 1 , - 1 )

( - 1 , + l )

+

1, 1)

+ L

1 )

r s p o m c 01 neuron

6

r cbPo l c of neuron 1

. . . .

5 7

I

I I

loo - - .

I

I

0

1.2 2.4

3 6

time [psec]

Fig. 11. Simulation results for the single-layer network.

TABLE

V

INPUTAND OUTPUT

A ~ E R N SOR

THE

EXCLUSIVE-OR PROBLEM

Input pattern Output pattern

nA (1.25 of the maximum input current) with the same

biasing current. The network still provides the correct

response. When the offsets are in the range of 0 to 10

nA

5 of the maximum input current), incorrect results

were produced as shown in Fig. 13. As shown in the

simulation, the offset errors of the circuits may affect the

performance of the neural networks.

neuron

5

output

current

[nAI

I 1 I

0

1 2 3

40

time p e c )

Fig.

12.

Simulation results for the

EXCLUSIVE-OR

problem with offset

in the range of

.5 to 2.5

nA.

neuron 5

output

[nAl

current

I I

I

I

U 1 20 3 40

time

psec ]

Fig. 13.

Simulations results for the

EXCLUSIVE-OR

problem with offset

in the range

of

0 to 10nA.

For the case of Hopfield network, the patterns are

stored at the minimum points of the following energy

function:

where

oi

the output of neuron

i

wi j

the weight from i to j

i

the constant input to neuron

i

The offset errors of the circuits are incorporated into the

constant input Bi7sand therefore may affect the minimum

points of the above function.

A n

incorrect pattern will be

recalled unless the minimum points are widely spread. If

a correct pattern is recalled, the offset errors will cause a

variation in the settling time. Fig. 14 shows the schematic

diagram of a four-neuron Hopfield network. The output

of the network with random offset errors in the range of

-15 to 15 nA (3.75 of the maximum input current) at

the input of each neuron is shown in Fig. 15. The weights

of the network are obtained by the outer-product rule

[lo]. The network has two minimum points which are

+

1, ,

+

1, ) and

-

1, 1,

,

1). Since the two

points are widely spread, the resulting pattern is correct

but various settling times are evident with various random

offset errors.


8/8

I1

LEE

AND GULAK: CMOS FIELD-PROGRAMMABLE ANALOG ARRAY

1867

I

I4

1 17

OUQUl

Fig.

14.

Schematic diagram of the H opfield network.

I

I

U 0

5

1

1 5

1

time [psec]

Fig. 15.

Simulation results for th e Hopfield network.

VII. CONCLUSION

The concept of developing a field-programmable ana-

log array (FPAA) to realize different neural network

topologies is proposed. The array is designed using sub-

threshold circuit techniques to achieve very low power

dissipation. The interconnection network is based on an

area-universal fat tree. Consequently, the layout of the

array is compact and area efficient. n experimental

prototype design was successfully implemented and tested.

The prototype can be dynamically reconfigured to per-

form various analog functions. A set of macromodels for

the circuits is developed. These models are then used in

the simulation of various neural networks. Based on the

prototype and simulation results, the FPAA concept ap-

pears to be a promising candidate for neural network

applications.

ACKNOWLEDGMENT

The authors thank Prof. S. Zukotynski for generous

access to the Keithley SMUs and to Oswin Hall for

designing the PC interface unit. Fabrication support by

CMC is gratefully acknowledged.

REFERENCES

[ l ]

The Programmable Gate Array Data

Book, Xilinx, San Jose, CA,

1989.

[2] G.

E. Hinton,

D.

E. Rumelhart , and R. J . Will iams,

Parallel

Distributed Processing: Explorations in the Microstructure of Cogni-

tion,

vol.

1, Foundations.

[3] L. R. Coke and G.

J.

Lipovski, Banya n networks for partitioning

multiprocessing system, in

Proc. 1st Annual Computer Architecture

[4] H.

P.

Graf and L.

D.

Jackel, Analog electronic neural network

circuits, IEEE Circuits Devices Mag.,

vol.

5 ,

no.

4,

pp.

44-49,

July

1989.

[5]

D. H. Law rie, Access and alignme nt of data in an array processor,

IEEE Trans. Comput.,

vol.

C-24,

pp.

1145-1155, 1975.

[6] E. K. F. Lee, Field programm able analog arrays-A CM OS

realization, M.A.Sc. thesis, Univ. Toronto , Toro nto, Ont., Canada ,

1991.

[7] C. E. Leiserson, Fat-trees: Universal networks for hardware-effi-

cient supercomputing,

IEEE Trans. Comput.,

vol.

C-34,

no.

10,

pp.

181

C. E. Leiserson,

VLS Theory and Parallel Supercomputing.

Cam-

bridge, M A MIT Press,

1989.

[9] J.

Mann,

R.

Lippmann, B. Berger, and

J.

Raffel, A self-organizing

neural net chip, in

Proc. IEEE

1988

Custom Integrated Circuits

Conf., 1988,

pp.

10.3.1-10.3.5.

[ l o ] R.

J.

McEliece, E. C. Posner, E.

R.

Rodemich, and S.

S.

Venkatesh,

The capacity of the Hopfield associative memory,

IEEE Trans.

Inform. Theory,

vol.

IT-33,

no.

4,

pp.

461-482,

July

1987.

[111 J.

H. Patel, Processor-memory interconnections for multiproces-

sors, in Proc. 6th Annual Symp. Computer Architecture, 1979, pp.

168- 177.

[

121 J. I.

Raffel, Electronic implementation of neuromorphic systems,

in

Proc. IEEE I988 Crrstom Integrated Circuits Conf. 1988,

pp.

1131

D.

B.

Schwartz, R. E. Howard, and

W .

E. Hubbard , A pro-

grammable analog neural network chip,

IEEE. J . Solid-state Cir-

cuits,

vol.

24,

no.

2,

pp.

313-319,

Apr.

1989.

[14]

M. A. Sivilotti, A dynamically configurable architecture for proto-

typing analog circuits, in

Advanced Res. VLSI: Proc. Decennial

Caltech Conf . VLSI .

Cambridge, M A MIT Press,

1986.

Conf.

1973, pp. 21-28.

892-901, 1985.

10.3.1- 10.3.5.

Cambridge, MA: MIT Press,

1988.

I

systems for signal proc

Edward K.

F.

Lee received the B.A.Sc degree

from the University of Windsor, Windsor, Ont.,

Canada, in

1988

and the M.A.Sc degree from

the University of Toronto, Toronto, Ont., in

1991. Currently, he is with the Department of

Electrical Engineering, University of Toronto,

where he is working towards the Ph.D. degree.

His research interests are in the areas of ana-

log/digitalessing. circuits, VLSI design, and signal pro-

P.

Glenn Gulak

(S82-M83)

received the Ph.D.

degree in electrical engineering from the Uni-

versity of Manitoba, Winnipeg, Man., Canada.

From February 1985 to January 1988 he was a

Research Associate in the Information Systems

Laboratory and the Computer Systems Labora-

tory at Stanford University, Stanford, CA.

Presently he is an Assistant Professor in the

Department of Electrical Engineering at the

University of Toront o, Toronto, O nt., Canada .

His research interests include VLSI circuits and

essing and digital communications.

a cmos field-programmable

Documents