JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2016.16.6.873 ISSN(Online) 2233-4866

Manuscript received Aug. 25, 2016; accepted Nov. 18, 2016 Dept. of Radio Science and Engineering, Kwangwoon University, Korea E-mail : hshin@kw.ac.kr

A CMOS Charge Pump Circuit with Short Turn-on Time for Low-spur PLL Synthesizers

Jihoon Sohn and Hyunchol Shin

Abstract—A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 mA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory. Index Terms—Charge pump, reference spur, PLL, CMOS

I. INTRODUCTION

In the RF transceivers, charge pump type-II PLL synthesizers are widely used for generating LO signals to up-/down-conversion mixers. Compared to type-I PLL, type-II charge pump PLL provides several advantages such as wider locking range and smaller static phase error in locked condition. The smaller static phase error translates to smaller spurious tones at the output. In

addition to an ideal rectangular output current waveform, charge pump circuit’s non-idealities create additional unwanted current that is added to the ideal part. Such unwanted residual and periodic output current at the locked condition leads to a periodic ripple voltage at the VCO’s tuning node. As a result, spurious tones are generated at the output spectrum. The spurious tones appear at the harmonics of the reference frequency away from the carrier frequency and commonly referred to as reference spur. The reference spur at the LO signal deteriorate the receiver’s signal-to-noise ratio and the transmitter’s adjacent channel, thus must to be minimized.

Typically, minimizing loop bandwidth can improve the reference spur. However, it is not that much straightforward because changing the loop bandwidth can also affect other performance parameters such as lock time, stability, and phase noise. Thus, for improving the spur, it is important to suppress the unwanted output current that is mainly caused by the non-idealities of the charge pump circuit.

The non-idealities of a charge pump circuit are usually dominated by three characteristics, which are leakage current during off-state, mismatch between the up-/down-current magnitudes, and mismatch between the up-/down-current pulse timing [1]. The three non-ideal characteristics result in the unwanted output current at the locked state. The total output current at the locked state can be expressed as

Itotal(t) = Ileak(t) + Imismatch(t) + Itiming(t) (1)

where Ileak(t), Imismatch(t) and Itiming(t) are the output current components due to the leakage, the current magnitude

874 JIHOON SOHN et al : A CMOS CHARGE PUMP CIRCUIT WITH SHORT TURN-ON TIME FOR LOW-SPUR PLL SYNTHESIZERS

mismatch, and the timing mismatch, respectively. Then, Itotal(t) can be expanded by Fourier series as

1

( ) refjk ttotal k

k

I t c e w¥

=

=å (2)

where ck is the Fourier coefficient of the k-th harmonic component. In (2), c1 is the amplitude of fundamental component that corresponds to the reference spur. In practice, accurate prediction of the reference spur through full analysis of the total charge-pump current would require very complex modeling and simulations [2, 3]. More practical approach is to analyze only the amplitudes of three components and add them together to obtain the worst-case spur magnitude. The analytic expressions of the three components can be found in [4], and the worst-case c1,total is given by

1, 1, 1, 1,

2

2

total leak mismatch timing

on onDleak cp cp

ref ref ref

c c c c

T TTI I IT T T

p p

= + +

æ ö= + D +ç ÷ç ÷

è ø

(3)

where Icp, Ileak, DIcp, Ton, Tref and TD are charge pump current, leakage current in off-state, mismatch of the up-/down-current magnitudes, charge pump turn-on time in locked state, reference clock period, and timing mismatch, respectively. Eq. (3) implies that reducing the turn-on time Ton is most desired for minimizing c1,total, and consequently the spur. Ton is also referred to as minimum pulse width of the charge pump output current during the locked state. Since Ton is determined by the charge pump circuit’s switching speed, a fast charge pump circuit with very short turn-on time is needed for minimizing spur. This work presents a new charge pump circuit with significantly reduced turn-on time compared to conventional circuits.

II. CIRCUIT DESIGN

Fig. 1 is the schematic of a conventional source-switching charge pump. M3-M6 and M10 form the current mirror part, and M1 and M7 are switches at the sources of M3 and M5, respectively. M2 and M8 are replicas of M1 and M7, respectively, which are used for better control of the output current in on-state. Source-switching charge

pump has a benefit such that the clock feedthrough and charge sharing is alleviated because switches are placed near the supply rails. However, when UP and DN switches enter the off state, the source nodes of M3 and M5 becomes floated without any discharging path, hence the current source transistors, M3 and M5, cannot be turned off instantaneously.

Previous charge pump circuit in [5] addressed this issue by employing additional discharging transistors, Mx and My, as shown in Fig. 1. When switches are turned off, Mx and My ensure a fast turn-off of M3 and M5 by removing the channel charge from their source nodes to VDD and ground, respectively. However, in this method, the source nodes of M3 and M5 are re-connected to ground and VDD during the subsequent turn-on transition. Thus the source nodes inevitably experience large variation of Vgs, which leads to the large current glitch especially if the turn-on time is short. Adding C1 and C2 as proposed in [6, 7] can reduce the current glitch to some extent due to the low pass filtering characteristic,

Fig. 1. Conventional charge pump.

Fig. 2. Proposed charge pump.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 875

but at the price of slower rising time of current pulse. Thus, this method also leads to long turn-on time, thus poor reference spur.

Fig. 2 is the proposed charge pump circuit. The main differentiation is to provide optimum voltages VBP and VBN to the sources of M5 and M3 by employing the unity gain buffers A2 and A3, respectively. Conventional methods have fed supply voltage and ground to these nodes. However, the proposed circuit uses optimum voltages VBP and VBN that are close to the gate voltage of current source transistor M5 and M3. For instance, the optimum gate voltages of M5 and M3 in this design are found to be 0.69 V and 0.25 V, respectively. We have found that these optimum voltages are not much dependent on the output voltage variation. Moreover, automatic control and tracking of VBP and VBN over process, voltage, and temperature variations can be easily achieved if we directly connect VBP to M5 gate node and VBN to M3 gate node. It makes Vgs5 and Vgs3 to zero during off-state. As a result, the output current of charge pump can become zero quickly. This technique dramatically suppresses the unwanted current glitch because Vgs of M3 and M5 do not go through large variation during turn-on transition. Another advantage of this circuit is that the rising time of charge pump current is significantly shortened because it eliminates the capacitors C1 and C2 at the source nodes of the conventional circuit of Fig. 1.

A rail-to-rail opamp is used for A1 to improve the UP/DN current mismatch over a wide range of the output voltage between 0.15 and 0.85 V under the 1 V supply. Fig. 3 shows the schematic of A1. A1 consists of a common-mode adapter and a single-stage amplifier [8]. Note that when the common mode level of VINP and VINN is higher than VREF, where VREF is the maximum input common mode level of the single-stage amplifier, the common-mode adapter lowers the common-mode level at the M11,12 input nodes by subtracting the IR drop from the VIN common-mode level. On the other hand, A2 and A3 are conventional two-stage opamp with NMOS and PMOS input stages, respectively.

The charge pump is designed in 65 nm CMOS and simulated to verify the performances. It consumes 490 mA from 1 V supply, of which the 220 mA is consumed by the charge pump core and the 270 mA is consumed by the two opamp A2 and A3. Although the

additional circuitry slightly increases the current consumption, this can be negligible considering that typical PLL synthesizers dissipate several milliamperes. Fig. 4 shows the simulation results of the transient current pulse waveforms. The simulations are carried out with an ideal voltage source of half VDD connected at the charge pump output node. Thus the results can be considered as the intrinsic switching characteristics of the charge pump circuit. Note that the pulse waveforms of the conventional circuit shown in Fig. 4(a) become severely distorted when the turn-on time is less than 0.5

I1

R R

I2

M13M9M10M8 M14

M2 M3

M4

M1

M5 M6M7

M12M11VINN

VINP VINN

VREF VINP

Vout

VDD

Common-mode adapter Single-stage amplifier

Fig. 3. Rail-to-rail opamp.

(a)

(b)

Fig. 4. Output current waveform of (a) the conventional charge pump, (b) the proposed charge pump.

876 JIHOON SOHN et al : A CMOS CHARGE PUMP CIRCUIT WITH SHORT TURN-ON TIME FOR LOW-SPUR PLL SYNTHESIZERS

nsec. In contrast, the current pulse waveforms of the proposed circuit as shown in Fig. 4(b) are much more like an ideal pulse waveform. It proves that the proposed charge pump circuit is fast enough to operate successfully with the turn-on time as short as 0.1 nsec without any significant waveform distortion and noticeable current glitch. The current gain of the charge pump can be obtained by differentiating the total net charge over a single period with respect to the time. Fig. 5(a) is the current gain of the conventional charge pump. It exhibits non-constant current gain with respect to the time difference between up/down pulse. It also implies that the dead-zone occurs when the turn-on time is shorter than 0.2 nsec. In contrast, Fig. 5(b) clearly exhibits almost constant current gain with respect to the entire range of turn-on time.

III. MEASUREMENT RESULTS

The proposed charge pump circuit is employed for a

1.1–1.6 GHz type-II PLL synthesizer. In order to observe and verify the effects of the turn-on time on the spur performance, the turn-on time is designed to be tunable between 0.1 and 0.5 nsec. The chip is fabricated in 65 nm CMOS process and the chip micrograph is shown in Fig. 6. The die size is 1.78×1.38 mm2. The circuit is tested after directly mounted on a printed circuit board. The reference clock frequency is 26 MHz. Fig. 7(a) shows the measured PLL output spectrum at 1.456 GHz, for which the turn-on time is set to 0.5 nsec. Such large turn-on time implies that the charge pump circuit is conventional so that the minimum pulse width is large. Note that the reference spur is -73.6 dBc. Then, with the turn-on time shortened to 0.1 nsec, the output spectrum is measured again as shown in Fig. 7(b). As can be seen, the reference spur is -81.1 dBc, which is 7.5 dB improvement. It clearly indicates that the proposed charge pump circuit allows a very short turn-on time, which can result in significant reference spur improvement.

The effect of the turn-on time on the spur performance can be theoretically verified by using c1,total in (3). Note that c1,total in (3) explains how the three non-ideal effects are translated to the ripple voltage on Vtune and eventually to the reference spur. However, in practice, there can be more coupling paths involved, which in turn increases the ripple voltages further than this. For example, Fig. 8 illustrates that the periodic switching operation of PFD and charge pump can cause additional periodic perturbation on the supply, ground and substrate voltages. Such perturbation can lead to much higher spur than predicted by c1,total [4]. Thus, we adopt an empirical parameter h to reflect the practical situations, and

(a)

(b)

Fig. 5. Current gain against the UP/DN pulse time difference(a) the conventional charge pump, (b) the proposed charge pump.

Fig. 6. Chip micrograph.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 877

introduce a new coefficient c1,out by multiplying c1,total by h as

1, 1,out totalc h c» × (4) Meanwhile, the ripple voltage on Vtune is determined

by the product of the impedance of the loop filter and ( )total tI in (1). Note that in the loop filter as shown in

Fig. 8, the series Rz and CI typically has a much larger time constant compared to the reference period for the sake of loop stability. This mean that only Cp is considered to be charged and discharged during the reference frequency cycles [9]. So the reference spur can

be expressed as following.

1,

20log2

1 2 20 log

2

vco ripple

ref

vco out ref p

ref

K VSpur

f

K c j f C

f

p

×=

× ×=

(5)

Fig. 9 shows the measured and computed reference spurs with respect to the turn-on time. For the theoretical computation of (5), the PLL design parameters are used such that the reference frequency is 26 MHz, the charge pump current Icp is 60 mA, Cp is 143 pF, Kvco is 40 MHz, the leakage current Ileak is 4 nA, the timing mismatch TD is 50 ps, and the current mismatch is 10 %. The empirical factor h of 500 is also assume. It can be clearly seen that the theoretically computed predictions are agreed well with the measured results. PLL performances are summarized and compared with other recent works in Table 1. The proposed PLL shows the most excellent reference spur levels.

(a)

(b)

Fig. 7. (a) Measured PLL output spectrum with 0.5 nsec turn-on time, (b) Measured PLL output spectrum with 0.1 nsec turn-on time.

Fig. 8. Periodic perturbation on the supply, ground and substrate voltage.

Fig. 9. Reference spur with respect to turn-on time.

878 JIHOON SOHN et al : A CMOS CHARGE PUMP CIRCUIT WITH SHORT TURN-ON TIME FOR LOW-SPUR PLL SYNTHESIZERS

V. CONCLUSIONS

A charge pump with very short turn-on time is presented for very low reference spur PLL. The proposed charge pump effectively reduces the rising times of the output current and suppresses the current glitch. As a result, this circuit can reduce the turn-on time significantly, and thus improve the reference spur in CMOS PLLs.

ACKNOWLEDGMENTS

This work was supported by Institute for Information and Communications Technology Promotion (IITP) grant funded by the Korea Government (MSIP) (R7117-16-0169, Development of Ultra-Low-Power Dual/Wide-Band MICS/BAN Transceiver for Capsule Endoscopy) and (R7119-16-1009, Development of Intelligent Semiconductor Core Technologies for IoT Devices based on Harvest Energy)

REFERENCES

[1] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,”, IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 545-548, May 1999.

[2] N. Kamal, S. Al-Sarawi, and D, Addott, “An Accurate Analytical Spur Model for an Integer-N Phase-Locked Loop,” Int. Conf. on Intelligent and Advanced Systems, vol. 2, pp. 659-664, Jun. 2012.

[3] D. Mandal, P. Mandal, and T. K. Bhattacharyya, “Prediction of reference spur in frequency

synthesisers,” IET Circuits, Devices & Systems, vol 9, no. 2, pp. 131-139, 2015.

[4] K. Shu and E. Sanchez-Sinencio, CMOS PLL Synthesizers, Boston, MA, Springer 2005.

[5] P. Larsson, “A 2–1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability,” IEEE J. of Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Dec. 1999.

[6] J. M. Ingino, “A 4GHz 40dB PSRR PLL for an SOC Application,” IEEE Int. Solid-State Circuits Conf., Dig., pp. 392-393, Feb. 2001.

[7] K. D. Feng and J. C. Lee, “Spark current in charge pump of phase lock loop,” IEEE Custom Integrated Circuits Conf., pp. 199-202, Sept. 2005

[8] M. Peng, M. Hossain, W. A. Davis, H. T. Russell, and R. L. Carter, “A 1-V Quasi Rail-to-Rail Operational Amplifier with a Single Input Differential Pair,” IEEE Region Five Technical Conf., pp. 93-96, Apr. 2007

[9] Linear Technology, Application Note 143, pp. 1-8. [10] C.-F. Liang, S.-H. Chen, and S.-I. Liu, “A digital

calibration technique for charge pumps in phase-locked systems,”IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 390-398, Feb. 2008.

[11] M. M. Elsayed, et al., "A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS," IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2104-2117, Jul. 2013.

[12] J. Shin, J. Kim, S. Kim, and H. Shin, “A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-mm CMOS,” J. of Semiconductor Technology and Science, vol. 7, no 4, pp. 267-273, Dec. 2007.

Jihoon Sohn was born in Korea in 1984. He received B.S. from Kwang- woon University in 2010, and is currently working toward Ph.D. at the same university. His research is focused on the PLL frequency synthesizers and analog circuits in

CMOS.

Table 1. Performance summary and comparison

This work [10] [11] [12] Output Frequency

(GHz) 1.1-1.6 5.1-5.3 3.6 0.9-1.8, 2.9-3.7

Reference Frequency

(MHz) 26 10 6 19.2

Reference Spur (dBc) -81.1 -68.5 -74 -70

Power Consumption

(mW) 6.0 19.8 1.5 41.4

Technology 65 nm CMOS

180 nm CMOS

90 nm CMOS

180 nm CMOS

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016 879

Hyunchol Shin (S'93–M'01–SM'10) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1991, 1993, and 1998, respectively. During his Ph.D.,

he held an internship as a Doktorand at the Daimler-Benz Research Center, Ulm, Germany. Upon completion of the Ph.D., he worked at several research institutions and companies, such as Samsung Electronics, Korea, University of California at Los Angeles, CA., USA, and Qualcomm, San Diego, CA, USA, where he had been involved with RF/analog circuit design for wireless communications. Since 2003, he has been with Kwangwoon University, Seoul, Korea, where he is currently a Professor with the Department of Electronics Convergence Engineering. From 2010 to 2011, he took his sabbatical leave with Qualcomm, San Diego, CA, USA. He has coauthored over 70 journal and conference papers. He holds over 30 patents in the field of RF/analog circuit design. His research interests focus on CMOS RF/analog/microwave circuits and phase-locked loop (PLL) frequency synthesizers. Prof. Shin has served on Technical Program Committees of several IEEE conferences such as the International Solid-State Circuits Conference (ISSCC), the IEEE VLSI Circuit Symposium (VLSI), the Asian Solid-State Circuit Conference (A-SSCC), the Midwest Symposium on Circuits and Systems (MWCAS), and the International System-on-Chip Conference (ISOCC).