MIXED SIGNAL LETTER

A buck converter with adaptive on-time PFM controland adjustable output voltage

Hyunseok Nam • Youngkook Ahn • Jeongjin Roh

Received: 24 August 2010 / Revised: 5 September 2011 / Accepted: 11 October 2011 / Published online: 21 October 2011

� Springer Science+Business Media, LLC 2011

Abstract This letter proposes a new adaptive on-time

pulse-frequency modulation (PFM) circuit that operates at

a wide range of supply voltage levels and that can generate

various output voltage levels compared to conventional

circuits. The circuit’s peak inductor current is well-con-

trolled; the magnitude of the output ripple voltage is con-

stant, even when the supply and output voltage levels are

significantly different. Since the ripple voltage is a noise

component, constant ripple voltage is important for pre-

dictable noise of a power management system.

Keywords Buck converter � Adaptive on-time (AOT) �Constant on-time (COT) � Pulse-frequency modulation

(PFM) � Inductor peak current

1 Introduction

With an ever-increasing number of mobile devices in

common use, the efficient use of power is an important

issue [1–7]. In particular, many techniques have been

studied to improve power efficiency when such devices are

in stand-by mode, since they operate in this mode most of

the time [8].

A simple way to increase power efficiency in stand-by

mode is the constant on-time (i.e., fixed on-time) PFM

method. This method does not require a sensing circuit, but

the inductor peak current changes significantly in response

to both the supply and output voltages [9]. This peak cur-

rent variation affects the accuracy and ripple magnitude of

the output voltage. Since the ripple voltage is a noise

component of the power supply, this variation makes fil-

tering noise in a power-management system design diffi-

cult. Therefore, an adaptive on-time PFM control

technique, rather than a constant one, is proposed. This

technique produces little output ripple variation and

improves power efficiency.

Table 1 shows characteristics in relation to on-time

control methods. Constant on-time (COT) can be imple-

mented using a comparator and a simple on-time circuit to

reduce the area and design complexity. However, due to

the constant on-time, inductor peak-to-peak and output

voltage ripples change significantly in relation to changes

in supply voltage, output voltage, and load current.

Adaptive on-time can be largely divided into fixed fre-

quency and variable frequency methods. The AOT using

the fixed frequency method can minimize voltage ripples

against changes in supply voltage, output voltage, and load

current. In addition, this method shows electromagnetic

interference (EMI) problems can be minimized compared

to other methods. However, the size of the entire system

increases due to complicated sensing and control circuits.

On the other hand, the AOT using the variable fre-

quency method can reduce the system area as well as the

complexity through the use of small-sized circuits. In

addition, the magnitude of the output voltage ripples can be

reduced against changes in supply voltage and output

voltage [16].

However, the circuit in [16] was used under the

assumption that the output voltage was fixed, which sig-

nificantly limits the circuit’s applications. This letter pro-

poses a new type of adaptive on-time PFM circuit that does

not need a complex current-sensing circuit and that can

maintain a constant peak inductor current despite any

variation in either supply or output voltage.

H. Nam � Y. Ahn � J. Roh (&)

Department of Electrical Engineering, Hanyang University,

Ansan 426-791, Korea

e-mail: jroh@hanyang.ac.kr

123

Analog Integr Circ Sig Process (2012) 71:327–332

DOI 10.1007/s10470-011-9802-7

2 Controller design

Figure 1 shows a block diagram of the proposed PFM con-

troller. If the output voltage (VO) is lower than the reference

voltage (Vref1), the comparator’s output toggles to high, and

this high signal turns the Qb of SR latch1 to low, which turns

on the PMOS power transistor. Then, after an adaptively

controlled delay time, the adaptive on-time circuit changes

the RESET signal to high, which turns the Qb of SR latch1 to

high and turns off the PMOS power transistor. At the same

time, the Q of SR latch2 becomes high, which turns on the

NMOS power transistor. The reverse current, which

decreases overall efficiency, might occur if the NMOS power

transistor stays on for too long. In order to prevent this, a

reverse-current comparator (Comp2) is included in the

controller [8, 16, 17]. Figure 2 presents the results of the

HSPICE simulation of the control signals in Fig. 1.

Figure 3 shows the proposed adaptive on-time circuit.

The proposed circuit can adaptively control the on-time for

various output and supply voltage levels, and, therefore,

can generate different output voltages with very little

change in the magnitude of the output voltage ripple. In

order to generate a current (Iadp) that is proportional to the

difference between the supply and output voltage, we

designed a circuit that consists of MN1, R1, CC, and an

amplifier. The current is copied using a current mirror that

consists of MN2, MP1, and MP2. This current can be

expressed as follows:

Iadp ¼VDD � VO

R1

ð1Þ

which is converted to a saw-tooth waveform through C1:

DVrampðtÞ ¼1

C1

ZIadp � dt ð2Þ

Therefore, when the pdrive in Fig. 3 becomes low, the

PMOS power transistor in Fig. 1 remains on until the

Vramp is equal to Vref2. This on-time is defined as TON, and

is proportional to changes in both the supply and the output

voltage. This can be expressed using (1) and (2) as follows:

DTON ¼Vref2R1C1

VDD � VO

ð3Þ

As shown in (3), TON changes in response to the supply

voltage (VDD) and output voltage (VO). Using TON, we can

adjust the peak inductor current:

DIL ¼VDD � VO

2LTON ð4Þ

When the supply voltage is high, the inductor current’s

slope increases and TON decreases; the inductor’s peak

current is constant. Similar operations occur for different

supply or output voltages, or both, by adaptively increasing

Table 1 Comparison of the control methods

Constant on-time Adaptive on-time

[10–12] Fixed frequency

method [13–15]

Variable frequency method

Fixed output voltage [16] Adjustable output voltage

(proposed scheme)

Area Small area due to simplicity Large area due to the

sensing circuit

Small area due to the simple sensing circuit

Complexity Easy implementation Complexity increases

due to the complex

sensing circuit

Reduced complexity by using simple sensing circuit

Output

ripple

voltage

Large ripple voltage due to changes

in supply voltage, output voltage,

and load current

Small ripple voltage Ripple voltage is

minimized only against

changes in supply voltage

Ripple voltage is minimized against

changes in both supply voltage

and output voltage

EMI EMI problem is serious as fSchanges are severe

EMI problem is

minimized due to

constant fS

EMI problem is slightly

relieved compared to

COT structures

EMI problem is relieved by small

changes in fS and small ripple

voltage

Fig. 1 Block diagram of the proposed PFM controller

328 Analog Integr Circ Sig Process (2012) 71:327–332

123

or decreasing TON to maintain a constant peak current

without requiring a current-sensing circuit.

Figure 4 shows the voltage generator that regulates the

output voltage level. In conventional buck or boost dc–dc

converters, the output voltage is regulated by two external

resistors that compare the output voltage with the reference

voltage. In this study, we adjusted the reference voltage

using only one external resistor in order to minimize the

number of external passive components. The Vref1 is:

Vref1 ¼ Vref

R1

R2 þ Roff

þ 1

� �ð5Þ

3 Simulation results

The operation of the proposed circuit was verified by

HSPICE simulations. Table 2 summarizes the design

parameters and simulation results. The waveforms in Fig. 5

show the magnitude of the ripple voltage of the buck

converter output and the inductor current peaks when the

supply voltage is 3.6 and 2.5 V, respectively. The wave-

forms in Fig. 6 show the magnitude of the ripple voltage

and the inductor current peaks were well-controlled, even

when the output voltage levels were as different as 1.8 and

0.8 V, respectively. Figures 7, 8, 9, and 10 show the results

of a comparison between the proposed PFM circuit and the

constant on-time PFM circuit. Figures 7 and 8 show the

ripple variation of the output voltage and peak inductor

current, according to the supply voltage levels, when the

output voltage is set to 1 V. Figures 9 and 10 show the

Fig. 2 Waveforms of control signals in the proposed PFM

Fig. 3 Proposed adaptive on-time circuit

Fig. 4 Voltage generator for output voltage of buck converter

Table 2 Performance summary

Technology 0.35 lm

Input voltage 2–3.6 V

Output voltage 0.8–1.8 V

Inductor/DCR 2 lH/200 mX

Capacitor/ESR 20 lF/50 mX

Quiescent current 20–30 lA

Load current 0.1–150 mA

Efficiency 50–89% @ VO = 1.8 V

Analog Integr Circ Sig Process (2012) 71:327–332 329

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ripple variation of the output voltage and peak inductor

current, according to the output voltage levels, when the

supply voltage is set to 3.6 V. As expected, the proposed

circuit shows a significant improvement. Figure 11 shows

the efficiency of the proposed buck converter.

Fig. 5 HSPICE simulation: VO = 1 V, L = 2 lH, C = 20 lF, load

current = 100mA

Fig. 6 HSPICE simulation: VDD = 2.5 V, L = 2 lH, C = 20 lF, load

current = 100 mA

Fig. 7 Output ripple variation according to changing supply voltage

levels (VO = 1 V, L = 2 lH, C = 20 lF, load current = 100 mA)

Fig. 8 Inductor current peak-to-peak according to changing supply

voltage levels (VO = 1 V, L = 2 lH, C = 20 lF, load current =

100 mA)

Fig. 9 Output ripple variation according to changing output voltage

levels (VDD = 3.6 V, L = 2 lH, C = 20 lF, load current = 100 mA)

330 Analog Integr Circ Sig Process (2012) 71:327–332

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4 Conclusion

We have proposed a new adaptive on-time PFM circuit and

verified it using HSPICE simulations. The proposed circuit

has a constant peak inductor current and has little ripple

voltage variation in the output voltage, even when there are

significant changes in the supply and output voltage levels.

The proposed circuit was designed with standard 0.18-lm

CMOS process parameters, and its performance was

demonstrated by comparative simulations with a conven-

tional circuit.

Acknowledgments This research was supported in part by the

Ministry of Knowledge Economy, Korea, under the University ITRC

support program supervised by the National IT Industry Promotion

Agency (NIPA-2011-C1090-1101-0003), and supported in part by

Basic Science Research Program through the National Research

Foundation of Korea(NRF) funded by the Ministry of Education,

Science and Technology (2011-0026001).

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Fig. 10 Inductor current peak-to-peak according to changing output

voltage levels (VDD = 3.6 V, L = 2 lH, C = 20 lF, load current =

100 mA)

Fig. 11 Power conversion efficiency (L = 2 lH, C = 20 lF)

Analog Integr Circ Sig Process (2012) 71:327–332 331

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Hyunseok Nam received the

B.S. degree in electronic and

electrical engineering science,

Hallym University, Chuncheon,

Korea, in 2005. He received the

M.S degrees in electrical engi-

neering and computer science,

Hanyang University, Ansan,

Korea, in 2007, where is cur-

rently pursuing the Ph.D.

degree. His research interests

include power management cir-

cuits and mixed-signal inte-

grated circuits.

Youngkook Ahn received the

B.S. degree in electronic and

electrical engineering science,

Kyeonsang University, Jinjoo,

Korea, in 2006. He received the

M.S degrees in electrical engi-

neering and computer science,

Hanyang University, Ansan,

Korea, in 2009. He is now

working toward the Ph.D.

degree in the same department.

His research interests include

power management circuits and

mixed-signal integrated circuits.

Jeongjin Roh received the B.S

degree in electrical engineering

from the Hanyang University,

Seoul, Korea, in 1990, the M.S.

degree in electrical engineering

from the Pennsylvania State

University in 1998, and the

Ph.D. degree in computer engi-

neering from the University of

Texas at Austin in 2001. From

1990 to 1996, he was with the

Samsung Electronics, Kiheung,

Korea, as a senior circuit

designer for several mixed-sig-

nal products. From 2000 to

2001, he was with the Intel Corporation, Austin, Texas, as a senior

analog designer for delta-sigma data converters. In 2001, he joined

the faculty of the Hanyang University, Ansan, Korea. His research

interests include oversampled delta-sigma converters and power

management circuits.

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