JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, 2018 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2018.18.1.036 ISSN(Online) 2233-4866

Manuscript received Nov. 11, 2016; accepted Nov. 13, 2017 Electronic Engineering Department, Kyung Hee University, Yongin-si, Gyeonggi-do 17104, Korea E-mail : sangwyoon@khu.ac.kr

A Broadband On-chip Power Divider up to W-band with Three-dimensional Three-coupled Lines

Trung-Sinh Dang, Nhut-Tan Doan, Byung-Sung Kim, Nam-Yoon Kim,

Chang-Woo Kim, and Sang-Woong Yoon

Abstract—A state-of-the-art broadband on-chip power divider in millimeter-wave up to 103 GHz is presented. The power divider employs novel three-dimensional (3-D) three-coupled lines to achieve the desired mode impedances for an extremely wideband characteristic. The power divider was implemented in TSMC 180 nm RF CMOS IC technology with six metal layers. Measurements show the absolute bandwidth from 11 to 103 GHz with matching conditions of all of the ports and isolation between two outputs of less than -10 dB. The fractional bandwidth is 161.4%. The insertion loss is between 1.2 and 7.9 dB across the overall bandwidth. The core size of the power divider is 0.18 mm × 0.68 mm. Index Terms—Broadband, CMOS, millimeter-wave, power divider, three-dimensional three-coupled lines, wideband

I. INTRODUCTION

Due to increasing demand for high data rates, wireless communication systems using extremely wide bandwidth at millimeter-wave frequencies are increasing in popularity, but they also require broadband millimeter-wave radio. Power dividers are essential components, so considerable effort has been invested in designing broadband power dividers in millimeter-wave. The millimeter-wave on-chip power divider using lumped

elements of inductors and capacitors had a compact size, but a very narrow bandwidth [1]. The simplest way to obtain a wide bandwidth is to cascade multiple sections. A multi-sectional Wilkinson type power divider is the most popular wideband configuration. However, the size becomes very large because of the multiple sections, so a folded configuration was proposed to reduce the overall size [2]. The configuration of three parallel-coupled lines was commonly used, not for a wide bandwidth, but for multi-way [3]. The wideband characteristics of three parallel-coupled lines with a short-circuited shunt stub at the input were reported [4]. The wideband performance was demonstrated in printed-circuit board (PCB) technology for ultra-wide band (UWB) application [4], and CMOS IC technology was incorporated to obtain a wider bandwidth at millimeter-wave frequencies [5].

Millimeter-wave radios have been traditionally designed in GaAs IC technology. However, as CMOS devices have recently become faster, CMOS IC technology has become a good candidate for design. On-chip power dividers for millimeter-wave applications have been published using GaAs IC technology [2, 3] as well as CMOS IC technology [1, 5]. Most on-chip power dividers using transmission lines have adopted a microstrip configuration [2, 3, 5]. In GaAs IC technology, only two metal layers are commonly provided, so there has been no alternative but to use a 2-D planar structure like a microstrip with one metal layer for the signal line, and the other for ground. On the other hand, CMOS IC technology provides more than six metal layers, which enables the employment of a 3-D structure. Even if the power divider in [5] showed a broadband characteristic with three parallel-coupled lines, the bandwidth

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, 2018 37

performance was limited by the inherent nature of the 2-D planar structure. In this work, the 3-D three-coupled line structure using CMOS IC technology with six metal layers is presented to overcome the limitation.

II. ANALYSIS AND DESIGN

Fig. 1(a) represents the simplified schematic of the broadband power divider consisting of three-coupled lines, a shunt stub, and a resistor. Fig. 1(b) and (c) show the cross-sections of the 2-D and 3-D configurations of the three-coupled lines, respectively. In [5], the 2-D planar three-coupled lines were designed by the even-even-mode (EE-mode) and odd-odd-mode (OO-mode) impedances, Z0ee and Z0oo, which were based on the theory of three-coupled lines in [6]. The bandwidth becomes wider as Z0oo gets smaller. Z0oo of the 2-D planar three-coupled lines in Fig. 1(b) is mainly decided by the coupling capacitances (Cab, Cbc). The minimum achievable Z0oo was 25 Ω in [5].

In this work, the broadband design methodology based on the 2-D planar configuration is extended to the 3-D structure. Three-coupled lines using a novel 3-D structure in CMOS IC technology with six metal layers are proposed to increase the bandwidth, as shown in Fig. 1(c).

To decrease Z0oo, the side lines (TLa and TLc) are designed to surround the center line (TLb), which increases C′ab and C′bc. To find Z0ee and Z0oo, the following capacitances for each conductor in three modes should be found first [6]:

EE – mode: a c 11 12 13C Cee ee c c cm= = + +

b 22 12

2C ee c cm

= + (1)

OO – mode: a c 11 12 13

2C Coo oo c c cm

= = - +

b 22 12C oo c cm= - (2) OE – mode: a c 11 13C Coe oe c c= = - (3)

where the Cimm values (conductor: i = a, b, c; mode: mm = ee, oo, oe) are the static mode capacitances, and the cij values (i, j = 1, 2, 3) are the coefficients of the matrix [7]:

a 11 12 13 a

b 21 22 23 b

c 31 32 33 c

Q VQ VQ V

c c cc c cc c c

é ù é ù é ùê ú ê ú ê ú=ê ú ê ú ê úê ú ê ú ê úë û ë û ë û

(4)

where the Qi values are the charges per unit length, and Vi values are the potentials with respect to ground of each conductor (conductor: i = a, b, c). Assuming equal mode impedances for the center and side conductors, the parameter μ is determined as

( )2 211 22 13 11 22 13 12

12

8 .

2

c c c c c c cc

m- + - - - + +

= (5)

Because of the complicated 3-D structure, a numerical

method was employed to find all of the Cimm values. The numerical calculation was performed through MATLAB programming. Transverse electromagnetic (TEM) wave propagation along the three-coupled lines and quasi-static conditions were assumed in order to simplify the problem. The region around the conductors was divided into rectangular meshes with grid points or nodes. The Poisson equation was solved with the finite difference method to determine the voltage distribution at all mesh points. The potential at each node was calculated using a five-point formula, which gives an error of order h (the distance between two successive nodes) [6]. The execution of the MATLAB code was continued until an

(a) (b)

(c)

Fig. 1. (a) Simplified schematic of the power divider using three coupled lines, and cross-sectional views of (b) the 2-D planar, (c) the proposed 3-D configuration from A to B showing internal capacitances among conductors and ground.

38 TRUNG-SINH DANG et al : A BROADBAND ON-CHIP POWER DIVIDER UP TO W-BAND WITH THREE-DIMENSIONAL …

accuracy of 10-4 was achieved. Gauss′ law was utilized to calculate the charge per unit length associated with each conductor. Finally, all of the cij values were obtained by the ratio of the charges and excitation voltages. The calculation was executed twice, with and without dielectric material. Then, the mode capacitances, Cmm,die and Cmm,air (mm = ee, oo, oe), were found. The mode impedances, Z0mm, were obtained with the following equation [6]:

0mm

mm,air mm,die

1C C

Zv

= (6)

where v is the velocity in the free space. The three mode impedances (Z0ee, Z0oo, Z0oe) of the proposed structure were computed using the MATLAB code. Fig. 2 shows the effect of W′c and S′ on Z0ee and Z0oo, keeping μ in the proper range for broadband matching and isolation. Based on the mode impedance calculation, the design parameters such as W′c, W′s, W′v, and S′ in Fig. 1(c) were found, and were optimized to maximize the bandwidth with an EM simulator. The discrepancy between the analysis and the EM simulation on the final design parameters came from the assumptions made in the analysis. Z0oo, Z0ee, Z0s, and R were designed to be 15 Ω, 141 Ω, 100 Ω, and 60 Ω, respectively.

III. IMPLEMENTATION AND MEASUREMENT

RESULTS

The proposed power divider in the 3-D configuration was simulated with the EMX (Electro Magnetic

eXtractor) full-wave EM simulator and was implemented in TSMC 180 nm RF CMOS IC technology with six metal layers. The 4th, 5th, and 6th metal layers and vias were used to implement the 3-D three-coupled lines. The 1st metal layer was used as the ground. The thickness of the 6th (top) metal layer was 2.34 um, and the thicknesses of the 4th and 5th metal layers were 0.53 um. The 5th metal layer was only used for the center line, while all three metal layers were used for the side lines to surround the center line. Therefore, compared with the 2-D structure, the proposed 3-D structure had more skin effect, but less radiation effect.

The design parameters, W′c, W′s, W′v, and S′ in Fig. 1(c) were designed to be 4 um, 2.0 um, 1.4 um, and 0.5 um, respectively. The length of each of the three coupled lines was 680 um. The width and length of the short-circuited shunt stub were 1.5 um and 520 um, respectively. Fig. 3 shows a photograph of the fabricated power divider. The occupied area of the power divider is 0.18 mm × 0.68 mm, excluding all of the pads and access lines that were used for the measurements.

The performance of the power divider was verified using the Anritsu ME7838A vector network analyzer (VNA) measuring up to 110 GHz. The VNA was calibrated with the short-open-load-thru (SOLT) method. Two RF ground-signal-ground (GSG) probes (I110-A-GSG-150) were used for the on-wafer measurements. All the ports of the fabricated chip were terminated with on-chip 50 Ω resistors. When two ports were measured, the on-chip resistors were cut by the laser cutting machine (Quicklaze Trilite Laser), so that only the third port was matched with the on-chip 50 Ω resistor.

The measurement results are shown in Fig. 4. All of the parasitic components from the probing pads and access lines were de-embedded by the open and short test

Fig. 2. Effect of W′c and S′ on Z0ee and Z0oo (W′s = W′c / 2, W′v= W′s – 0.5 μm).

Fig. 3. Photograph of the fabricated on-chip power divider.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, 2018 39

structures. The measurements show that the low and high ends of the bandwidth are decided by S22 and S11, respectively. The matching at all three ports and the isolation between the two outputs are less than -10 dB from 11 to 103 GHz. The absolute bandwidth is 92 GHz, and the fractional bandwidth is 161.4%. The insertion loss is between 1.2 and 7 dB across the bandwidth. Measured imbalance of magnitude and phase are very small within 0.2 dB and 2o, respectively.

Table 1 compares the performance of the proposed power divider with other designs that have been published in the literature. This proposed power divider has the largest fractional bandwidth and smallest size compared to all of the power dividers in the table. The bandwidth is 485% larger than the lumped element power divider in [1]. The size is 73% smaller than the folded Wilkinson type power divider in [2]. When compared with the power divider that was implemented using 2-D three parallel-coupled lines in [5], the proposed 3-D power divider provided a fractional bandwidth that was 19.7% wider. Furthermore, even if

the center line suffered from the skin effect, the 3-D configuration suppressed the radiation effect, so that the insertion loss decreased by maximum 3.5 dB.

IV. CONCLUSIONS

An on-chip power divider using three coupled lines in a 3-D configuration was presented. The multiple metal layers in CMOS IC technology enabled the implementation of the proposed configuration. A wider bandwidth and smaller loss were obtained than with the 2-D planar structure. To the best of our knowledge, this work presents a state-of-the-art on-chip power divider with the most broadband bandwidth in millimeter-wave.

ACKNOWLEDGMENTS

The EMX simulator was supported by Sysontek Inc. The EDA tool was supported by the IC Design Education Center (IDEC), Korea. This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2017R1A2B4002134), and by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2016-R2718-16-0012) supervised by the IITP (National IT Industry Promotion Agency).

REFERENCES

[1] J. G. Kim et al., “Miniature four-way and two way 24 GHz Wilkinson power dividers in 0.13um CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 9, pp. 658–660, Sep. 2007.

[2] Y. Sun et al., “Broadband folded Wilkinson power combiner/splitter,” IEEE Microwave Wireless

Fig. 4. Measurement (solid line) and simulation (dotted line) results of the proposed power divider.

Table 1. Comparison of On-chip Power Dividers

Bandwidth Ref. IC

Tech Size

(mm2)

Matching condition

(dB)

Frequency range (GHz)

Absolute (GHz)

Fractional (%)

Insertion loss in Bandwidth

(dB)

[1] CMOS 0.109 < -9.8 20 – 28 8 33.3 1.4 – 2.5 [2] GaAs 0.45 < -12 20 – 50 40 133.3 1.3 – 2.2 [3] GaAs 1.12 < -10 22 – 36 14 48.3 0.8 – 1.4 [5] CMOS 0.146 < -10 14 – 82 68 141.7 2.8 – 10.5

This work CMOS 0.122 < -10 11 - 103 92 161.4 1.2 – 7.9

40 TRUNG-SINH DANG et al : A BROADBAND ON-CHIP POWER DIVIDER UP TO W-BAND WITH THREE-DIMENSIONAL …

Compon. Lett., vol. 14, no. 6, pp. 295-297, Jun. 2004.

[3] Y. Lai et al., “A compact Ka-band planar three-way power divider,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 12, pp. 840 -842, Dec. 2007.

[4] T.-S. Dang et al., “Ultra-wide band power divider using three parallel-coupled lines and one shunt stub,” IET Electronics Letters, vol. 50, no. 2, pp. 95–96, Jan. 2014.

[5] T.-S. Dang et al., “Power divider with bandwidth from 14 to 82 GHz in CMOS IC technology,” IET Electronics Letters, vol. 50, no. 14, pp. 1007–1009, July 2014.

[6] D. Pavlidis et al., “The design and performance of three-line microstrip coupler,” IEEE Trans. Microw. Theory Tech., vol. 24, no. 10, pp. 631-640, Oct. 1976.

[7] S. Yamamoto et al., “Coupled strip transmission line with three center conductors,” IEEE Trans. Microw. Theory Tech., vol. 14, no. 10, pp. 446-461, Oct. 1966.

Trung-Sinh Dang received the B.S. degree in Electronics Telecommuni- cation Engineering from the Ho Chi Minh City University of Technology, Vietnam, in 2006, and M.S. in Electronics and Radio Engineering from Kyung Hee University, South

Korea, in 2010. Now he is a Ph.D. candidate in High Frequency Circuits and Systems lab, Dept. of Electronics and Radio Engineering, Kyung Hee University. His research interests include analog/RF IC, power amplifier design, and microwave component/ module design.

Nhut-Tan Doan received the B.S. degree in Electronics Tele-communi- cation Engineering from the Ho Chi Minh City University of Technology, Vietnam, in 2014, and Addendum of Bachelor of Engineering from Superior National School of Tele-

communication in Bretagne, France, in 2014. He received the M.S. in Electronics and Radio Engineering

from Kyung Hee University, South Korea, in 2017. Now he is a Ph.D. candidate in High Frequency Circuits and Systems lab, Dept. of Electronics Engineering, Kyung Hee University. His research interests include analog/RF IC design and microwave module design with advanced integration technologies.

Byung-Sung Kim (S’96–A’98–M’03) received the B.S., M.S., and Ph.D. degrees in electronic engi- neering from Seoul National University, Seoul, Korea, in 1989, 1991, and 1997, respectively. In 1997, he joined the College of Information

and Communication Engineering, Sungkyunkwan University, Suwon, Gyeonggi-Do, Korea, where he is currently a Professor. In 2013, he was a Visiting Researcher with the University of California at Santa Barbara. His research interests include high-frequency device modeling and RF/millimeter-wave CMOS integrated circuit design.

Nam-Yoon Kim received his B.S. degree in electronic engineering from chungwoon University, Korea, in 2001, and the M.S. and Ph.D. degree in electronics and radio engineering from Kyung Hee University, Korea, in 2005 and 2012. From 2004 to

2014, he was with LG innotek and Samsung Advanced Institute of Technology (SAIT), Suwon, Rep. of Korea, where he served as a senior RFID, USN (Ubiquitous Sensor Network), loosely coupled wireless power transfer, communication technology in the wireless charging system and energy harvesting research. He was working on the IWPRC (Intelligent Wireless Power Research Center) for wireless charging as a member of IWPRC Group in 2015. Since 2017, he has been a professor at Daeduk University, Daejon, Rep. of Korea. His research interests include RF characterization, Non-contact measurement of heart and energy-IT converging systems.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, 2018 41

Chang-Woo Kim received the B.S. and M.S. degrees in electronic engineering from the Hanyang University, Seoul, in 1984 and 1986, respectively, and the Ph.D. degree in electronic engineering from the Shizuoka University, Hamamatsu,

Japan, in 1992. From 1992 to 1996, he was with the Microelectronics Laboratories, NEC Corporation, Tsukuba, Japan, where he worked on the high-frequency and high-power hetero-junction devices and ICs used for mobile and satellite communication applications. Since 1996, he has been with the Department of Electronics and Radio Engineering, Kyung Hee University. His research interests include microwave/mm-wave solid-state device modeling, MCIC and MMIC design, and RF characterization. Prof. Kim is a member of IEEK, KIEE, KIEES, IEEE, and IEICE.

Sang-Woong Yoon received the B.S. degree from the Yonsei University, Seoul, Korea, in Aug. 1998, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea in Feb. 2001, and the

Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, in Dec. 2004. He was a senior design engineer in RF Micro Devices, Billerica, MA, from Apr. 2005 to May 2006 and in Marvell Semiconductor Inc., Santa Clara, CA, from June 2006 to July 2007. He has authored or coauthored over 47 papers in referred journals and conference proceedings. From Sep. 2007, He joined Kyung Hee University in South Korea as a faculty member. His research interests include solid-state device characteri- zation, analog/RF IC design, power amplifier design, microwave component/module design, and RF Front-End-Module design in advanced integration technologies.