a breadboard for real-time image processing on board gaia - mignot_shan... · gaia. 4 phase charge...

A breadboard for real-time image processing on board Gaia

Shan MignotGilles Fasola & Philippe Laporte

Outline

I. Gaiauser requirements

II. Image analysisalgorithmic framework

III. VHDL pipelinethe logic behind the scenes

IV. The demonstrator: a case studysome solutions to some problems

V. Conclusion

MAPLD 2008 – September 18th 2008 – Shan Mignot, Gilles Fasola, Philippe Laporte 2/33

I. Gaia

Observing principle

Global astrometry survey2 telescopes with combined focal planes

spin & precession motions

→ on-the-fly data acquisition→ attitude & orbit control

106 CCDs & L2 orbit

→ selective data acquisition→ autonomous data management

survey: no star catalogueselection biases

→ on-board object detection

Gai

a


PayloadG

aia


Time-delay integration (TDI) G

aia

4 phase charge transfer

column per column read-out(every 0.9828 ms)

pixel packets sent toVideo Processing Unit(SpaceWire interface)

4.4s


double stars density

Some cases of interestG

aia

prompt particle events

extra-galactic complex skies


II. Image analysis

Functional architectureIm

age

anal

ysis

raw data thresholdedbackground map

segmentation connectedcomponents

measurements

pixel level

object level


Pre-calibrationIm

age

anal

ysis

Needscontrol the selection functionavoid false detectionsgraceful degradation of performance in time

Methodlinear transform (generalises flat-field & dark)replacement mechanism fixed-point arithmetics (VIMOS CCD)


BackgroundIm

age

anal

ysis

Needscontrol the selection function: estimate the total noisecontrol false detections

Functionallatency & resolution trade-offrobust to stellar contentsystematic calculation

Methodregional estimates: hyperpixelshistograms: 4 ADU bins interpolated mode: precise & robust2D bilinear interpolationfixed-point arithmetics


Background II (1) Im

age

anal

ysis

hyperpixel

mode values


Background II (2) Im

age

anal

ysis

mode values

interpolation


Background II (3)Im

age

anal

ysis


Pixel selectionIm

age

anal

ysis

Needssave resources→ discard background pixels

control false detections→ robustness to noise→ filter faint stars

Methodsignal to noise thresholdsignal: subtract estimated backgroundfixed-point arithmetics


III. VHDL pipeline

DesignV

HD

L pi

pelin

e

Pipelinepre-calibration → buffer_pix → background → pixel selectiondata driven & exploiting the available latencytarget slow operation (timing constraints, power consumption, resource sharing)

ClocksDCLK: data clock → pipeline control (~1 MHz)SCLK: SRAM clock → sequential optimisations (~32 MHz)CLK: main clock → SRAM interface (125 MHz)

Design for testinterchangeable processing core & debug coreconditional instantiation → modular for unit validation

→ increasing complexityMAPLD 2008 – September 18th 2008 – Shan Mignot, Gilles Fasola, Philippe Laporte 17/33

Pixel selection (1)V

HD

L pi

pelin

e

Taskson demand background interpolation → optimise storagesignal to noise threshold → fixed-point arithmeticsoutput stream of selected pixels → ~90% data reduction

prior to software

Pipeline DCLK

mode addresses (x4)AL & AC coordinates

interpolation coefficientsread modes (x4)


Pixel selection (2)V

HD

L pi

pelin

e

Taskson demand background interpolation → optimise storagesignal to noise threshold → fixed-point arithmeticsoutput stream of selected pixels → ~90% data reduction

prior to software

Pipeline DCLK

mode addresses (x4)AL & AC coordinates

interpolation coefficientsread modes (x4)

contributions (x4)

sum

signal

signal2

threshold

testoutput


Synthesis (1)V

HD

L pi

pelin

e

VHDLESA standard (except for testing: verification & validation)

Simulationvalidated pre-synthesis & post-synthesis

Synthesis14722 cells > ProASIC3E 600 → ProASIC3E 1500 (100% margin)slow routingtarget: RTAX-S 1000 (ITAR)


Synthesis (2)V

HD

L pi

pelin

e





Synthesis (3)V

HD

L pi

pelin

e





Synthesis (4)V

HD

L pi

pelin

e



Synthesis14722 cells > ProASIC3E 600 → ProASIC3E 1500

(100% margin)slow routingtarget: RTAX-S 1000 (ITAR)


IV. The demonstrator: a case study

ArchitectureTh

e de

mon

stra

tor:

a ca

se s

tudy

Interfacesinput: CCDs via serial SpaceWire link

→ video buffer: PC with IO board (handshake)output → hard/soft interface: dual-port asynchronous SRAMstorage → 2 asynchronous SRAMs

SimplifiedFPGA board developments

→ no real-time processor

design simplifications→ no connected component labelling→ no management of software interface

inspectable design→ conditional module instantiation→ output data stored in PC→ free pins


PlatformPart

Actel: ProASIC3E instead of RTAX-S→ reprogrammable: flash-based instead of anti-fuse→ slower (interconnections)→ less dense

Development KitProASIC3E 600

SRAMsISSI ISI61LV51216staticasynchronous16-bit data19-bit address

PC interfacehandshake16-bit data


The

dem

onst

rato

r: a

case

stu

dy

IOs: Experimental observationTh

e de

mon

stra

tor:

a ca

se s

tudy

Logicprotocol timing failures: need to adjust timing to IO boardidle cycles: disrupted logic

Analogicnoiseglitchesovershootsground noise

→ Functional for 60% of the maximum load (16 SSOs)


Signal integrity problemsTh

e de

mon

stra

tor:

a ca

se s

tudy

Fast transitions (~1 ns)current rushharmonics

Impedance issuesinadequate line transmission improper routing (common impedances, long paths)

Power supply designpoor ground referenceineffective decouplingmultiple power supplies


SolutionsD

emon

stra

tor:

a ca

se s

tudy

IO characteristics & routingdriver's strength reduceddriver's capacitance increasedschmitt triggers added on inputsinsertion of strong quiet outputs between sensitive signalsdelay buffers to avoid SSO

Boards modifiedimpedance → line terminations when possible

→ diversion of the current pathspower supply → passive solutions preferred

(terminations & level adaptation)→ kept one power supply only→ improvement of ground routing→ decoupling capacitors→ use of ferrite beads

→ Functional at the maximum load (occasional perturbations)


V. Conclusion

ConclusionC

oncl

usio

n

Sciencedesigned in collaboration with scientistssatisfactory: completeness, false detection rate, special objects (binary stars, textured backgrounds etc.)

Feasibility meets user requirements & system-level constraints (data flow)representative demonstrator (technology & logic): portable to RTAXmultiple clock synchronous design: data driven timing, relaxed constraints, power consumptiontest platform for testing & validation (& improvement !)

Lessons learntlogic design: resource sharing, scheduling, fixed-point arithmetics etc.signal integrity is a key issue (even for slow designs due to transitions)need for careful design of the ground reference !


PerspectivesC

oncl

usio

n

Towards a 2nd demonstratorimprovements

multi-layer PCBcompact designpower supply design impedances

extensionsinterface to software: dual-port asynchronous SRAMEEPROM & initialisationreal-time software engine (PPC750FX)

Testing & validationECSS: verification (correctness) & validation (intended use)compare to industrial system (Astrium SAS)



More details, discussion etc.

Poster !

a breadboard for real-time image processing on board gaia - mignot_shan... · gaia. 4 phase charge...

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