A 90nm RF CMOS technologysupported by device modelling

and circuit demonstrators

J. Ramos, A. Mercha, W. Jeamsaksiri, D. Linten1, S. Jenei, S. Thijs, A.J. Scholten2, P. Wambacq1,

I. Debusschere, S. Decoutere

IMEC Leuven, Belgium

1 Also with the Vrije Universiteit Brussel, Belgium

2Philips Research Eindhoven, Netherlands

Outline of the presentation

Introduction

Technology overview

Active device description and modelling

Passive devices description and modelling

Circuit demonstrators results

Conclusions

IntroductionCMOS technology traditionally used for digital applications

90nm ~ 3.6GHz

130nm ~ 1.5GHz

180nm ~ 1GHz

Aggressive Down-scaling for High-performance microprocessors

↓ Lg ↑ fT

150GHz for a 90nm CMOS process *

Purely CMOS RF- Mixed-signal System-on-Chip

* W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004

European IST IMPACT projectPushing CMOS technology for its use in products operating

well into the radio frequencies (5-20 GHz)

90nm CMOS technology*

Active Device

20-cm P type Si substrate

1.5nm EOT nitrided oxide dielectric

5nm EOT Dual Gate Oxide device

150nm poly gate stack

Cobalt silicide

5 Metal layer Cu back end of line

* W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004

Passive Devices

Cu back end of line High-Q inductors

High-Q MIM capacitors

Junction varactors

MOS-like accumulation-depletion varactors

90nm RF CMOS technology

*S. Jenei et al. Topical Meeting on Silicon Monolithic Integrated Circuits, 2001

**G.J.Carchon et al., IEEE Trans. on Microwave Theory and Techniques, April 2004

CMOS Transistor

Lphysical ~ 70nm

Saturation Vt ~ 0.3V

Ion, NMOS=720A/m, Ion, PMOS=320A/m

Ioff, NMOS= Ioff, PMOS=1.5nA/m

~15ps inverter delay

Digital key performances

10-10

10-9

10-8

10-7

10-6

10-5

0 280 560 840 1120 1400

I off

[nA

/m

]

Ion

[A/m]

Intrinsic Transistor Performance

1.5nA/m

320A/m720A/m

NMOS

PMOS

NMOS

10

12

14

16

18

20

22

30 40 50 60 70 80 90 100

Inve

rter

del

ay,

d [

ps]

p*d [fJ]

Vbias

= 1.05 V

Unloaded Ring oscillator

Vbias

= 1.2 V

Vbias

= 1.35 V

Vbias

= 1.5 V

CMOS Transistor Analogue/RF key performances

0

5

10

15

20

25

30

0

50

100

150

200

250

100 101 102 103 104

gm

/Id

s (V-1

) an

d g

m/g

ds

fT and

fma

x (GH

z)

Drain current, Ids

(A/m)

gm/I

ds

gm/g

ds

fT

fmax

stronginversion

moderateinversion

Moderate inversion Up to 5GHz applications.

Low power consumption.

Strong inversion Up to 20GHz applications.

Higher power consumption.

Design specification:fmax and fT > 5-10 times fapplication

** J. Ramos et al. ESSDERC, September 2004* W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004

CMOS Transistor modelling MOS Model requirements?

Intrinsic model at any operation regime (Id–Vg, Chargers)

First and higher order derivatives of Id (gm/Id, gm/gds,Distortion)

Current noise (1/f , Thermal and Induced Gate noise)

RF model (Impedance levels, current and power gains)

Non Quasi static effects (High frequencies, large devices)

Scalability (Freedom of design)

CMOS Transistor modelling MOS Model 11 – The choice

All requirements fulfilled

Moderate inversion

Distortion

Noise

RF extension

NQS

Scalability

RG

G

DS

B

SUB

Rjun,S Rjun,DRbulk

MM11

Rsub

Cwell

Substrate Network

Gate Resistance

Intrinsic Device

Juncap Juncap

* R. van Langevelde et al. NanoTech 2002 - MSM, pag. 674-677 , April 2002

CMOS Transistor modelling MOS Model 11 – DC modelling

gm/Id and gm/gds

S-parameters Low frequency points

Distortion

DC operation point

Moderate inversion

Ldesign=100nmWdesign=10m

*Courtesy of Philips Research Laboratories

CMOS Transistor modelling MOS Model 11 – Analogue modelling

Gate capacitance (accumulation to inversion, poly-depletion) Overlap capacitances (Bias dependent) Junction capacitance (STI-edge, gate-edge and bottom effects)

*Courtesy of Philips Research Laboratories

CMOS Transistor modelling NQS MOS Model 11 – S-Parameters

fT

5-20 GHz range covered

Passive Devices

Passive device processed on standard 5LM Cu/Oxide BEOL.

Provide circuit designers with a complete set of devices.

In-house RF SPICE models.

Alternative add-on solution for High-Q inductors

Metal Insulator Metal CapacitorMIM Technology

0

1 10-12

2 10-12

3 10-12

4 10-12

5 10-12

0 500 1000 1500 2000 2500 3000 3500 4000

Cap

acit

ance

, Cap

(F

)Capacitance area, A (m2)

MIM Cap TaN + Oxide

Target 1.1fF/m2

1.06 fF/m2

Y = M0 + M1*XM0=0M1=1.062e-15

Specific capacitance of 1.1fF/m2

Embedded in Cu BEOL (M2- M3) TaN plates (50-100 Ω/square) 35nm Silicon Oxide dielectric

*S. Jenei et al. Topical Meeting on Silicon Monolithic Integrated Circuits, 2001

Metal Insulator Metal CapacitorMIM In-house RF Model

Pass-through equivalent circuit

Coupling to substrate

Q11=-Im(1/y11)/Re(1/y11)

Top plate grounded

Q22=-Im(1/y22)/Re(1/y22)

Bottom plate grounded

429fF (Optimized layout)

443fF

Lines ModelsSymbols Measurement data

Q11

Q11Q22

Q22

429fF MIM Capacitor

Variable Capacitors - Varactors Varactor Technology

N+/Pwell and P+/Nwell Junction varactors

MOS-like accumulation-depletion varactor

N+

oxide

Poly - silicon

N+

Nwell

7.0E-13

8.0E-13

9.0E-13

1.0E-12

1.1E-12

1.2E-12

1.3E-12

-1.00 -0.50 0.00 0.50 1.00

Vbias (V)

C (

F) N+/Pwell

P+/Nwell

Variable Capacitors - Varactors Junction varactor In-house RF Model

Linear passive components Spice diode models Frequency and bias dependent

Pass-through equivalent circuit

Variable Capacitors - Varactors MOS-like varactor In-house RF Model

Pass-through equivalent circuit

Linear passive components Frequency and bias dependent

BEOL High Q Inductors 5 Level of Metal Cu/Oxide BEOL

Inner

Outer

Conventional CMOS Cu/oxide BEOL High sheet resistance (35m/square) Lossy substrate (20-cm P type)

SpiralShunted M4 & M5

UnderpassShunted M2 & M3

PatternedPoly or M1

shield

G S G

G S GIMD4

IMD3

IMD2

IMD1

PMD

*S. Jenei et al. Electron Device Letters, April 2002

BEOL High Q Inductors BEOL Inductors In-house RF Model

Double lumped equivalent circuit to account for distributed substrate coupling. Layout + process information used in closed form calculation of the model parameters.

*S. Jenei et al., IEEE Journal of Solid-State Circuits, January 2002

BEOL High Q Inductors BEOL Inductors In-house RF Model

RF circuit demonstrators

Voltage-Controlled Oscillator (VCO)

* D. Linten et al. Symposium on VLSI Circuits, June, 2004

SchematicMicrograph

• MIM Capacitors• Junction Varactors• BEOL High Q Inductors• NMOS Transistors

RF circuit demonstrators

Voltage-Controlled Oscillator (VCO)

Only possible with accurate device models and careful circuit design!!!

Conclusions

A fully integrated RF CMOS technology fabricated in a 90nm RF CMOS FEOL with High-Q passive components processed on a standard 5LM Cu/Oxide BEOL, has been presented.

Accurate modelling of the active a passive devices made possible RF circuit design.

RF CMOS can definitely become the technology of choice for large volume RF applications and Mixed-signal SoC platforms.

IMEC P-line for processing the devices

Flemish IWT for financial support

The European commission in the framework of IST-2000-30016 IMPACT

for the financial supports

Acknowledgments

D.Linten et al. “Low-power 5 GHz LNA and VCO in 90 nm RF CMOS”, Symposium on VLSI Circuits, June, 2004

W.Jeamsaksiri et al. “Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA”, Symposium on VLSI Technology, June, 2004

W.Jeamsaksiri et al. “Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors”, IEEE Transactions on Electron Devices, March, 2003

D.Linten et al. “A 5GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS”, Accepted for publication on the European Solid-State Circuits Conference, ESSCIRC, September 2004.

V.C. Venezia et al. “The RF potential of high-performance 100nm CMOS technology”, European Solid-State Device Research Conference, ESSDERC, September 2002.

M. Jurczak et al. “Elevated Co-silicide for sub-100nm High Performance and RF CMOS”, European Solid-State Device Research Conference, ESSDERC, September 2002.

List of related publications

D.Linten et al. “A 328 mW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor ”, Accepted for publication on the Custom Integrated Circuits Conference, CICC, October 2004.

S. Thijs et al. “Implementation of Inductor Based ESD Protection for 5.5 GHz LNA in 90 nm RF CMOS – Concepts, constraints and Solutions”, Accepted for

publication on the Electrical Overstress and Electrostatic Discharge Symposium, EOS/ESD, September 2004.

S. Thijs et al. “Impact of Elevated Source Drain Architecture on ESD Protection Devices for a 90nm CMOS Technology Node”, Electrical Overstress and Electrostatic Discharge Symposium, EOS/ESD, September 2003.

D.Linten et al. “Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain”, European Solid-State Device Research Conference,

ESSDERC, September 2003.

D.Linten et al. “Influence of Back-End architecture on the performance of RF CMOS VCOs”, Southwest Symposium on Mixed-Signal Design, February 2003.

List of related publications

W.Jeamsaksiri et al. “Optimal frequency range selection for full C-V characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide MOSFETs ”, International Conference in Microelectronic Test Structures, ICMTS, March, 2004

M. Ferndahl et al. “40 and 60 GHz Frequency Doublers in 90-nm CMOS”, International Microwave Symposium, MTT-S, June 2004.

G.J. Garchon et al. “Wafer-Level Packaging Technology for High-Q On-Chip Inductors and Transmission Lines”, IEEE Transactions on Microwave Theory and Techniques, April 2004.

G.J. Garchon et al. “High-Q above-IC inductors and transmission lines - comparison to Cu back-end performance”, Electronic Components and Technology Conference, ECTC, June 2004.

G.J. Garchon et al. “Wafer-Level Packaging Technology for Extended Global Wiring and Inductors”, European Solid-State Device Research Conference, ESSDERC, September 2003.

M. Ferndahl et al. “The influence of the gate leakage current and the gate resistance on the noise and gain performances of 90-nm CMOS for micro and millimeter-wave frequencies ”, International Microwave Symposium, MTT-S, June 2004.

G.J. Garchon et al. “High-Q RF Inductors on standard Silicon realized using wafer-level packaging techniques”, International Microwave Symposium, MTT-S, June 2003.

List of related publications

European IST IMPACT project

Technologydevelopment

(WP3)

Devices modelling

(WP2)

Circuits design(WP1)

IMEC Philips PITS

IMEC Philips Research

IMEC Ericsson

Chalmers University