04/22/23

A 32-bit ALU with Sleep Mode for Leakage Power Reduction

Manish KulkarniDepartment of Electrical and Computer Engineering

Auburn University, Auburn, AL 36849mmk0002@auburn.edu

Low Power Design of Electronic Circuits ELEC 6270, Spring 2009

Objectives:

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Modify existing ALU circuit to incorporate Sleep mode in order to reduce leakage power Study the effect of Sleep transistor network on the ALU circuit in Active and in Sleep mode Design a Sleep transistor network for maximum Leakage Power savings for a given delay overhead Find a set of vectors which causes minimum leakage power in ALU during the sleep mode

Power Gating:

Sleep

Sleep

VDD

(a)Header(PMOS)

Switches for power gating

(b) Footer(NMOS)

Switches for power gating

(c) Both Header & Footer

Switches for power gating

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David Chinnery, Kurt Keutzer, "Closing the Power Gap Between ASIC & Custom, Tools and Techniques for Low-Power Design", chapter 10, authored by Jerry Frenkil, co-author Srini Venkatraman, Springer 2007.

Circuit Diagram:

Data 1

Data 2

Add / Sub

Data Out

32

32 32

32 - bitALU(Low Vt)

Sleep Transistor Network(High Vt)

VDD

Sleep

GND_V

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Design of Sleep Transistor: It is a tradeoff between Saving in Leakage power and Speed This method tries to Minimize Leakage power during sleep mode for a given delay penalty

Anis, M., Shawki, A., Mahmoud ,M., Elmasry, M., “ Dynamic And Leakage Power Reduction In MTCMOS Circuits Using An Automated Efficient Gate Clustering Technique”, Proc. of the 39th conference on Design Automation, June 2002, pp. 480-485

Delay of a Gate without Sleep transistor is given by

Delay of a Gate with Sleep transistor is given by

Where, α is Velocity Saturation Index (1< α < 2)α = 1.8 for 45nm

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Design of Sleep Transistor (Cont..):

= 4774.4 ≈ 4800

This is obtained by simulating the ALU circuit and finding the Maximum current through GND

The current flowing through Sleep transistor is expressed as

Where,μn = Electron mobility = 150 cm2/V.s at 90oCCox = 19.7 X 10-7 F/m for 45nmVtL = 0.466 V , VtH = 0.6226 V and VDD = 1.1 V for 45nm

The Sleep transistor size is then obtained as

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Allowing 5% overhead on delay

Circuit Diagram:

Data 1

Data 2

Add / Sub

Data Out

32

32 32

32 - bitALU(Low Vt)

Sleep Transistor Network(High Vt)

VDD

GND_V

T1 T2 T3 T79 T80

Sleep04/22/23 7

Experiment Setup : The 32-bit ALU circuit is tested for 200 random vectors of 65 bit each The vectors are applied with to the circuit in following modes

200 vectors with Sleep = 1 i.e. Active Mode 200 vectors with Sleep = 0 i.e. Sleep Mode 200 vectors with Sleep changing from 1 0 after 100 vectors to get Sleep time 200 vectors with Sleep changing from 01 after 100 vectors to get Wakeup time

During Sleep mode with 200 vectors a ‘Minimum Leakage’ power consuming vector is identified

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Some of Results from this experiment have been shown in following slides.

Active Mode:Average Dynamic Power : -1.804 dBmW = 660.0 uW

Average Leakage Power : - 14.683 dBmW = 34.01 uW

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Sleep Mode:Average Dynamic Power : -35.197 dBmW = 302.204 nW

Average Leakage Power : - 36.174 dBmW = 241.32 nW

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Sleep Time:Time taken by the Sleep transistor network to bring circuit to sleep mode after the Sleep signal is asserted. Sleep time = 14nS

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Wakeup Time:Time taken by the Sleep transistor network to bring circuit to normal operation (active) mode after the Sleep signal is de-asserted. Wakeup time = 0.4nS

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Sleep Mode Power for Complete Vector Set:Min. Leakage Power = -38.948 dBmW = 0.1274 uW

Observed when Input vectors 0X3FB1F6F7 & 0X84AA877B are applied.

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Minimum Leakage Power Vector @ 6.9 uS

Circuit Diagram (Modified):

Data 1

Data 2

Add / Sub

Data Out

32

32

32

32 - bitALU(Low Vt)

Sleep Transistor Network(High Vt)

VDD

GND_V

T1 T2 T3 T79 T80

Sleep

0X3FB1F6F7

0X84AA877B

Sleep

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Active Sleep with changing input vectors

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Active Sleep with Min. Power Vector at input

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Power Consumption during sleep mode when vectors are varying at the input

Power Consumption during sleep mode when constant vector is applied at the input

Normal( uW)

Sleep (nW)

Power Saving (%)

Sleep Mode with Min Leakage Input Vector

Power Saving(%)

Avg. Dynamic Power

660.0 302.204 99.95 % 0 nW 100 %

Avg. Leakage Power

34.01 241.32 99.29 % 127.4 nW 99.61%

Peak Power 5040.5 1361.131 99.79 % 127.4 nW 99.99 %

Minimum Power

29.2549 127.4 99.56 % 127.4 nW 99.56 %

Summary of Results:

Sleep Time 14 nS

Wakeup Time 0.4 nS

Area Overhead* 1456 1536 CMOS devices ( 45.05%)

04/22/23 17* The area overhead can be reduced by reducing number of sleep transistors through clustering.

References:

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Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi, “ Low Power Methodology Manual for System On Chip design” Springer 2008 Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, Pradip Bose, “Microarchitectural Techniques for Power Gating of Execution Units”,proc. Of ISLPED 2004, pp. 32-37 Bushnell, M., Yu, B., “A novel dynamic power cutoff technique(DPCT) for active leakage reduction in Deep Submicron CMOS circuits”, Proc. Of ISLPED october, 2006, pp. 214-219 Neil H.E. Weste, David Harris, “CMOS VLSI Design” Third Edition, Boston: Pearson, 2005 David Chinnery, Kurt Keutzer, "Closing the Power Gap Between ASIC & Custom, Tools and Techniques for Low-Power Design", chapter 10, authored by Jerry Frenkil, co-author Srini Venkatraman, Springer 2007. Anis, M., Shawki, A., Mahmoud ,M., Elmasry, M., “ Dynamic And Leakage Power Reduction In MTCMOS Circuits Using An Automated Efficient Gate Clustering Technique”, Proc. of the 39th conference on Design Automation, June 2002, pp. 480-485