a 2.5 gbls cmos add drop multiplexer€¦ · a 2.5 gws cmos add - drop multiplexer for atm master...

A 2.5 Gbls CMOS Add - Drop Multiplexer

for ATM

by

Nicolae Goiinescu

A thesis subrnitted in conformity with the requirements

for the degree of Master of Applied Science

Depammnt of Electrical and Computer Engineering

University of Toronto

0 Copyright by Nicolae Goîinescu 1999

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In memory of my mother.

Abstract Page I

A 2.5 GWs CMOS Add - Drop Multiplexer for ATM

Master of Applied Science, 1999

Nicolae Golinescu

Department of Electrical and Computer Engineering

University of Toronto

ABSTRACT

Asynchronous Transfer Mode (ATM) is used to accommodate the simultaneous

transmission of voice, data and image, in an integrated manner using the same network. It

is based on the transfer of fixed-length cells. In order to connect the source of information

to the optical transmission line, a universal ATM functional block, the Add-Drop Multi-

plexer (ADM), is used. The block adds or extracts cells (53 byte words) fiom the high

speed data bus. The objective of this work is to implement the ADM in 0 . 5 p CMOS

technology, running at 31 1 MHz or 2.5 Gbls.

The ADM consists of an Input Buffer which provides the selection logic for the

ceil extraction, an Add Module used to insert ATM cells into the high speed data bus, a

Drop Module used to extract the cells fkom the high speed data bus and an Output Module

that prepares the cells for physicai transmission.

The chip was designed and successfuily implemented. It occupies an area of 14.7

mm2 and dissipates 4.5 W of power. The chip was tested functionally at 20 MHZ. High

speed testing was also perfomied at 31 1 MHz by focusing on the critical path of the chip.

A good comlation was obtained bctween simulation and experimental results.

A 2.5 GWs CMOS Adâ-Drop Multiplexer for ATM University of Toronto

Adviowledgments Page II

1 would üke to express my sincere gratitude to Rofessor C.A.T. Salama. Without

his guidance, support and encouragement this work would not have been possible.

1 would also like to thank many people in the VRG group: Jaro Pristupa for ai l the

software and technical related issues, Dana Reem, Dod Chettiar and Anthoula Vlahakis

for theh help.

1 also owe a lot to my former colleagues and fnends: Mehran Aliahmad for being a

tme model, Mehrdad Ramezani, Dusan Suvacovic, Naoto Fujishima, Hormoz Djahan-

shahi, Diana Gradinam, A r i s Balatsos, Jamil Ahmed and Vieet Joshi for their technical

and personal suggestions.

At last but not least, I would Like to thank my patient wife who devoted her time

and effort keeping our family strong in times of great stress.

Greatly appreciated is the financial support from Micronet, Gemum, Mitel, Norte1

Networks and PMC Sierra which made this work possible.

A 2.5 Gb/s CMOS Add-Orop Muttiplexer for ATM University of Toronto

Table of Contents Page IV

htfoàuction ................................................................................................ 20

Block Diagram ........................................................................................... 21

ADM Implementation ...... ..................................................................... 23

2.3.1 h o p Section .................... .... .................................................. 26

................................................................. 2.3.2 Add Section ................... 35

..................................................................... HDL Functional Verification -38

Building Blocks Design ................... ............... .... ..... ....................... 42

.. ........... ............. 2.5.1 Input Buffer ... .... .... ......................................................................................... 2.5.2 Counters 47

2.5.3 CAM .............................................................................................. 50

..................... 2.5.4 SRAM ................................................................... 54

........................................................................ 2.5.5 MUX and DEMUX 58

2.5.6 ECG ................................................................................................ 61

Critical Path Simulation ............................................................................. 62

Sumrnary ......................................................................... .. ................... 64

REFERENCES ................................................................................................................. 66

CHAPTER 3

Experimental Results ........................................................................................................ 67

3.1 Chip Layout .............................................................................b................. 67

3.2 Post Layout Cntical Path Simulation ......... ... ...... ............................... B . 3.3 Experirnental Implementation ....................... ..................... d

3.4 Functional Testing ...................................................................................... 71

....................... 3.5 Speed Testing ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ m b ~ ~ e b ~ ~ ~ ~ ~ ~ ~ b ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ e ~ ~ ~ ~ ~ ~ 7 3

.................................................................................................... 3.6 Summary 75

REFERENCES ................................................................................................................. 76

CHAPTER4

..................................................................................................................... Conclusions 0.77

A 2.5 Gbls CMOS Add-Drop Mulaplexer for ATM University of Toronto

Table of Contents Page V

APPENDIX A

...................................................................................... Tme Single Phase Clock VSPC) 78

FEFERENCES ........... ... ......................................................................*............................ 81

APPENDTX B

..... Clock Distribution ..............................................................*....*.*.....................*.*.......*** 82

........................... REFERENCES ........... .....*.....i................*.**...........*.......*....*.......... *84

APPENDK C

.................................................................. ..................... Test Setup Description .... *.85

A 2.5 GWs CMOS AddDrop MuHiplexer for ATM University of Toronto

List of Figures Page VI

Figure 1.1

Figure 1.2

Figure 1.3

Figure 1.4

Figure 1.5

Figure 1.6

Figure 1.7

Figure 1.8

Figure 1.9

Figure 1.10

Figure 1.1 1

Figure 1.12

Figure 1.13

Figure 1.14

Figure 1.15

Figure 1.16

Figure 2.1

Figure 2.2

Figure 2.3

Figure 2.4

Figure 2.5

Figure 2.6

Figure 2.7

Figure 2.8

LIST OF FIGURES

ATM Traffic 'ISrpes .......................... ........................................................ 2

Typical Ethemet network [l] .................... ............C.......*..............O............ 5

Ethemet Packet Structure [l] ....................................................................... 5

......................................................... lOBaseT LAN [l] ....................... .. 6

......................................... Token Ring LAN [l] ...................................... 7

FDDI LAN [ I l ..................... ................ ........................................................ 8

Packet Switching evolution [4] ............................................................... 9

................................... Typical ATM network [1] ..................................... 1 0

................. Synchronous Transfer Mode .................... ......*................. 1

............................................... Asynchronous Transfer Mode ............... .. 12

ATM Multiplexing Scheme .........................................n.............................. 12

ATM ce11 structure for UNI and NNI ...................................................... 13

VmaI path and virtual channels [Z] ........................................................ 1 4

OS1 Layered Architecture [l] ......................~.................................... 16

SONET ring architecture ........................................................................... 17

ADM distnbuted architecture ................... ....................................... 18

Block Diagram for ADM [l] .................................................................... 21

ADM Core Block Diagram [l] ....................................................... ...........22

Pipelined versus Paralle1 Architecture ....................................................... 22

ADM Logic Chart ............................................................................... 2

Receive Timing Sequence ................................*..................................... 24

ADM High Level Architecture .................................................................. 25

Drop Section .............................................................................................. 28

TRI-DROP Logic Chart .......................................................................... ..29

- --

A 2.5 Gb/s CMOS AddDrop Muîtiplexer for ATM University of Toronto

List of Figures Page VI1

Figure 2.9

Figure 2.10

Figure 2.1 1

Figure 2.12

Figure 2.13

Figure 2.14

Figure 2.15

Figure 2.1 6

Figure 2.17

Figure 2.18

Figure 2.19

Figure 2.20

Figure 2.2 1

Figure 2.22

Figure 2.23

Figure 2.24

Figure 2.25

Figure 2.26

Figure 2.27

Figure 2.28

Figure 2.29

Figure 2.30

Figure 2.3 1

Figure 2.32

Figure 2.33

Figure 2.34

Figure 2.35

TRI-DROP Implementation ...................................................................... 30

DROP-MüX Logic Chart ......................................................................... 31

DROP_MUX Implementation ............................~~......*...~.......~.~~~~. a.am033

DROP-DEMUX Logic Chart .................................................................... 33

............................................................ DROP-DE- Implementation 34

................................................................... BLOCK Signal Generation ....... 35

Add Section ....... ............ ... ....... ................ .. 37

Simulation Structure [6] ............................................................................. 38

HDL Non Event Behavior .......................................................................... 39

HDL Initial Match Sequence ..................................................................... 40 ................................................ HDL h o p and Add Sequence after Match 41

........................................ High Speed Path ..................... ... .... ....... 42

Generic TSPC D Fiip Fiop [3] ..................................................... A

D Flip Flop TSPC with Reset ....................... ..................................... . 45

D Flip Flop TSPC with Set ........................................................................ 6 Synchronous Counter to 5 .......................................................................... 47

PRBS Rinciple ................... ... ............................................................... 48

PRBS Counter to 53 ................................................................................... 4 PRBS Counter to 53 Simulation Waveforms ............................................. 49 CAM Principle ..................... ...... .......................................................... 50

CAM Match Ce ll ...................................................................................... 3 2

CAM Empty Cell Schematic ..................................................................... 53

.................. ................... CAM Empty Celi ........................................... 54

SRAM Ceil ........................................ ~ ~ ~ ~ ~ m ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ . ~ ~ ~ a a ~ ~ ~ ~ a m ~ ~ 5 5

S M Decoder .............................................. .. ...................... ........ ............ 56

h o p SRAM Architecture ..................................................................... .....57

Add SRAMI Architechue ........................................................................... 58

A 2.5 Gbfs CMOS Add-Drop Multiplexer for ATM University of Toronto

List of Figures Page Vil1

Figure 2.36

Figure 2.37

Figure 2.3 8

Figure 2.39

Figure 2.40

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6

Figure 3.7

Figure 3.8

Figure 3.9

Figure 3.1 O

Figure A . 1

Figure A.2

Figure A.3

Figure B . 1

Figure B.2

Figure C . 1

Figure C.2

................................... ................... Classical MUX and DEMUX ....... .. -59

Add Section MUX ..................................................................................... 60

.......................... Empty Ce11 Generator ............... .- ....................... ............................... ADM Schematic & Critical Path ......... 63

............................................................................. Critical Path Simulation 64

................... *.***.**.**.............*.....**..............**** ADM Chip Layout ... ...... 68

...................................................................................... Clock Distribution 69

.... ........ ........... Post Layout Critical Path Simulation ..... .. ..................................................................... ADM Chip Photomicrograph 70

........................... Power Up Test Settuig .................. ....................... 1

Plotted Power Up Test Results ...............................*................................... 72

Functional Test Sening .............................................................................. 72

...................................... ................... Sampled Test Wavefonn .... ....... 73

............. .......*..*.**.*****.**..... High Frequency Measurement Setting ...... 74

.............................................................. Measured Waveforrn at 31 1 MHz 75

............................................................... Ktype and P-type TSPC [II 78

2 ................. ............................ Ktype and P-type DC MOS [l] ......... 79

.... ........ ................... Edge-tciggered TSPC D Flip-Flop [l] .. ... 2

Clock Distribution ...................................................................................... 82

................................................................................... N . Stage Buffer [l] 83

Fixturing of the ADM .............................................................................. *.85 ......................................................... Tested Connectors Correspondence ..86

A 2.5 Gus CMOS AddDrop Mulüplexer foi ATM University of Toronto

List of Tables Page IX

LIST OF TABLES

Table 2.1 PRBS Decoded Values.. ............................................................................. 49

.......................................................................... Table 2.2 CeU Header Values [4] 53

..................................................................................... Table 2.3 Empty Cell Pattern 61

.......................................................................... . Table A 1: Chip Pin Correspondence 87

.. ................... Table A.2. Test Head . HP Modules Fixnuing Correspondence ...... 88

A 2.5 GWs CMOS AddDrop Multiplexer 101 ATM University of Toronto

Acrony ms Page X - -

ACRONYMS

ADM

ANS1

ATM.

CBR

CClTT

CLP

CSMA / CD

DCS

EISA

FDDI

GFC

HEC

LP

ISA

ISDN

LAN

MAN

NC

NIC

NNI

OC

OS1

PAD

PT

Add-hop Multiplexer

American National Standards Institute

Asynchronous Transfer Mode

Constant Bit Rate

Consultative Committee for International Telephone and Telegraphy

Ce11 Loss niority

Carrier Sense Multiple Access 1 Collision Detection

Digital Cross-Comect

Extended Industry Standard Architecture

Fiber Distributed Data Interface

Generic Flow Control

Header Error Check

Intemet Protocol

Industry Standard Architecture

Integrated Services Digital Network

Local Area Network

Metropolitan Ana Networks

Ne twork Communication

Network Interface Card

Network-to-Network Interface

ûptical Carrier

Open System Interconnect

Packet Assembler / Disassembler

Payload lfrpe

A 2.5 Gbis CMOS Add-Drop Muitiplexer for ATM University of Toronto

Acrony ms Page XI

PVC

Qos SDH

SMDS

SONET

SQE

STP

svc TDM

TCP / IP

UNI

VC

VCI

VPI

WAN

Permanent V l a l Circuit

Quality of Service

Synchronous Digital Hierarchy

Switched Multimegabit Data Service

Synchronous Optical Network

Signal Quality Error

Shielded Twisted Pair

S witched V i a 1 Circuit

T h e Division Multiplexing

Transmission Control Protocoi / Intemet Protocol

User-to-Network Interface

V i a i Comection ( V i a 1 Channel)

Virtual Channel Identifier

Virtual Path Identifier

Wide Area Networks

A 2.5 Gbfs CMOS Add-Drop Mulplexer for ATM University of Toronto

Glossary Page XII

GLOSSARY

Meîropolitan Area Network (MAN) - A network connecting computers over a large

geographical area on the order of 100 Km. such as a city or school district.

Wide Area N e ~ r k (WAN) - A network connecting computers within very large areas

on the order of 100 to 1 0 Km, such as States, countries, and the world.

Switch - is a silicon-based device that creates the equivalent of a telephone system, in

which temporary dedicated "virnial" circuits are created, Linking various switch ports.

Router - is a device that operates at the network layer of the OS1 mode1 (see Chapter

1.5), to find the optimum path a packet should take to reach its destination.

Local Area Network (LAN) - A network connecting computers in a relatively smail

area such as a building on the order of 100 m.

Carrier Sense Multiple Access I Collision Detection (CSMAECD) - is a network

access method in which devices that are ready to transmit data first check the channel

for a carrier. If no carrier is sensed, a device can transmit. If two devices transmit at

once, a collision occurs and each computer backs off and waits a random amount of

time before attempting to retransmit. This is the access method used by Ethemet.

lOBaseT - Ethemet specification for unshielded twisted pair cable, transmits signals at

10 Mbps (megabits per second) with a distance Limit of 1 0 meters per segment.

Concentrator - A device that provides a central connection point for cables nom work-

stations, servers, and peripherals. Most concentrators contain the ability to ampli@ the

elecüical signal they receive.

Hu6 - A hardware device that contains multiple independent but co~ec ted modules of

network and intemetwork equipment. Hubs can be active (where they repeat signals

-- -

A 2.5 Gb/s CMOS Add-Orop Multiplexer for ATM University of Toronto

Glossary Page Xlll

sent through hem) or passive (where they do not repeat but merely split signals sent

through them).

N e ~ k Interface Card (NIC) - A board that provides network communication Capa-

bilities to and fiom a cornputer.

Bridge - A devices that connect and pass packets between two network segments that

use the same communications protocol.

Digital Cross Connect @CS) - Part of SONET device that is used to interconnect f ikr

optic rings.

A 2.5 GWs CMOS Add-Drop Multiplexer for ATM University of Toronto

Chapter 1: Introduction Page 1

CHAPTER 1

Introduction

A trend that started in the early '80s and is probably going to continue is the ever

increasing need for bandwidth in communications. More and more data has to be transmit-

ted over different types of transmission media, from copper and fiber to wireless. In addi-

tion voice, data and video have very different characteristics. It is clear that a transmission

protocol that addresses al1 the issues mentioned above is highly needed. The new protocol

should be able to transmit any kind of information: voice, data, image, text and video in an

integrated manner as shown in Figure 1.1. It should have a scalable and flexible bandwidth

and should not be tied to any type of physical implementation or set speed.

In an effort to achieve ail the objectives mentioned, P new transmission protocol,

Asynchronous Transfer Mode (ATM), was proposed in 1988 by The Consultative Corn-

mittee for International Telephone and Telegraphy (CCI'TT) for use for future Broadband

Integrated Services Digital Networks (B-ISDN). Asynchmnous refm to the manner in

which bandwidth is ailocated among connections and users. ATM is seen, in the first

phase, as a transport method for Metmpulitun Area ~etworks* (MAN) and Wide Areu Net-

works** (WAN). It is in these networks where the huge, scalable bandwidth can best be

used. ATM merges voice, video and data into a common format, and provides a connec-

tion oriented packet switching technique, in which al l packets called cells, are of smali

fixed leagth. ATM resources, like bandwidth and buffers are s h a , among usm, they are

* Metmpolitan A m Network - A n e t d comecting computers over a large geographical area on the ordcr of 100 Km, such as a city or schod disîrict.

** Wide Area Neiwork (WAN) - A netwodc conwcting computers within very large areas on the order of 100 to 1000 Km, such as States, corntries, and rhe world.

A 2.5 Gb/s CMOS Add-Drop MuHiplexer for ATM University of Toronto

Chapter1:lntroduction . Page 2 - - - - - - -- - - - --

allocated to the usen only when they have something to transmit. In this way, the n e m k

uses statistical multiplexing to improve the effective throughput. No error control is done

on the information field of ATM cells inside the network. Because of the low bit-error rate

in fiber optic transmission, this function is cost-effectively done in the end system.

ATM Cells

Figure 1.1 ATM Traffic Types

1.1 Packet Versus Circuit 'Ikansmission

When information is sent using ATM, data travels not over a dedicated, physicaily

owned line, but over a shared circuit composed of virtual channels. In traditional Ethemet

protocol (see Section 1.2. l), information is sent through a packet-based delivery tech-

nique. Instead of assigning a fixed line between the two parties, the data is inserted into a

packet and sent on its way on the wire with source and destination addresses encoded. The

destination system looks for packets that are targeted for it and intercepts these.

There are advantages and disadvantages in both techniques. With a virtual circuit,

(ATM) a clear path has to be available from the source point al l the way to the destination

point. If there is a break at any point, the connection is lost and will not be available until a

new path is established. In contrast, a packet delivery mechanism (Ethemet) does not

make any assumptions on the path between the source and destination. If a packet on its

way encounters an obstruction, such as a break, it will not reach the destination and simply

be discarded. The source w u not know if the packet was lost unless the destination

A 2.5 Gbls CMOS Add-Drop Mulüplexer for ATM University of Toronto

Chapter 1 : Introduction Page 3 -

acknowledges a missing packet. To keep a circuit operational, all the swirches* in the path

must know the existence and purpose of the circuit. This means that each switch has to be

able to keep track of many circuits, their sources, destinations, and other parameters at all

tirnes. oute ers** keep track of destination paths but not on a per-connection basis. In order

to fhd out where to send a packet, the router has to process the packet, fhd out the desti-

nation address and additional parameters, look up in its route table the next best delivery

point (router or system), and then send it on its way.

The processing overhead for each of the two methods occurs at different moments.

In ATM case, a circuit has to be established at the start of the connection, and a path must

be determined. This start-up overhead involves informing all the switches in the path of

the details required by this circuit: how large it is, if it is tirne-dependent and its maximum

bandwidth. A packet switch doesn't need to know al1 this; each router along the way will

figure it out for itself if and when it gets the data packets. Since it does not monitor actual

connections between two points, a packet switch normaiiy cannot keep track of the time

sequence of data packets. This has been a challenging problem for packet technology. In

theory if the packet switches fast enough, it will be able to keep track of temporal

sequences of data; however, this has only worked with limited success.

The circuit switch cm keep track of time since then is a fixed path beween the

two points, negotiated at the beginning of the transmission. So data is delivered in proper

temporal sequence as requested during the initial comection establishment. It is easier to

account for a l l data packets in a circuit because the comection Somation and the path

are known. To account for how packets are delivered is one of the biggest problems,

because of the nature of Internet Rotocol (IP) packet delivery through Intemet routers.

There are situations when this issue becomes a senous concem. A packet-based system

can act as a Wtual circuit using some added logic at the end-points. If sequence numbers

* Switch - is a silicon-based device that creates the equivalent of a telephone system, in which temporary dedicaîed "viraial" circuits are created, linking various switcb ports.

** Router - is a device that operates at the network layer of the OS1 mode1 (see Section 15). to find the optimum padi a packet should take to reach its destination.

--

A 2.5 Gbls CMOS Add-Drop Multiplexer for ATM University of Toronto

Chapter 1 : Introduction Page 4 - - -

are assigned to packets, the receiving end can identiQ which packets are missing and

inforrn the sending end. The sender then attempts to deliver the sarne packets again to the

destination. These packets may also establish specific routes for delivery if needed. Basi-

cally, what is done in these cases, is to improve the logic at each end for much finer control

of packet delivery.

1.2 Network Protocois

The way the network is structured is known as its topology. To understand the

ATM concept, one has to compare some of the available solutions on the market and the

compromise achieved using ATM. None of the existing Network Communication proto-

cols is the perfect solution for al1 situations, but ATM is closest to achieve this goal. The

key elements of some cornpetitive alternatives are discussed below.

1.2.1 Ethernet

With the surge in the number of computers and computing power, at the beginning

of the 1980's, companies tried to find an inexpensive way to share expensive hardware,

databases and software packages. This is when, (Digital Equipment, Xerox and Intel),

worked iogether to develop the first Local Area ~etwork* (LAN). In LANs, one of the

major advantage, is the distributed processing. The file server doesn't need to perform all

the processing a minicornputer or mainfnune has to perform.

The IEEE 802 Cornmittee, through the IEEE 802.3 document, set the specifica-

tions for the LAN and the k t Ethemet protocol was created. A typical Ethemet architec-

ture [l] is show in the Figure 1.2. The ideal Ethernet bandwidth is 10 Mbps. It is a bus

network and a break in the cabling will disrupt the entire network. One of the main draw-

* h a 1 A m Network (LAN) - A network co~ecting computers in a relatively small area such as a M d - ing on the order of 100 m.


Chapter 1 : l nttoduction Page 5

Terminator Terminator Figure 1.2 Qpical Ethernet network [l ]

backs of the Ethemet architecture is that it is a contention network topology - ody one

user can transmit data at a time and workstations compte to use the network. There is a

possibility of data collision causing the data rate to drop significantly. To address this issue

a specific method for accessing the LAN was created: the Carrier Sense Multiple Access 1

Collision ~etection* (CSMA 1 CD). Ethemet is best suited for short data bursts, like data

base inquiries. A typical Ethemet packet is show in Figure 1.3. Ethemet offers the fol-

lowing advantages: inexpensive, good for b w t y traffic, fast (10 Mbps) and disadvantages:

no guaranteed time for transmission and not efficient for heavy traffic. Ethemet served the

computing comrnunity well at the beginning of the networking era. As networking traffic

started to increase, Ethemet, could no longer meet the traffic requirements.

Figure 1.3 Ethemet Packet Structure [l]

* Carrier Sense MultipIe Access I Collision Defection (CSMAICD) - is a netwoilr access method in which &vices mat are ready to trrnsmit âata h t check the cbannel for a carrier. If no carrier is sensed, a device can trammit. If two devices trammit at once, a collision occurs and each compter backs off and waits a random amount of time before attemptiag to retransmit. This is the acccss method used by Etherntt.

check sequence

A 2.5 Gb/s CMOS Adâ-Drop Muitiplexer for ATM University of Toronto

J

Rotocol type

Destination address

Source address


1 1OBaseT Ethernet

Xn 1990, the IEEE 802.3 Committee foimalized a set of specifications for Ethemet

over unshielded twisted-pair wire. This set of specifications is known as 10~ase f . This

type of Ethernet became very popular for its ease of instdlation and its inexpensive

twisted pair copper wiring, in contnist with the more expensive coaxial wiring used eariier.

The other main reason for its populanty is the change in physical structure. Instead of a

central cable acting as data highway, lOBaseT uses a wiring concentrator** known as the

hub***. lOBaseT has a bus structure identical to the traditional Ethernet, but has a physical

star structure, as seen in Figure 1.4. The central hub reliability is critical.

I I

Figure 1.4 1 OBaseT LAN [l]

* 1 OBaseT - Ethemt speciiication for unshielded twisted pair cabie, transmits signals at 10 Mbps (megabits per second) with a distance limit of 100 meters per segment.

** Concemutor - A devia chat provides a central connection point for cabies h m workstations, suvers. and peripherals. Most concentrators contain îhe ability to amplify the electrical signal they receive.

*** Hu& - A hardware device ihat contains multiple idependent bit connected modu1cs of mtworic and internetwal cpuipwot. Hubs can k active (where ibey repat signals sent tbrough them) or passive (where they do wt repeat but merely split signals sent througb them).

A 2.5 Gb/s CMOS Add-Drop Muhiplexet for ATM University of Toronto

Chapter 1 : I ntroducüon Page 7

Figure 1.5 Token Ring LAN [l]

The next step for improving Network Communication was made by IBM with the

Token Ring. The main improvement was that the new communication protocol ensured

that no data would be lost through collisions. Unlike Ethemet, Token Ring is a nonconten-

tion network. A special bit pattern is circulated across the network. When a user wants to

send data across the network, he will set the token bit pattern to indicate that the network

is in use. After the transmission has taken place, the pattern is reset, to indicate a free net-

work. Data is sent at 4 Mbps or 16 Mbps, depending on the Network Interjke c d * (NIC) and the concentrators. Although Token Ring has a lower transmission speed than

Ethemet, because of its mncontention nature, there is a high throughput for heavy trafic,

excellent mainfiame comectivity, guaranteed transmission and since it forms a ring (as

seen in Figure 1.5), it bas bener protection against network w i ~ g failure. As for disad-

vantages, this topology is expensive and it does not offer an option for higher traasmission

-

* Network Interface Card (MC) - A board that provides network communication capabüities to and h m a compter.

A 2.5 Gbls CMOS AdbDrop Muitiplexer for ATM University of Toronto

Chapter 1 : Introduction Page 8

12.4 Fiber Distributecl Data Interlace (FDDI)

The next step in development of Network Communication was FDDI which corn-

bines the advantages of lOBaseT and Token Ring topologies and goes a step M e r , offer-

hg 100 Mbps transmission over twisted pair wire or fibre. It uses a dual ring approach as

seen in Figure 1.6. This is an added protection against system failure. The primary ring

caries information and the secondary ring carries control signals. FDDI operation is simi-

lar to that of Token Ring, but the token can be held by one single station for a predeter-

mined time period. This enables sending multiple frames, without stripping hunes, before

releasing the token. FDDI is fast, handling speeds up to 100 Mbps and when fiber is used

the transmission is immune to electromechanical interference. On the downside, it is

expensive and bridges', routers and concentrators are needed to operate with Token Ring

and Ethernet.

Oual Ring Rber /. Network

Concentrator

Figure 1.6 FDDI LAN [l]

The above mentioned topologies are the most cornmon fiame based Network

Communication. Many compiinies are Qing to corne with improved versions. Some mon

recent developments are: Full-Duplex Ethemet, Switched Token Ring, 100BaseT. 1ûûVG-

* Bridge - A devices that coaacct and pass packets between two network segments that use the same communications pmtocol.

A 2.5 Gbls CMOS AdbDrop Multiplexer for ATM University of Toronto


AnyLAN and Fibre Channel. For dl but the Fiber Channel topology, it is very difficult to ?

overcome the 100 Mbps barrier. When it comes to MANS and WANs faster solutions were

investigated. A suggestive evolutionary interaction among the various attempts for solving

Network Communication is given in [4] and shown in Figure 1.7.

OLDER ,, OS1 ' ISDN Fast Packet 1

X.25 Frame Relay

TCP/IP ATM Fast Ethemet FDDI SMDS

NEWER

Figure 1.7 Packet Switching evolution [4]

1.2.5 ATM.

The organization that sets the standards for ail the issues related to the ATM topol-

ogy is The ATM Forum, established at the 1991 Fa11 Interop show, presently having more

than 800 members. The steps involved in an ATM transmission, a comection-oriented

system, are: identify the address of the destination, detennine the route in the network to

the destination, establish the precise instructions needed by each node dong the network.

To make possible communication between different devices and the ATM network, inter-

faces are needed. As seen in Figure 1.8 there are two types of interfaces: User-to-Network

Interface 0 and Network-to-Network Interface (N'NI) developeâ by the ATM Forum.

When a signaling request is received across the UNI, it is passed across the network to its

final destination. If the system agrees to the connection, then a v h a l channel is formed

for the whole duration of the transmission. Vmal Channel or V i a 1 Comection (VC) is

defineci at the beginning of the c d . The path remains unchanged for the duration of the

comection. UM contains mapping uiformation, so the ceils can be routed properly. Each

A 2.5 Gbls CMOS Add-Drop MuWiplexer for ATM University of Toronto


cell has information about the mapping which is contained in the Viaual Path Identifier

(VPI) and V l a l Channel Identifier (VCI).

NNI Ti - witeh ' ' IV' 1 1 UNI

ATM Y switch 1 /,/Lq UNI

UNI Figure 1.8 'ZLpical ATM network [ I l

1.3 ATM in detail

Unlike other packet technologies [2] [3] that use a variable data field, ATM uses

very short (53 bytes), fixed length packets, called cells. Each packet contains the user data

and information used for movement across the network, iike: address, scquencing and

error control. It runs on top of protocols like Fiber Channel and Synchronous Optical Net-

work (SONET). ATM approach is different than Time Division Multiplexing (TDM) used

extensively in the past. TDM uses a fixed time-slot, with the major drawback that if one

channel dœsn't have data to transmit, the slot runs empty. ûne example of TDM is the T-

carrier system. In this approach, dedicated physical paths are established when the con-

nection is set up. The Synchronous Transfer Mode (STM) terminology used in this case

refers to the fact that each tirne slot is synchronized to the frame as seen in Figure 1.9. For

Tl, as an example, there are 24 channels. Instead of using addresses, in STM, the position

in the hime determines the channel. Even if one of the channels is idk, it can't be used by

A 2.5 GWs CMOS Adâ-Orop Multiplexer for ATM University of Toronto


another more needy network participant. In the case of voice transmissions this bandwidth

loss is not so critical. But in case one would want to send data and voice on the same path

and time slots would mn empty, the inefficiency is obvious.

Synchronous Transfer Mode (STM)

Figure 1.9 S ynchronous Transfer Mode

ATM on the other hand, fiils in any empty space with data fiom any channel,

depending on needs, providing the highest bandwidth al1 the time. It is thenfore some-

times called banhvidth on demund technology and referred to as label rnultiplexing as

opposed to position multip1exuig. Figure 1 .IO shows a Stream of ATM cells. The order of

the cells does not have a fixed timing relationship, and the order depends on the needs of

the moment, thus achieving statistical rnultiplexing. ATM is a comection-oriented tech-

nology, in contrast to most LAN protocols that are co~ectionless. Once a connection is

established, ATM ceiis are self-routing, following the same path from source to destina-

tion. Because ATM ceîis are small and of h e d length (oniy 53 bytes), there is no need for

additionai buffers.

Ethemet and Token Ring, with variable length packs, need to be buffered and

checked for errors, before king transmitted. Switching hed-shed cells makes possible to

implement the algorithm in silicon, thus eliminating delays caused by software. Since

ATM does not reserve a specific t h e dot within the fÎame, there is very linle latency in

A 2.5 Gb/s CMOS AddOrop Muitiplexer for ATM University of Toronto


transmission and the 53 bytes size is a compromise. It ensures that video and voice can be

given pnority, and waiting tirne is less than 0.3 ps at 155 MWs.

Asynchronous Transfer Mode (ATM)

info D cb

I" Figure 1.10 Asynchronous Transfer Mode

A suggestive way of showing how

and data is multiplexed in an ATM Stream

0 ATM

information from various sources: audio, video

is given in Figure 1.1 1.

0 Fiber Optic Channel 0

Station A 0 Station 6 0 Station C

Station 0 0 EmpW O

Figure 1.1 1 ATM Multipiexing Scheme

Sources A to D have various transmission needs. Some have bursty transmissions

with a lot of idle periods of tirne, others have a constant flow of heavy data. AU the sources

are allowed access to the network in a statistical order, in such a way, that the Quality of

Service (QoS). traded at the call setup, is met al i the tirne. For al1 the w o n s above, ATM

is best suited for mkhg different types of transmissions, such as voice, image and corn-

A 2.5 Gb/s CMOS AddDrop Mulüplexer for ATM University of Toronto


puter data. Major organizations that are interested in ATM technology hclude the enter-

tainment industry, large hancial institutions, govemmental agencies and engineering

high-tech fhns, ail of which generate a very heavy LAN trafic.

1 .1 ATM Characteristics

ATM cells are 53 bytes long, consisting of a 5 byte header and a 48 byte payload

field. As seen in Figure 1.12 there is a slight difference between NNI and UNI header. In

NNI header, the Generic Flow Control (GFC) field is used for an expanded VPI. The rok

of each header field are described and explained below [4,5]:

UNI cell header fields Byte #

NNI cell header fields Byte #

Figure 1.12 ATM cell structure for UNI and NNI

GFC, is used only across UNI to control aafnc flow and prevent overload condi-

tions when supporting multiplexing.

Payload Type (PT) identifies the payload type c d in the ce11 and control proce-

dures. It discriminates between a payload of user information and one of manage-

ment information.

CeU Loss Pnority (CU) indicates ceil's loss of priority. A 1 in this field indicates

that the cell can be discarded if congestion occurs.

A 2.5 Gb/s CMOS AddDrop Muîtiplexer for ATM University of Toronto


Header Error Check (HEC) can detect single-bit and some multiple-bit enors. It

dso identifies the start of each ce11 within a serial bit Stream.

VPI and VCI fields, route the cell through the network from sender to destination.

VPI describes a semi-permanent VP and can accommodate up to 2' - 256 paths for

UNI and 212 - 40% paths for NNI.

VCI describes a VC, that is assigned dynamically, at the setup of a call. There can

be up to 216 = 65536 possible channels in a VP.

In Figure 1.13 one intuitively can see how a physical transmission path can have

several VPs and each of them might contain several VCs.

Physical vc '-771 Transmission )

Figure 1.13 V i a 1 path and v h a l channels [2]

1.3.2 ATM highlights

ATM offers the following benefits [4]:

Integration of multiple trafic types

Efficient bandwidth use by statistical multiplexing

Guaranteed bandwidth and resource allocation

Dynamic bandwidth management

High service availabiliîy

Multiple Quatity of S e ~ c e (QoS) class support

Automatic configuration and failure recovery - - - - - - pp -

A 2.5 Gbfs CMOS AWOrop MuNiplexet for ATM University of Toronto


Cost-effective fixed length ce11 processing

Longer iife cycle - futureproof investment

On the downside ATM has the following disadvantages:

Lack of applications development

ûperation and rnanaging costs are still high

With these advantages, ATM is most ükely to be adopted as a transmission mode

of choice in future networking environment.

1.4 Layered Architecture

The Open System Interconnect (OS0 model seen in Figure 1.14 is the bais for

Network Communication. The OS1 model is sirnilar to what happens in a company with a

hierarchical organization: each department receives orders from the department above it. It

uses a corporate manual of procedures to determine how to handle these tasks. M e r pro-

cessing, it hands d o m orders to the depamnent under it. Further, each department needs

data in a certain format. M e r receiving it, the information is processed and refomatted to

meet the requirements for the department below. After the data arrives at the "mail room"

(the lowest department), it will have attached severai instructions, depending on the

departments whose input was required. Ail these instructions remain with the correspond-

h g data and will be needed when data arrives at a different company. There, it will move

up the various department levels in a reversai process. A precise alignment with the OS1

layers is not necessary however.

In ATM the correspondent hctional layers are:

Physical Layer that sends and receives information in the form of electrkal or opti-

cal signals over a physical transmission path

ATM Layer that performs the cell switching: accepts cells, determines the trans-

mission path and fomiats the ceU header before transmission

A 2.5 GWs CMOS AddDrop Muttiplexer for A f M University of Toronto


ATM Adaptation Layer (AAL) that provides the interface between the ATM user

software and the ATM network, king implemented only in ATM endpoints.

At send point, AAL receives a bit Stream of data from the ALU user software and

structures it in a celi format suitable to be send across the ATM network. At the

receiving end the process is reversed.

ATM and AAL layers correspond to parts of OS1 layer 2 (Data Link). The addnss

field of the ATM ceii header, has a network wide cormotation, that is like OS1 layer 3.

Host A Host B Application Application

1

Presentation Presentation I

Session Peer-to-peer Session Transport Transport Network Neîwork Data Link Data Link

1

Network media

Figure 1.14 OS1 Layered Architecture [ 1 ]

A 2.5 Gbls CMOS Add-Drop Muliplexer for ATM University of Toronto


ATM in a SONET environment

Figure 1.15 SONET ring architecture

An important part of B-ISDN is the specifications of the SONET standard for

physical layer. SONET is a modular family of rates and formats for interfaces used in opti-

cal networks. The basic SONET rate of 5 1.84 Mbps, Optical Carrier 1 (OC-1), is the stan-

dard incrementai rate for alI higher speeds. Today's WANs use ATM as switching platform

and SONET OC-3 (3 x 51.84 - 155.52 Mbps) as the transport system.

SONET has a Nig architecture [6], similar to FDDI, with a self-healing feature,

meaning that it cm recognize an interruption of the fibre, or other type of failure, rerouting

traffic before senous performance degradation OCCLUS. A schematic SONET - ATM archi-

tecture is shown in Figure 1.15. As seen, apart fiom the A m switch, there is a unique

component to the SONET architecture. This Add-Drop Multiplexer (ADM) is the main

focus of this thesis. Together with another component, the Digital cross-connec{ @CS),

it gives SONET its self-heaüng capabilities. It acts like a distributed MUX / DEMUX

* Dl'gitol Cross Connect @CS) - Part of SONET device that is used to interconnect fikr optic rings.

A 2.5 Gb/s CMOS AcWDrop Mulaplexer for ATM University of Toronto

Chapter 1 : Introduction Page 18 - --

(Figure 1.16), taking in many low speed data streams and one higher speed Stream. It

cornes wiih the capability of selectively adding input streams and dropping off data at their

destination. From system point of view, the ADM belongs in the ATM layer. It perfoms

ce11 rnultiplexing and demultiplexing, VCI / VPI translation. header generation and extrac-

tion and has some flow control functions.

155 1 622 Mbps 155 1 622 Mbps 155 1 622 Mbps

Figure 1.16 ADM distributed architecture

1.6 Objective and Outline of the thesis

The main objective of this thesis is to design an ADM, with a high throughput of

2.5 Gbps (8 bits at 3 1 1 .O4 Mhz) and supporting low speed co~ections of 155 1 622 Mbps

(8 bits at 19.44 / 77.76 Mhz). Although a BiCMOS process could be used satisfactorily,

the higher cost of BiCMOS (approximate 30% higher than CMOS), the limited supply and

the lower integration level due to the bipolar transistors makes this often unlikely. CMOS,

as a mainstay technology, is a more likely approach for the design of the ADM, using a

supply voltage of 5 V. The ADM must aiso address other issues, like: statistical multiplex-

ing, lost cells, available celis, ce11 request and start of cell. This is a challenge, since at

present the only available ADMs have a throughput of 155 Mbps and 622 Mbps. However,

based on experimental results obtained by Madsen et al [7], an ADM which works at 2.5

Gbps, hm been implemented, using GaAs technology. A 0.5 pm CMOS based chip work-

h g at this fkequency, would be a much cheaper option.

In Chapter 2 the whole chip is analyzed, starting with the high level hierarchy. The

block diagram and the functioning chart is descriid. All the components are individually

considend and simulation results are discussed. The layout choices are then highlighted



and p s t layout simulations results are then provided. In Chapter 3 the testing of the exper-

imental chip is discussed and the results are compared to simulation. Conclusions are

given in Chapter 4.

References

[il S. Schan, Understanding ATM, McGrow-Hill, New York, 1996

[2] F. Fm Mazda, Packet Based Communications, Buîîerworth-Heinemann, Oxford, 1996

[3] J. Lane, "ATM knits voice, data on any net", IEEE Spectrum, pp. 42-45, Febmary

1994

[4] D. E. McDysan and D. L. Spohn, ATM - theory and application, McGraw-Hill, New

York, 1995

[SI M. De Rycker, ATM - Solution for Broadband ISDN, Prentice Hail, New York, 1995

[6] T. M. Chen and S. S. Liu, ATM Switching Systems, Artech House Inc., Norwood,

1995

[7] J. K. Madsen and P. S. Lassen, "A 2.5 Gbps ATM Add-Drop Unit for B-ISDN Based

on a GaAs LSI", IEEE Journal of Solid-State Circuits, vol. 3 1, pp 1400- 1405,1996

- - -

A 2.5 Gb/s CMOS Add-Dtop Multiplexer for ATM University of Toronto

Chapter 2: AddDrop Muitiplexer Design Page 20

CHAPTER 2

Add-Drop Multiplexer Design

2.1 Introduction

As discussed in Chapter 1, SONET networks are preferentially a m g e d in rings

providing an altemate route in case of a fiber cut or failure of a node. Ring networks are

less expensive than point - to - multipoint or star configured fiber optic networks since

only two fibers (versus two for each location) are required to support all users or network

elements on the ring. Trafnc can be routed in either direction around the SONET ring. In

case the primary path is cut, trafiîc is very quickly re-routed. One important element in the

ring topology is the ADM. In real life network environments, the information msferred

between the two endpoints in a circuit is duplicated. One copy of al1 information (voice 1

data 1 image) travels on the primary path in the clockwise direction and another copy

counterclockwise on the secondary fiber. The ADM continuously reads both copies of the

information received, compares them and writes the information from the path which bas

k e n designated as the p h a r y path. If the information nceived on the primary path

degrades to an unacceptable level of performance (Le. high Bit Error Rate) or disappears

as a result of a fiber cut, it simply switches to the better or altemate source and sound the

appropriate alamis. In this mode it provides "hot standby" operation.

In this thesis however, the redundancy and switching path issues are not addresseci.

Although the ADM is part of SONET, its design does not have a SONET / ATM interface

and framer. It assumes that the synchronization and clock recovery is done extemaily and

ail the received data frames have a P;LU structure. The whole design is donc in a pure

A 2.5 Gb/s CMOS Add-Drop Multiplexer for ATM University of Toronto

Chapter 2: AddDrop Multiplexer Design Page 21

ATM environment, solving the problem of the core ADM SONET component working at

2.5 Gbls.

2.2 Block Diagram

I Media Accesg Control Filtering Queuing 1

Figure 2.1 Block Diagram for ADM [l]

The idea for the ADM came fiom a paper by Madsen and Lassen [l], who imple-

mented their design in GaAs 0.8 p.m E/D MESFET technology. The high level block dia-

gram of the chip is shown in Figure 2.1. The core is performing the insertion and

extraction of ATM cells fkom the 2.5 Gb/s cell strearn while the auxiliary unit, working at

lower speeds, performs tasks like: Media Access con& (MAC), filtering and queuing.

The circuit presented in their paper was concemed only with the high speed con. A block

diagram of the core block is given in Figure 2.2.

Similar to Madsen and Lassen's design, this thesis solves the same high speed core

problem but in much cheaper 0.5 p CMOS technology. Basically the ADM chip featuns

considered in the thesis include:

1) An Input Module providing phase independent interface

2) An Add Module that inserts ATM ceils in the data stream

3) A Drop Module that extracts ATM cells

- - - -- -

* Media Access Contrul (MAC) - provides address recognition, generation and verificaîion of frame check sequences. Its @ary function is the delivery of m e s , including fiame insertion, repetition, and remwal.

A 2.5 Gbls CMOS Add-Dmp Multiplexei k r ATM University of Toronto

Chapter 2: Add-Drop Multiplexer Design Page 22

4) An Output Module that prepares ATM cells for physical transmission.

The high speed data path is 3 11.04 MHz (2.5 GWs on a 8 bit bus) and the add /

&op slow speed path is up to 77.76 MHz (622 W s on a 8 bit bus). For simplification pur-

poses and in view of packaging limitations, instead of using a 32 bit bus connection on the

&op path, a 8 bit bus is used at any extemal data co~ection of the circuit.

Input Section Add Section Omp Section Output Section

Figure 2.2 ADM Core Block Diagram [ 1 ]

2.5 Gbps 2.5 Gbps

Pipeiined Data Path

f ,

Parallei Data Path

1 1 - OAM OAM OUT

Figure 2.3 Pipehed versus Parallel Architecture

8 8

- - DROP

155 / 622 Mbps 4 8

ADD

A 2.5 GWs CMOS Add-Drop Muttiplexer for ATM University of Toronto


From the beginning a decision of whether to use a parallel or a pipeiined concept

for the logic of the circuit must be made. As seen in Figure 2.3, the pipelined architecture

assumes that the signal circulates through the pipeline as long it is necessary to penomi

the logic calculations. In the parallel structure. the calculation needs fewer clock cycles,

but it results in a significant increase in area. For the ADM it is necessary to buffer data for

at least five clock cycles. Since writing and especially reading data from a memory buffer

at this speed (3 11 .O4 MHz) is not trivial and because of area considerations. the pipelined

mode1 was chosen in this thesis.

V P l 6 VCI w

Figure 2.4 ADM Logic Chart

The easiest way to understand the design is by following a logic chart. As shown in

Figure 2.4 the staa of the incornhg data is given by the Start of Cell (SOC) signal, corre-

sponding to Universal Test and Operations Physical Layer Interface for ATM (UTOPIA)

specification.

- --

A 2.5 Gbls CMOS Add-Drop Muttiplexer for ATM ~nivérsity of Toronto

Chapter 2: Add-Orop Mulplexer Design Page 24 - - --

The k t step after a cell arrives is to check the header for possible match. This is

done by checking the VPI and VCI fields (8 + 12 and 16 bits respectively). The first deci-

sion to make depends whether or not the cell targets the local node. If its target is the local

node, then the ceil has to be stored in a bufEer and a ce11 empty flag has to be turned on.

If the cell's target is not the local node, then the cell has to be checked if it's a

empty ce1 or not. If the ceU is not empty and it doesn't target the local node, then the ce11

is transmined without any change. If the ce11 doesn't target the local node, but it is empty,

then again, a ce11 empty Bag has to be tumed on.

One last decision step is to choose if there is a local cell ready to be transmitted or

a empty ce11 is transmitted instead. This last step takes in consideration the priority of ce11

transmission relative to the network availability for that particular node. The chart, bnefly

described above, explains the basic functions of the ADM.

Clk

SOC

- Enb -

~1 1 H2 1 H3 1 Data

Figure 2.5 Receive Timing Sequence

In practice, apart fiorn Data, SOC and Clk signals there is also an Enb (Enable)

signal. The timing sequence, shom in Figure 2.5, helps to better understand the Receive

interface:

SOC is an active high signal asserted by the Physical Layer when Data contains the

first valid byte of cell.

Enb is an active low signal asserted by the ATM Layer to indicate that Data and

SOC is sampled at the end of the next cycle.

--



Clk is a synchronization clock from the ATM Layer to the Physical Layer synchco-

nizing transfers on Data.

Data byte wide data driven from Physical Layer to ATM Layer.

Since the design doesn't have a SONET fiamer, the Enb signal is not needed and

the functionality demonstration is not affected. The logic relies on the SOC signal with an

unintempted cell string.

The ADM implemented in this thesis perforrns similar functions to the GaAs ver-

sion. However, the design is built using a different architecture. The main differences are

the use of a SRAM with a FIFO behavior and a CAM as part of the logic in the chip.

In the input module, a very short (6 clock cycles) shift register pipeline is used.

The buffering of the ce11 on the add and drop side is minimal. There are no waiting time

periods, except for the initial 5 clock cycles needed to make the routing decision. A multi-

plexing of data signals is used. n i e high level function is best understood by referring to

Figure 2.6. The data Stream enters a short pipeline. The pipeline is used for decision pur-

poses only. After 5 clock cycles, the data stored in the pipeline (the header of the cell), is

compared in a Content Addressable Memory (CAM) to the local stored address, and a

decision is made. At the same tirne, the data is stored in a Ce11 Buffer, implemented as a

regular SRAM. If there is no match, and the ceil is not addressed to the local node, than

the data stored in the buffer is discarded. The data is directed to the appropriate buffer

through a demux. This section represents the Drop Section.

In the Add Section, the buffering of the ce11 is done in a spiit SRAM. The reason

for using this approach is that it is fairly easy to &te with high speed in a memory; al l

depenâing on sizing of the Write Buffers as done in the Drop Section, but it is diflicult to

achieve the same speed when reading h m memory. The Add Section also contains a

Empty Cell Generator (KG), instead of storing a empty cell, as was done in the first case.


Chapter 2: Add-Drop Muitiplexer Design Page 26

OUT -'d

8

Figure 2.6 ADM High Level Architecture

2.3.1 Drop Section

As mentioned earlier, data that arrives at the input enters a short pipeline formed

by six D flip-flops @FF-PIPE) and in the same tirne is written in a SRAM (DROP-A or

DROP-B). The SRAM storage element is 53 rows long and 8 columns wide. This size

enables the storage of one single ATM cell and can be made very fast.

The writing of the SRAM is very simple: the 8 bit data bus is coupled to the col-

umn lines of the SRAM through the tristate elements T K A and T K B and directed to

the appropriate storage element by the DROP-DEMUX. The row decoder of the SRAM is

formed by a shift register made of 53 DFF. In fact, for a complete separation between the

write and read, the memory is designed using dual rails cells, one pair for each operation.

- . -. . . - -. . . - - - - - - . . . . -

A 2.5 Gbis CMOS Add-Drop MuJtiplexer for ATM University of Toronto


In this way, data can be read and written in the same time and no wait period is needed

between the two taslcs. As soon as the SOC signal arrives, it is directed to the empty

SRAM by SOC-DEMUX, where it enters the appropriate shift register. If both memory

elements are full, nothing is written, due to the presence of the tristate kiffers T K A and

TRI-B.

At each clock cycle another row in the SRAM is selected by the output of the next

DFF, and in the same tirne another set of data activates the columns of the memory. A h r

53 dock cycles, the whole ATM ce11 is stored. As mentioned before, data that arrives at

the input enters a short pipeline formed by six D Rip-flops (DE-PIPE) and in the same

time is written in a SRAM (DROP-A or DROP-B). The SRAM storage element is 53

rows long and 8 columns wide. This size enables the storage of one single ATM ce11 and

can be made very fast.

The reading process is sirnilac selecting the other rail of each cell, reading is done

by sending a signal (In2-A or In2-B) through a shift ngister decoder. In this case, the

working frequency is much lower and the DFFs can be scaled down. The data nad is

muxed to the drop output by the selection donc in the DROP-MUX. Further, data is sepa-

rated from the output by a tristate buffer TRI_DROR The detailed block diagram is shown

in Figure 2.7.

A 2.5 Gb/s CMOS AdbDrop MuMplexer for ATM University of Toronto

.


OUT

soc

Figure 2.7 Drop Section


Chapter 2: Adû-Drop Muitiplexer Design Page 29

An in deptb explanation of all command signals is given startins in reverse order.

The TRI-DROP tristate buffer is activated by DropOut signal. The value of this signal

depends on the state of the two SRAMs (DROP-A and DROP-B), the read signal (Out2A

and Out2-B) and the CeMq signal which is received every time a ATM cell can be

dropped to the local node.

The flowchart in Figure 2.8 reads as follows: the START is given by a Ce11 Request

signal. If DROP-A is empty (SPA - O) then it is checked if DROP-B is empty. If it is also

empty (SpB - O), then no data should be sent to the output and the tristate buffer

TRI-DROP has the output at high impedance.

SPA, SpB 1 -> full O -> empty

Fi- 2.8 TRI-DROP Logic Chart

If the DROP-A is full (SPA - l), then the nad signal Out2-A is checked. A

Out2-A - 1 signal means that DROP-A is empty oust hished the read process) and

TRI-DROP should have the output at high impedance. If OutZ-A - O, then it is checked if

Out2-B - 1. If it is one, that means that DROP-B is empty and the output impedance

A 2.5 Gb/s CMOS AddOrop Multiplexer foi ATM University of Toronto


should be high as well. Finaily, if both Out2-A - O and Out2-B - O, TRI-DROP should

drive the DRûP output and data should be sent outside.

The same judgement as above applies in the case SpB - 1. The functional behavior

just describecl above is put in equations below:

OPEN - SA.E - S A + S B

SA and SB are SpA and SpB, OA and OB are Out2-A and Out2-B respectively.

But the useful signai is STOP-OU:

STOP OU - ( O A + O B ) . ( S A + S B ) - O A + O B + S A + S B - The implementation of this behavior is shown in Figure 2.9 in pater detail.

Figure 2.9 TRI-DROP Implementation

A 2.5 Gbls CMOS Add-Drop Muttiplexer for ATM University of Toronto

Chapter 2: Add-Orop Mulüplexer Design Page 31

The DROP-MUX is selected by MuxDropSelect signal. The value of the signal is

dependent on SpA and SpB (which indicate if DROP-A or DROP-B are full or not), on

LAST signal (which indicate the last written SRAM: LAST - O meaning DROP-A was

written last and LAST - 1 meaning DROP-B was wRtten last), on Read-A and Read-B

(which indicate if there is an ongoing reading action done on any SRAM: a "1" means

reading in progress and a "O" means no reading in progress) and finally on CellReq signal.

The functionality is best understood following the chart in Figure 2.10. Similar to

the previous chart, the star& is given by the amival of the CellReq signal. Then it is checked

if DROP-A is full or not by analyzing SPA. If DROP-A is empty (SPA - O), then

DROP-B is checked through SpB. If DROP-B is also empty (SpB - O), thzn the STOP-R

signal is activated. This signal blocks any change in MuxDropSelect signai.

Figure 2.10 DROP-MUX Logic Chart

If DROP-A is full (SPA - l), then it is checked if DROP-B is full. If it is empty

(SpB - O), then it is checked if thete is any reading in progress done on DROP-A. If a

reading is in progress (Read-A - l), then again STOP-R signal is activated. Otherwise if

Read-A - O, DROP-A SRAM is selected and downloading c m start.

If DROP-A and DROP-B are full, LAST signal is evaluated. If LAST - 1 that

means that DROP-B was Wntten last, so DROP-A must be nad nrst DROP-A is selected

A 2.5 GWs CMOS Add-Drop Mulüplexer for ATM University of Toronto


if there is no reading done in progress. If LAST = O that means that DROP-A was written

last, so DROP-B must be read fust Similar to the reading of DROP-A, Read-B signal is

evaluated. If Read-B - 1, a read process on DROP-B is in progress so STOP-R signai is

activated. Reversed, if Read-B - O, DROP-B is selected and the downloading cm start.

The final possibility left is when DROP-A is empty but DROP-B is full. In this

case again Read-B signal is evaluated. If Read-B - 1, STOP-R signal is activated. Other-

wise, if Read-B - O, DROP-B is selected, and the downloading cm start.

The functional behavior just described above is put in equations below, where SA

and SB are SPA and SpB and RA and RB are Read-A and Read-B respectively.

SelR - A = S A - ~ - ~ + S A - S B . L A S T ~ = ~ + R A + ( ~ + L A s T )

The useful signal is STOP-R:

STOP - R - (SA +SB) [RA (SB -SA LAST)]. RB- (SA* SB LAST) [ -1 The implementation of this func tion is illustrated in Figure 2.1 1.

-O important signals are generated: In2-A and 1.2-B. These are the read signals

that act as inputs for the shift register decoder when reading the two SRAMs, DROP-A

and DROPB.

Read-A and Read-B are generated by two SR Bip-fiops which have 1112-A and

ûut2-A for Read-A and IaZ-B and Out2-B for Read_B as inputs respectively. 0119-A

and Out2-B are the signals at the output of the read shift register for DROP-A and

DROP-B.

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Chapter 2:-Add-Drop Muitiplexer Design Page 33

The DROP-DEMUX is selected by WrSel (Write Select) signal. The value of the

signal is dependent on SpA and SpB (which indicate if DROP-A or DROP-B are full or

not) and on SOC (Start Of Cell) signal.

Figure 2.1 1 DROP-MUX Implementation

The functionality is best understood from the chart in Figure 2.12. The STmT sig-

nal is given when SOC signal arrives. Fit DROP-A is checked. If it is empty, then it is

selected and the writing of DROP-A begins.

Figure 2.12 DROP-DEMUX Logic Chart

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Chapter 2: Add-Drop Mukiplexer Design Page 34

If DROP-A is fiil, DROP-B is checked. If it is empty, then it is selected and the

writing of DROP-B begins. Otherwise, STOP signal is active.

The fbnctional behavior just descnbed above is put in equations below, where SA and SB

are SpA and SpB.

Like before, STOP-W is more useful.

STOP W = SA -SB STOP W = SA* SB

The implementation of this function is shown in Figure 2.13.

I STOP-W TRI-A Y+

Figure 2.13 DROP-DEMUX Implementation

As seen in Figure 2.7, WrSel signal is also used for the selection in

SOCOCDEMUX. The generation of SpA and SpB signals which signalize if the DROP-A

and DROP-B are hill or not, is done by reading the OutA and OuQ-A signals (Out-B

and Out2-B respectively). The Out-A and Out2-A are the output signals of the shift ngis-

ter decoder: Out-A is for the write process and Oud-A is for the nad process. Since the

wnte process is only meaningful if the ATM cell is addnssing the local node and there is a

match for the address in the header, the Out-A and OutB signals are ANI)-ed with a

BLOCK signal.



The generation of the BLOCK signal is illustrated in Figure 2.14 and is explaimd

below. If any of the two SRAM buffers is empty, then, when SOC signal &es, the SpAv

(Space Available) is set to one. SpAv = 1 means that if there is a match in the CAM, the

cell can be stored in the empty buffer.

If both DROP-A and DROP-B buffers are full, SpAv is met to zero at the shth

clock cycle by CNT-6 and does not change state at the next &val of SOC signal. In this

case, if there is a match in the CAM, the ce11 can not be stored in the SRAM buffer and a

CeilLost signal is generated.

The BLOCK SR Bip-Bop is reseted in each ATM cycle at the fourth clock cycle by

CNT-4. If SpAv - 1 and if there is a match in the CAM, then BLOCK is set to one and the

ce11 that is king written in the SRAM buffer is a valid ATM cell.

Figure 2.14 BLOCK Signal Generation

23.2 Add Section

The adding of cells process can be explained fkom the schernatic shown in Figure

2.15. After the data exits the input bufEer pipeline, it enters the MAIN-MüX. If the ATM

cell's destination was not the local node and if it is not an empty cell, then it won't be

altered ami it passes unobsûucted through the MUX

A 2.5 Gb/s CMOS Acîd-Drop Muitiplexer for ATM University of Tomnto


If the cell is empty or there is a match in the CAM, then, the decision has to be

taken if an empty cell or a loaded celî is inserted. The empty cell is created by an Empty

Ce11 Generator and the loaded ce11 is obtained by downloading the data fiom the Add

SRAM buffer.

The Add SRAM buffer cm hold one ATM celî and the buffer is split in four sec-

tions. The reason of splitting the buffer is to increase the reading speed. It is easy to write

with high speed in a memory, since the M t e bugen cm be made easily powemil without

a big area penalty. However, reading is done by sensing the stored value in the memory

cell. Since the cells in a memory are made purposely small (the transistors are minimum

size), the reading process is slow. One way of increasing the speed is reading a split mem-

ory by scanning each column in a ring fashion. Data is presented on the bit lines of each

column and the ADD-MUX is reading it every fourth clock cycle.

A more detailed explmation of al1 cornrnand signals is given below. The

MAIN-MUX selection is dependent on the Match and Empty signals. These signals are

generated in the CAM and indicate if there was a match in the header (VPI and VCI fields)

of the ATM ce11 or if the ATM ce11 is empty. In any of these cases, MAIN-MUX switches

the input and data from AUX-MUX is read instead.

The AUX-MUX selection is dependent on CellAv (Ce11 Available in the ADD

SRAM buffer) and on STAT input. The input of AUX-MüX can be toggled ktween the

Empty Ce11 Generator (KG) and the ADD-MW output. The last one inserts a loaded

ATM cell stored kom the local node.

CellAv signal hdicates if the ADD buffer is empty or not. A CellAv 1 means that

data (ATM ceil) is waiting iransrnission in the ADD buffer. CeWv is obtained by reading

the output of the shift registers used in writing and reading h m the ADD buffer. The read

and write process of the ADD buffer, uses the same type of shift register decoder, similar

to the DROP buffer, having the DFFs scded dom.

A 2.5 Obis CMOS Add-Drop Muitiplexer for ATM University of Toronto

STAT SOC-Add ADD

CWI CLK4- - 4

MUX

rd-.rld MaM

QK4

CAM wadw & -- 5 5 - Figure 2.15 Add Section

-%-D OUT

Chapter 2: Add-Drop Multipfexer Design Page 38 - --

STAT signal is extemal and inhibits the ATM cell insertion even if it is waiting in

the ADD buffer. If STAT = 0, then a empty ceil is inserted unconditionally. Adding this

signal enables statistical multiplexing. In a ATM network Quality of Service (QoS) is

guaranteed. Transmission of cells, therefore, depends on all participants to the traffic. If

the QoS negotiated at the beginning of transmission is higher for other participants in

cornparison with the local node, then, local node data cells is delayed.

Similar to the DROP SRAM, cells in ADD SRAM are dual rail cells. The write

shift register decoder receives as an input a AND-ed signal of: CeiiAv, wr-add and

SOCAdd. wr-add is a signal that indicates if the ADD buffer is king written or not.

wr-add - 1 means that the write process is active.

The read shift register receives as an input a AND-ed signal of: STAT, CellAv,

rd-add and CNT-6. rd-add is a signai that indicates if the ADD buffer is being nad or not.

rd-add = 1 meaning a read process is active.

2.4 HDL Functional Verification

1 HDL Test Harness

I T

Stimulus Output Vectors Vectors

Test Bench 8 . - w ~ œ ~ ~ œ ~ ~ ~ ~ œ œ 1 œ * - œ ~ 1 ~ œ ~ ~ œ I - ~ ~ ~ m œ w * ~ I ~ œ ~ ~ * * - - - œ ~ œ * œ e 1 ;

Fi- 2.16 Simulation Stnictun [6]

To ver@ the functionality of the whole chip, a HDL mode1 was developed. The

mode1 used a combination of structural and behavioral description. The logic of the chip

as desmbtd in Section 2.3 on page 23 was implemented in a structural fashion. Behav-

iota1 description was used for the CAM, SRAM, MUX and DEMUX. Al1 the parts were

A 2.5 W s CMOS AdckDrop Multiplexer for ATM University of Toronto

Chapter 2: AdcCDrop Multiplexer Design Page 39

then connected together using Synopsys Graphical Environment (SGE). A high level func-

tional simulation was then performed. A test structure similar to the one descnbed in [6]

was used and is illustrated in Figure 2.16. The HDL test structure is composed of the HDL

chip model (Device Under Test - DUT) and the Test Bench which consists of a stimulus

generator (Waveform Generator), a stimulus monitor (Monitor) and the comparison block

(Compare). The DUT and the Test Bench are connected in a structure called Test Hamess.

The test procedure consists of the comparison between the data vectors generated

by the Wavefom Generator with the data that is the output of the DUT. If any discrepancy

between the output values and the expected values is encountered duMg the testing, an

error message is issued. Since the ADM has a 8 bit bus structure, in the HDL model a stan-

dard bus representation is used: IN[7:0] for the 8 bit input bus, OUT[7:0] for the 8 bit out-

put bus, DR[7:0] for the 8 bit drop bus and AD[7:0] for the 8 bit add bus.

ADM Simulation

II Figure 2.17 HDL Non Event Behavior I To have a test case as close as possible to reality, at the input IN[7:0], a random

data pattern is presented by the Waveform Generator in the Test Bench. The data is shifted

through the chip and after 6 clock cycles it arrives at the OUT[7:0] output pins. No pro-

cessing of &ta is done. This behavior is shown in figure 2.17. Data at the input / output

bus is in hex.

A 2.5 Gbfs CMOS A&Drop Muitiplexer for AATM University of Toronto


ûccasionally, the data in the header (the first 5 bytes of data after a SOC signal

arrives), matches the header address stored in the CAM. The t r i gge~g event is a 1 on the

MATCH b e (see Figure 2.7). When this happens, the input data is stored in the DROP

SRAM (assuming that at least one of the two DROP SRAMs is empty) and if vaîid data is

stored in the ADD SRAM it is presented at the output of the chip, replacing the input data.

One of these moments is illustrated in Figure 2.18. The upper part of the figure shows a

sequence when an empty cell was detected. After the celi stored in ADD SRAM is sent to

the output, a new ceil is added. This new ceîi stored in the ADD SRAM is showed to be

sent to the output (the lower part), in a new sequence, this time following a match. Starting

with the 6" clock cycle, the stored data is sent to the output, replacing the input data.

kDM Simulation

Figure 2.18 HDL Initial Match Sequence

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Chapter 2: Adô-Orop Multiplexer Design Page 41

The cell that triggered the MATCH signal is stored in one of the empty SRAMs. At

the next SOC the stored celi starts the downioading process and data is presented at the

drop bus, DR[7:0] as illustrated in Figure 2.19. "C" shows the first "dropped" byte, having

the same value as the byte at the input bus in previously ilîusûated sequence in Figure

2.18. The data is "dropped" using the lower ( C m ) fkquency used by the local node. The

conditions chosen for the simulation were so that a CELLREQ signal was present and the

"dropping" of the stored cell could proceed immediately. Also another assumption in this

case was that data was available in the ADD SRAM and the data was "added" in the high

speed bus. Afier the "adding" process finished, new data replaced the content of the ADD

SRAM through AD[7:0] input. "B" is showing the start of the "adding" process. " A

points to the last byte "added" fiom the ADD SRAM. M e r the last "added" byte, the

behavior to the non event sequence shown Figure

ADM Simufation I1iPim ImMMydTiAno IYIrOina

II Figure 2.19 HDL h o p and Add Sequence after Match

The comparison between the expected vector values and the DUT output vectors

was performed for 100 matched cens. No ciifference was noticed and no error message

was issued. It was concluded that the ADM design passed the finctional simulation test.

A 2.5 GWs CM06 Add-Orop Multiplexer for ATM University of Toronto

Chapter 2: Add-Drop Muitiplexer Design Page 42 - - - - p. . .

2.5 Building Blocks Design

The next step was to design ali the constituent building blocks individually starhg

with the basic DFF. HSPICE was used in the simulation of various components. Although

the specifications require that the chip is working at 3 1 1 MHz, to take into account process

variations and parasitic loads, all the constituent blocks were tested at a higher ftequencyL.

As a "rule of thumb", the main concem was to obtain rise and fall tirnes of no more than

0.3 ns across any high speed path of the design to account for setup and hold time.

26.1 Input Buffer

As seen in Figure 2.7 and Figure 2. L5 the ADM has multiple clock domains. The

high speed path enters the 8 bit bus, continues through the input buffer pipeline and is

shifted out by the MAIN-MUX and output pins. The path is highlighted in Figure 2.20.

This path works at high fkquency and al1 constituent elernents are designed to work at

31 1 MHz, over a temperature range h m 25 'C to 125 'C and at supply voltages in a

range fkom 3.3 V io 5.5 V, thus insuring functionality in any real world conditions.

Figure 2.20 High Speed Path

* All bl& were tested using a 500 MHz cl&

A 2.5 Gbls CMOS AddDrop Muliplexer for ATM University of Toronto


The important components in this path are the Input Buffer, a pipeline, six D Bip-

flops deep and 8 bits wide. Since the 0.5 prn CMOS technology available at the design

time had no available D flip-flops working at the required speed, very fast, dynamic D flip-

fiops were developed. The design of choice was the True Single Phase Clock PSPC)

dynarnic architecture [2].

TSPC combines the advantages of a dynarnic logic architecture, a simple structure

with fewer transistors, and a low load on the dock tree. If designed carefully, it is a perfect

solution for high frequency input buffers. Some of the TSPC design prhciples are

explained in Appendix A. One ùrawback of the classical design is the presence of spikes at

th3 output of the D flip-flop on the positive edge of the clock. That might trigger the sys-

tem into a wrong state and has to be corrected for a safe functionality. The other motiva-

tion behind the use of a glitch free TSPC is the reduction in power associated with the

fiequent switching of the DFF.

The solution is to add an additional transistor (MN4) in the output stage, dnven by

the inverted interna1 node X [3]. This prevents the false drop in the output voltage, due to

the fact that intemal node Y can not be discharged instantly. The schematic, layout and

waveforms are presented in Figure 2.2 1 [5].

Adding the MN4 transistor reduces the operating speed by IO%, but a glitch fm

function is achieved. For consistent sizing critena MP1 and MPSl change places with no

change of functionality. Another reason for moving clocked transistors close to VDD and

GND is due to the fact that floating transistors present less load and higher speed can be

achieved [3]. As seen in the layout of the General Purpose TSPC, the height of the DFF is

identical with the height of regular library cells, so it could be used for future designs.

Throughout the ADM chip, depending on the clock domain requirements, the transistor

sizes were scaled down or up, but the same basic TSPC architecture was used. In addition

TSPC with asynchronous reset and set were designed and shown together with the layouts

and simulated waveforms in Figure 2.22 and Figure 2.23.

A 2.5 Gbls CMOS AdbDrop Multiplexer for ATM University of Toronto

Chapter 2: Add-Drop Muîtiplexer Design Page 44

VDD

GND

Figure 2.2 1 Generic TSPC D Fiip Flop [3]

a) Schematic

b) Layout

c) Simulation Wavefonns

A 2.5 Gbls CM06 Add-Drop Multiplexer for ATM University of Toronto


Figure 2.22 D Fiip Flop TSPC with Reset

a) Schematic

b) layout

c) Simulation Waveforms

CLK

IN

RST

A 2.5 Gbls CMOS Add-Drop Muitiplexer for ATM University of Toronto

Chapter 2: Add-Drop Mulüplexer Design Page 46

GND

Figure 2.23 D Flip Fiop TSPC with Set

a) Schematic

b) Layout

c) Simulation Wavefonns

A 2.5 Gb/s CMOS AWDrop Mulaplexer for ATM University of Toronto


The ADM uses two types of counters: a counter to 5 and a counter to 53. Both

counters have to work at 3 11 MHz. The design of choice is the synchronous counter. The

implementation of a synchronous counter starts with writing the input equations of the

flip-flops, in this case the DFF. Three DFF are needed to realize the count to 5 counter. - -

DA = QA Qc

The schematic used to implement these equations is shown in Figure 2.24.

Figure 2.24 Synchronous Counter to 5

Since for the counter to 53, six DFFs are needed, a considerable amount of over-

head is required, slowing down the circuit. A shpler design architecture has to be used.

The solution is to use the Pseudo Random Binary Sequence (PRBS) counter. This cm be

used because the counting sequence is not important. After 53 clock cycles, the state can

be decoded and used. The principie is shown in Figure 2.25 and requins to XOR the out-

pu t~ of the first and the last D E The XOR output is used as an input for the h t DFF. In

this way a 2N States random counter is obtained, with N king the number of DFFs used.

In the particular case of the ADM, the countet is started by the SOC signai and is nseted

aftet 53 clock cycles.

A 2.5 Gbls CMOS Add-Drop Muîtiplexer for ATM University of Toronto


Figure 2.25 PRBS Principle

The schematic layout and simulation results are shown in Figure 2.26 and the

decoded values of the PRBS counter are given in Table 2.1. A very fast response tirne

(-0.6 ns) is obtained.

Figure 2.26 PRBS Counter to 53

a) Schematic

b) Layout


Chapter 2: Add-Orop Multiplexer Design Page 49

O-. ... m . . m..

6 -. . . 0 . .

-. . W . .

O-.

L .. . . O..

*.. . l a.. b .. . .

CLK

SOC

OUT

Figure 2.27 PRBS Counter to 53 Simulation Waveforms

a) 53 Clock cycles counting sequence

b) End of counting sequence zoomed view

Table 2.1 PRBS Decoded Values

~ C L K ~ ~ e a i 1 46 + Q11 Obs. 1

A 2.5 Gb/s CMOS Add-Drop Multiplexer lor ATM University of Toronto


2.53 CAM

Apart from flip-flops and counters, the CAM is another key component for the

ADM. At the 5" clock cycle, the value loaded in the input buffer pipeline is compared

with the value initially stored in the CAM cells. The first 40 bits of the ATM cell represent

the header and contain information related to the virtual path and destination of the ceil. If

there is a match, then the cell's destination is the local node and the ceil has to be dom-

loaded. In the same time the header is checked to see if the ce11 is canying a valid payload.

In any such cases, a signal is generated. To rninimize delays, the signal has to be generated

at the working frequency of 3 1 1 MHz.

VDD

VDO

7 OUT

r ! ! 1 GND 1 1

Figure 2.28 CAM Rinciple

In principle in a CAM, the value stored in each ceil, is XOR-ed with a new input

value. If there is a match for ail cells, a 44MATCH signal is genemteû. Otherwise, the

default value remains stable. There are two ways of perfonniag the cornparison: the ht,

shown in Figun 2.28 a) is by connccting the evaluation transistors in senes. If there is a

match (all bit cornparisons are tme), VDD is measund at the output. The second way,

A 2.5 Gbls CMOS Add-Drop Muhiplexer for ATM University of Toronto

Chapter 2: Add-Drap Mutiplexer Design Page 51

shown in Figure 2.28 b), is to comect a l l transistors in parallel, pulling down a common

line. In precharge phase the h e is pulled up to VDD. In the evaluation phase, if there is

any mismatch in the CAM, the common output line is pulled down. Otherwise a MATCH

signal is generated.

There are advantages and disadvantages for both solutions. In case a) the process is

very slow, a reduced number of transistors cm be connected in series, so frequent buffer-

ing is necessary if long lines are involved. As an advantage, this solution presents a lower

load for the clock signal and is therefore preferred when designing large CAMs. In case b)

the design is very fast and does not need any type of buffering even for an increased num-

ber of transistors (there is no voltage drop due to VJ. The disadvantage is that a large load

line has to be precharged at each clock cycle. Since the CAM used in the ADM is rather

small and the speed is critical, the last solution was used.

The scheniatic and layout of a CAM ce11 is show in Figure 2.29. TPP and TNE

are the clocked transistors used for precharge and evaluation. CN'ï-5 goes high at the 5'

dock cycle, starting with SOC. TP5 helps in the precharge phase to pull up the match line

and TN5 accelerates the pull down of the interna1 evaluation node. TS is minimum size

and discharges node X in the precharge phase, avoiding false readings. The SR latch is the

storage element of the CAM cell. Together with TX and 'iX it creates a XOR element

between the stored value (Q and a and the bit Iine value that is coming fiom the input

buffer pipeline, X and X.

The CAM cells are grouped on eight rows in five cells formation p u h g down a

common MATCH hie. All the eight partial MATCH lines are AND-ed and finaily a

MATCH signal is generated. In Figure 2.29 the simulation of the CAM is also shown.



SET RESR

+ MATCH

Figure 2.29 CAM Match Ceil

a) Schematic

b) Layout

c) Simulation Wavefoms

-- -- - - --

A 2.5 GWs CMOS AddDrop Multiplexer for ATM University of Toronto

Chapter 2: Add-Drop Multiplexar Design Page 53 -- -

The other signal that has to be generated in the CAM is the "EMPTY" signal, hdi-

cating if the ATM ceU in empty or not. Table 2.2 [4] gives the field values dependhg on

the position in the header for an unassigned ceil ("A" indicates Uiat the bit is used by

appropriate ATM-layer function (GFC) and "x" is a don't care bit):

Table 2.2 CeU Header Values [4]

Since the values that are tested are zeros, a simpler schematic is used. Figure 2.31

shows the schematic and the layout for a Ceii Empty decision block. Five such blocks are

used and the outputs are AND-ed generating a "EMPrY" signal that is used by the ADM

logic. The functionality of such a block is simple: during the waiting phase, the PMOS

me Unassigned ce11

transistors are keeping the NOR inputs high, so OUT is low. hiring the evaluation phase

the NMOS pass transistors are conducting and the PMOS are cut off. If al1 the NAND

inputs are hi@ (0, negated samplcd values are used), then the gate output is low. Having

Octet 1 0 + 7 AAAAOOOO

both inputs low, the NOR gate output is high, signaling a empty cell.

VDD

A AT,,

Octet 2 8 4 5 00000000

Out

VDD

Octet 3 16 a 2 3 00000000

Figure 2.30 CAM Empty Celi Schematic

- - - -

A 2.5 GWs CMOS AddDrop Muîtiplexei for ATM unive& of Toronto

Octet 4 24131 OOOOxxxO

Octet 5 HEC valid code


OUT

CLK

SOC

EMPTY

Figure 2.3 1 CAM Empty Ceil

a) Layout

b) Simulation Wavefonns

The buf fe~g strategy used in ADM design uses high speed SRAMs. The basic

memory ceil used in both Add and Drop part, is shown in Figure 2.32. It uses 8 transistors:

two extra transistors (beside the six transistor classical SRAM architecture) are used to

enable simultaneous read and &te of each ceil. The read - write cycle simulation for a

memory ceil is also shown in Figure 2.32.

A 2.5 Gb/s CMOS AddDrop Multiplexer for ATM University of Toronto


CLK

IN (decoder)

MBIT - MBIT

Figure 2.32 SRAM Cell

a) Schernatic

b) Layout

c) Simulation Waveforms

One of the key elements in achieving the hi@ speed at nad and write is due to the

row (word) decoder. The schematic used is presented in Figure 2.33 and is basically a 53

DFF shift register. SOC, or signals derived h m SOC are used at the input of the shift reg-

- ister. Since for rad or Wnte in the Add and Drop sections, various time domains are u d ,

a way of capairing n m w signds has to be developed. One simple solution is to use at the

input of the decoder a RS latch. The hctionality can be explaineci as foliows: when a

A 2.5 Obis CMOS AddDrop Muttiplexer far ATM University of Toronto

Chapter 2: AdckDrop Multiplexer Design Page 56 - --

input signal is present, the RS latch changes state and output Q goes high. At the next

clock cycle, DFF sees high at the input and toggles the output. This in hm resets the RS

latch and Q is low. So regardless of how narrow the input is, it is caught by this architec-

ture. The outputs of the DFFs are then used to select word lines in the SRAM at each clock

cycle. The NAND gaies are used to eliminate the overlapping present in such desip when

two adjacent rows switch.

Figure 2.33 SRAM Decoder

Drop SRAM

The Drop SRAM unit has a classical structure. It can hold one single ATM cell and

is therefore 8 cells wide and 53 cells high, for a total storage capacity of 424 bits. In the

ADM design, two such SRAM units are used on the Drop side. This number could be

scaleâ up giving the ADM a p a t e r buffering capability. A bigger biffer means fewer Ce11

Lost signals. The writing of a cell takes around 1.4 ns, when measuring fiom clock edge

and 0.3 ns from the row selection. The reading takes longer, but on the Drop side, where

the reading takes place. the maximum expected fiequency is four times lower when corn-

pand to the writing fquency.

Beside carefully choosing the transistors sizes, a particular layout feature helps

speeding up the read / write process. As seen in Figure 2.34, the layout of the h o p SRAM

could be done in two ways: the fust approach (a), would give a very long, but nanow

memory column. This would be very easy to layout, but would have the disadvantage of a

A 2 5 Ob/$ CMOS Add-Drop Multiplexer for ATM University of Toronto

Chapter 2: AdbDrop Multiplexer Design Page 57

wide spread in the parasitic capacitive and resistive load, fiom the ce11 closest to the read /

write block to the one furthest away. The spread, as simulated would be around 0.4 ns, an

unacceptable value for the frequency it is supposed to work. The second approach (b), the

one used in the ADM design, is the "broken column". The 53 rows high column is broken

in half. The two resulting columns (27 rows high each), have the colurnns C O M ~ C ~ ~

together. Although the parasitic capacitive load remains constant, the nsistive load is

halved compared to previous case. 0.3 ns maximum delay is obtained using this approach.

In the precharge phase of the SRAM, the colurnns bit and are shorted together

and pulled up to half VDD. This insures a very fast sensing in the evaluation phase.

Rea I rite &

8 cells

Figure 2.34 Drop SRAM Architecture

Add SRAM

The Add SRAM can hold one single ATM ce11 and is divided in four. Each column

is 14 rows high and 8 bits wide for a total of 112 bits as shown in Figure 2.35. Each col-

umn has a separate read and write block. The row decoder is comrnon for al l the columns

and has the same design as the one in the Drop SRAM. The reading and writing process

are similac at the positive edge of the clock, the decoder is selecting the same row in a l l

A 2.5 GWs CM06 Add-Drop MuJtiplexer for ATM University of Toronto

Chapter 2: Add-Drop Muitiplexer Design Page 58 -- -- - - -

four columns (A, B, C, D). The information present in the cells activates al l the bit and

intemal columns and is sensed by the appropriate read or write block. The Add MUX

scans a l l read outputs with a frequency four times higher than the fiequency used by the

row decoder. This way in one "decoder clock cycle" there are four "MüX clock cycles"

and a very high output frequency cm be achieved.

AD0 DEMUX L!h

8 œlls '7'

AD0 MUX x Figure 2.35 Add SRAM Architecture

2 MlJX and DEMUX

The MUX and DEMUX used in the h o p section is show in Figure 2.36 and has a

classical 2: 1 architecture. The same MUX architecture is also used in the MUXeMAIN

and MUX-AUX blocks.

- -- -- - -- - -

A 2.5 ~ b l s CMOS A C W D ~ O ~ Mulaplexer for ATM University of Tomnto

Chapter 2: AddDrop Mulaplexer Design Page 59

DEMUX MUX

IN IN1 OUT1 I

OUT IN2 I

SET d OUT2 SET

Figure 2.36 Classical MUX and DEMUX

For the Add section the design has to be very fast since the output kquency is 3 11

MHz. A special type 4 1 MUX / DEMUX was developed. The selection decision is identi-

cal for the MCrX and for the DEMUX, the only difference king how the pass transistors

are comected: in the MUX al1 the pass transistors outputs are shorted together and in the

DEMUX ai i the correspondent inputs are shorted. The MUX design consists of a 4 bit ring

counter made with 4 DFFs and a 3 input NOR gate, a RS latch, a PRBS synchronous

counter to 53 and 4 x 8 pairs of pass transistors, as seen in Figure 2.37. The design works

as descnbed below: at staaing sequence, the RS latch receives a reset signal and Q goes

low, resetting ail DFFs. When SOC arrives, Q goes high and the ring and the PRBS

counter are starting the counting sequence. Mer 4 clock cycles, the input of the ring

counter is forced to high and the counting sequence is started again. In this way each of the

4 groups of 8 pass transistors are selected in sequence. The NAND gates C O M ~ C ~ G ~ to the

output of the DFFs are insuring no overlapping is present. This process npeats itself until

the 53"' dock cycle is reached. Then the PRBS generatcs an impulse that resets the RS

latch and implicitly the ring counter. The process restarts again when a new SOC arrives.

The delay introduced by this design is extremely small: fkom the input to the out-

put of the MUX (DEMUX), the= is only the delay introduced by one pass transistor.

Using this approach the multiplexing and demultiplexing ratio c m be increased, without a

A 2.5 Gbfs CMOS AddDrop Multiplexer for ATM University of Toronto

Chapter 2: Add-Drop Muîtiplexer Design Page 60

CLK

O r t , F"-'-..""...''~.....-~-.----t , E ..--.---- **.-.* -...- * --.,. **..; , ................................ t , ....-..-S.---. 6 ----..- "- .---.- *,

L ,&:*-** .-..... i *.-.L--.-.-.... l mm *m.,m * * O *..O* * m . * * .O

*O- , * t t n s C L t M l o...

IN-A

OUT

SELECT-A

m u

Figure 2.37 Add Section MUX

a) Schematic b) Layout c) Simulation Wavefoms

A 2.5 Obis CMOS Add-Orop Multiplexer for ATM University of Toronto


2.5.6 ECG

As shown at the beginnhg of the chapter, a ernpty celi could be stored in a buffet

and read as many times as needed. Table 2.3 inclkates the structure of a empty ATM ceil.

By analyzing the pattern of the values some simple equations could be written.

Table 2.3 Empty Ce11 Pattern

The sequence of ones and zeros suggests a very simple way of generating a empty

cell. So instead of storing the cell, the ce11 is generated at each new SOC arrival. The

implemented structure is presented in Figure 2.38. The functioaing is describeci below: at

the 4' clock cycle after SOC arrives, a 1 is generated and is assigned to bit Qo. Next clock

cycle, a 1 is generated at the output of the 5' DFF and is assigned to bit Q4, Q1 and Q6. At

the 6' clock cycle, a 1 is generated at the output of the 6~ DFF and it is assigned to bit Q3

and Qg. In the same time this asserted 1 is applied at the input of the 6' DFF, keeping QI

and Qg at logic level high. This condition remahs stable until a new SOC arrives. The

DFF resets and the sequence of events repeats itself. A very simple and very fast state

machine is realized.

A 2.5 GWs CMOS AWDrop Mulüplexer for ATM University of Toronto


SOC

................. ..........................*.................-

. . . ; ............ : .... .;.. ................. .:. ............... ; soc 1 - = - 1 - 1 -b

....... ..... .... O L * ,..... '....",.'."'. .....,.......... " .....................- . m . . - ............ ............ : .....: ........ 1 ........................... 1 03 r * ................. =k% am. o u a s . o n

.....*... L s m a . o u r . * c I L . * l

8 . . o u * o . a m

Figure 2.38 Empty CeU Generator

a) Schematic b) Layout c) Simulation Waveforms

When connected together, the whole design (shown in Figure 2.39) was too big to

be simulated using HSPICE or AWSIM'. To ver@ how the whole design behaves at 31 1

W. a critical path was chosen and sirnulateci using HSPICE. The path has to k part of

the main data s t m m i and has to have the highest load.

* An in-bouse analog simulator for digitai circuits developed by Professor D. Lewis.

A 2.5 Gbls CMOS Add-Drop Muitiplexer for ATM University of Toronto

Chapter 2: AddDrop Multiplexer Design Page 63

Figure 2.39 ADM Schematic & Cntical Path

A 2.5 Gbls CMOS Add-Drop Mulaplexer for ATM University of Toronto

Chapter 2: Add-Drop Mulaplexer Design Page 64

The choices investigated were the SOC to SOCOUT path and the path from IN[8]

to OUT[8]. These choices were selected because they presented the highest load at the

input of the signal (maximum number of transistor gates), crossed the maximum number

of sequential gates fiom input to output and were part of the high speed data stream, work-

ing at 3 1 1 MHz. As seen in Figure 2.40 the delay on the two analyzed cases is almost

identical and equal to 1.1 ns.

Figure 2.40 Critical Path Simulation

9 - . 9 n i r r i r l ' 9 - ' , r w r l ' - # r r r r -

g 4 . ; S I * + - : - - - a - - ' P r - - , r--r a--.

1'1 ; : , n ; , " 0 # : a 0 : ; ; : ; 8 , ... l..;..:-----:--:--?-----+-,---L----- ; - - i - - - - - - . ........ , ;..+ , , ..... , .+- - , - - - - -w- : . ; : 8 , : : 0 ; ' :-:---: n a # : a

O 7- - - - . r - 2 - - - - - - lg&r' m m - - - ' f & g : - * ' * - ,A.1------ *dH& - - - - - **-: - - - - - - 19*rrt ------"

2.7 Summary

CLK

In this chapter, the design of a Add - Drop Multiplexer working in an ATM envi-

ronment bas been described. The ADM has been implemented in 0.5 pn CMOS process.

The ADM is dinded in functional blocks and presented at the behavior level first.

The logic b e h d a l l driving signals is analyzed and deducted. First the functional verifica-

tion was performed ushg high level simulation in VHDL. Separate entities for each corn-

ponent block were written. All were connected togethet using SGE.


Chapter 2: AdcCDrop Multiplexer Design Page 65

Each constituent block is then analyzed in detail. Specific design issues conceming

mainly high speed operation are raised and explained. Architectural and layout solutions

were provided. Simulation results are shown.

The bottlenecks related to speed that required extensive simulation and redesign-

ing were the CAM, the ADD SRAM, the 4: 1 MUX and DEMUX. The solutions were

more at the architectural and conceptual level than at the transistor level. Only the DFF

(TSPC) used a transistor level optimization. All constihient parts were simulated using

schematic and post layout exüacted netlist.



References

J. K. Madsen and P. S. Lassen, "A 2.5 Gb/s ATM Add-Drop Unit for B-ISDN Based

on a GaAs LSr', IEEE Journal of Solid-State Circuits, vol. 3 1, pp 1400-1 4OS,l9%

J. Yuan and C. Svensson, "High-Speed CMOS Circuit Technique", IEEE Jouml of

Solid-State Circuits, vol. 24, pp 62-70, 1989

Q. Huang a . R. Rogenmoser, "Speed Optimization of Edge-Triggered CMOS

Circuits for Gigahen Single-Phase Clocks", IEEE Journul of Solid-State Circuits,

vol. 3 1, pp 456-465,1996

T. M. Chen and S. S. Liu, ATM Switching Systems, Artech House Inc., Nowood,

f 995

R. Rogenmoser, The design of High-Speed Dynomic CMOS Circuits for VLSI,

Hartung - Gorre Verlag, Konstanz, Switzerland, 1996

D. J. Smith, "HDL Chip Design", Madison, Doone Publications, 1996


Chapter 3: Simulation and Experimental Results Page 67

Experimental Results

3.1 Chip Layout

The layout was done in a 3 metal layers HP 0.5 pn CMOS process. The layout of

the whole ADM chip and the position of various blocks is presented in Figure 3.1. Special

attention was given to minimize the high frequency path and interconnections between

various blocks of the design. The Input Buffer is centered as close as possible to the high

frequency inputs. The blocks are located in such a way that the data which is supposed to

pass without alteration has to travel only one length of the chip.

In the nght lower corner the additionai 4 pads are comected to the gate and drain

of a PMOS and a NMOS transistor, used to test the fabrication process. Measurements

indicated a close relationship between the HSPICE transistor parameters used in simula-

tions and the real measured parameters.

Roughly 35% of the intemal chip surface is occupied by decoupling capacitors.

Since the maximum number of available pins was used (68 PGA package), there was suf-

ficient interna1 fkee space for decoupling purposes. Decoupling capacitors are used to

reduce the impedance between power and ground, minimizing the effects of cumnt spikes

and board noise. The capacitor values are based on the maximum switching rate and the

power supply noise that the intemal logic cm tolerate. If decoupling capacitors are not

present, when large amounts of cumnt are needed, a significant voltage drop can occur

and the affected parts may malfunction. The only drawback is that a spccial power up pro-

cedm has to be followed.


Chaptei 3: Simulation and Experimental Results Page 68

ln? In0 Ntl dra dr7 drd &6 dr4 d a drP dri 2 2 " P U

Figure 3.1 ADM Chip Layout

AD = Add Demux AM = Add MUX

DD - Drop Demux DM - Drop Mux

DC - Decoupling Capacitor

Special test pins were used extensively throughout the design c o v e ~ g many dti-

cal points. These test pins are usefbl in case of a chip malfùnction. They help in localizing

the defec tive block.

The design uses distributeci buffers as shown in Figure 3.2. The delays were kept

qua1 for equivalent branches (same number of buffers) by analyzing the l a d on the clock p. .-

A 2.5 GUS CMOS AdbDrop Multiplexer for ATM University of Toronto


input for each block. Sizing formulas [l] were then used to minimize the number of invert-

ers. A detailed explanation of the dock b u f f e ~ g concept is described in Appendix B.

Figure 3.2 Clock Distribution

Pads were developed capable of driving a load of 14pF at 3 1 1 MHz.

3.2 Post Layout Critical Path Simulation

CLK

CLK-int

Figure 3.3 Post Layout Critical Path Simulation

Since both simulated paths using the schematic nettist pnsented the same delay,

only one of the paths is simulated using post layout extraction netlist and measund for

speed after fabrication. The chosen critical path is from IN[8] to OUT[8]. M y the parts

A 2.5 Gb/s CMOS AWDrop ~ultigexer for ATM University of foronto


that would affect the signal on the critical path were considered. The extracted netüst con-

tained information about the resistance of the metal layer and al l the parasitic capacitances

associated to the critical path. The p s t layout simulation results are shown in Figure 3.3.

A minor increase in the total delay (- 0 . 2 ~ ) is noticed by cornparison to the simulation

ilts reported in Section 2.6.

Experimental Implementation

Figure 3.4 ADM Chip Photomicrograph

The micrograph of the chip is shown in Figure 3.4. It occupies an area of 14.7 mm' and

has a transistor count of approximately 75 K.

A 2.5 Gb/s CMOS AWDrop Mulaplexer for ATM University of Toronto

Chapter 3: Simulation and Experimental Resuits Page 71

The HP test environment used for functional testing is described in Appendix A. It

consists of the HP E1496A Digital Test Development Software and the TH1000 Test

Head. The software allows to customize the environment and obtain a virtual testbench.

Signals are then generated and applied to the chip inputs. The outputs are recorded and

compared to the expected values. If any discrepancy is noticed between the expected val-

ues and the output values an error message is issued.

The first designed test is the power up test. This test is especially necessary in the

ADM case, were special care should be given due to the big decoupling capacitance. The

test setting is shown in Figure 3.5.

Figure 3.5 Powet Up Test Sening

The value of the idle current of the ADM chip was measured to be 300 rnA with

little variation as a function of the. The plotteâ power up test results are show in Figure

3.6. In the left window the voltage is shown to incrrase in steps h m O to N. In the right

window the expecteâ cumnt is measured.

A 2.5 GWs CM05 Add-Drop Multiplexer for ATM University of Toronto


Figure 3.6 Plotted Power Up Test Results

Next the functional test setting was designed. The sening used is shown in Figure 3.7.

Figure 3.7 Functional Test Setting

S M a r to the HDL testing, the vectors used for the maui and add input were generatcd

randomly and were stored in a He. They were nad and used as input stimulus by îhe test

A 2.5 GWs CMOS Add-Drop Mulaplexer for ATM University of Toronto


software. In total 10 patterns of ATM cells were checked. AU possible situations were

checked: cell for local node with valid payload, empty cell, cell not addressed for local

node, busy network case, low priority node and lost cell signal check. The high clock fie-

quency of the setthg was 20 MHz, and the low clock frequency (simulating the h o p side

was 5 MHz. Major test cycles were: Reset cycle, Load CAM cycle and the Test cycle

itself. A sample of the test vectors applied is shown in Figure 3.8.

Figure 3.8 Sampled Test Wavefom

AU functional tests were passed by the ADM. No error message was issued. It is

therefore concluded that the device operates functionally as expected at the test Frcquency.

3.5 Speed Testing

To ver@ that the chip is performing weU at the designed speed, a high frequency

test was also perfonned. The delay on the critical path (from IN[8] to OUT[8]) was mea-

sured. The setting used is shown in Figure 3.9. A high f i uency signal generator (HP

70322A Synthesized Signal Generator) was used to generate a refmnce signal. This sig-

nai was the input for the HP 70004A and HP 708418, a high frrquency display and pattern

generator. The waveform was visualized using the Tekttonix TDS 380 400 MEIz Digitiz-

h g Oscilloscope.

A 2.5 Gbls CMOS Adô-Drop Multiplexer foi ATM University of Toronto

Chapter 3: Simulation and Experimental Resuîts Page 74

Signal Generator Reference Data Out In

Clock Out

Trigger

ADM

OUT TDS380 fl DUT 1-, 1 Oscilloscope

Figure 3.9 High Frequency Measurement Setting

The pattern used in this measurement was a periodical000 1-000. This type of pat-

tern permitted the easiest way to synchronize the waveform. The chip was tested at the

nominal working frequency of 31 1 MHz. Although the generated pattem was selected to

be a square wave, at 3 1 1 MHz, the clock and input I output signals look more like a sinus

wave. Apart from a visible overshot on the falling edge, due to parasitic impedance of the

bonding wires, the measured signal is sunilar to the simulated waveform. A transition

fkom O to 1 at the input (IN[8]) is noticed at the output (OUT[8]) after 6 clock cycles and

the delay measured relative to the positive edge of the clock is 1.5 ns. This value is 15%

larger than the one obtained using the post layout extracted netiist.

For power measurements a 10 S2 / 10 W resistor was inserted in series with the

chip power supply. The average voltage drop was measured, yielding a cuirent of 0.9 A.

The supply voltage at the chip pins was kept constant at 5 V. The correspondent power is

therefore 4.5 W. This value is the same as the one obtained fiom schematic simulation.

From power point of view, t&ere is a 10% improvement over the GaAs design [2]. Using a

more advmced CMOS process with smaiier f e a w size could result in fuhlre reduction in

power dissipation. Measurement results are shown in Figure 3.10. In conclusion, the cir-

cuit performs well at the designed speed.

A 2.5 Gbfs CMOS Add-Drop Muttiplexer for ATM University of Toronto

Chapter 3: Simulation and Exparimental Results Page 75

. . . . . . . ,

. . . . . . . .

. . . . . . . . . . . . . . . . . . . . - . . . . . .

. . . - . . .

S NOV lBS8

Figure 3.10 Measwed Wavefom at 3 1 1 MHz

3.6 Summary

In this chapier the whole chip layout was presented. Techniques used to reduce

the interconnect were explained. Simulation of the critical path using the extracted post

layout netiist was performed. An increase of 18% in the delay was noticed over the

simulation results obtained when using the schematic netlist.

The micrograph of the ADM chip was presented. The chip implemented in 0.5

pn CMOS process has an area of 14.7 mm2 and dissipates, at the designed frequency of

31 1 MHz, 4.5 W. The functional verification of the chip was performed using the HP

Integrated Testing Environment. A virhial testbench was designed and test vectors were

applied. The testing procedure consisted of two parts. The first part was a power up test

where a 300 mA load current was measured as expected. The second part of the test was

a functionality test. AU main input combinations were tested. The testbench verified the

fact that the ADM performs as expected. Measunment on the critical path was ais0

successfully performed at the designed speed of 3 1 1 MHz.

A 2.5 GWs CMOS Add-Drop Muîtiplexer for ATM University of Toronto


References

[Il J. M. Rabaey, "Digital Integrated Circuits - A Design Perspective", New Jersey,

Prentice - Hall, 1996

[2] J. K. Madsen and P. S. Lassen, "A 2.5 Gbps ATM Add-Drop Unit for B-ISDN Based

on a GaAs LSI", IEEE Journal of Solid-State Circuits, vol. 31, pp 1400-1405, 19%

~ 2 . 5 Gbls CMOS AcWDrop Multiplexer for ATM University of Toronto

Chapter 4: Conclusions Page 77

CHAPTER 4

Conclusions

This thesis has addnssed the design of a high speed digital wtworking

component, using ATM protocol, the ADM. The goal of the thesis was to design the

ADM to work at a rate of 2.5 Gb/s (3 1 1 MHz) using a 0.5 pm CMOS process.

The designed ADM uses a pipelined architecture. It is divided in functional

blocks and presented at the behavioral level. nie gate level schematic is then shown. The

logic behind al1 driving signals is analyzed. Functional verification is performed at HDL

level. Each constituent block is optimized for speed. Architectural and layout solutions

were provided and simulation results are given.

The fabricated chip occupies an ana of 14.7 mm2 and was tested hnctionally at

20 MHz. Cntical path speed testing was also performed at 3 1 1 MHz. A good correlation

was obtained between simulation and experimental results.

Future work would include fully testing the chip at high fkquency. One solution

to perform this testing would be to use intemal dock multipliers. Another solution would

be to multiplex the high speed YO's. F'ally, test pattern generators could be also

integrated on the chip.

To improve the architecture of the chip, a combincd paraliel and serial

architecture must be developed. Che solution to speed limitation can be solved by

multiplexing the high speed VO's and using a lower hquency for the logic circuitry.

Substantial power and speed improvements cm be obtained if the process used is

scaled dom to 0.35 or 0.25 p.

A 2.5 Gbls CMOS AddDrop Multiplexer for ATM University of Toronto

Appendix A: TSPC Page 78

APPENDIX A

True Single Phase Clock (TSPC) Logic

In dynamic logic, the input data is stored as a charge on a floating node. It is there-

fore different fkom static logic, where a low impedance path is present at any time between

any node in the circuit and power or ground. The charge of the fioating node is discharged

by parasitic leakage currents and must be refieshed periodicaily.

VDD VDD

CLK

IN

OUT

CLK

IN

p-type GND

Figure A. 1 N-type and P-type TSPC [l]

The basic schematic of a TSPC is presented in Figure A.1. The Ktype TSPC

works by precharging the intemal node X. When the dock is low, X is precharged through

MPSZ When the clock goes high, MNS 1 is activated and node X is discharged or not,

dependhg on the input value applied on MN2. The output section (MP2 - MNS2 - MN3)

is a clocked inverter, transparent when clock is high and holds the output when dock is

low. Since the intemal node X is precharged high in the precharge phase, MP2 is always

off in this case and no clocked transistor between MP2 and OUT is necessary.

The cornplementary P-type TSPC works similarly: it discharges node X when

A 2.5 GWs CMOS AddDrop Muitiplexer far ATM University of Toronto


clock is high (the precharge phase for P-type) and evaluates the input when clock is low. In

the above described configuration (N or P-type), the input has to be stable during the

whole evaluation period, since once discharged, node X cm not be charged again until the

next precharge phase (referring to N-type).

VDD VDD

IN

CLK

OUT

IN

CLK

OUT

X

MN3

Figure A.2 N-type and P-type DC'MOS [l]

Another version for the TSPC is the Double Clocked CMOS @C~MOS) shown in

Figure A.2. In this case, there is no precharge phase and the input has to be stable only

around the clock edge, when the latch changes fiom king transparent to holding the out-

put value. A disadvantage of this design is that only simple logic is implemented, since for

any additional input, both upper and the Lower transistors have to be provided.

To obtain the edge-triggered D flip-Bop, two TSPC are needed: one of N-type and

one of P-type in a master-slave configuration. Using a combination of a DC*MOS (P-type)

and a precharged (N-type) TSPC, the output stage of the P-type can be eliminated. The

combined design is shown in Figure A.3. Simulating the design, spikes are noticed at the

output of the D flip-fiop, at the start of evaluation phase. The spikes are due to internai pn-

This bdiavior might trigger the systern into a wrong state and has to be comcted

for a safe functionality of the design. Therefore a improved version is used in this thesis

121

A 2.5 Gb/s CMOS AdcCDrop Muttiplexer for ATM University of Toronto


a) IN

CLK

VDD

GND

Figure A.3 Edge-triggered TSPC D Flip-Flop [l]

a) Schematic

b) Simulation Wavefom

CLK

IN

m X

Y

OUT

A 2.5 Gbls CMOS Add-Drop Mulüplexer for ATM University of Toronto


References

[l] I. Yuan and C. Svensson, "High-Speed CMOS Circuit Technique", IEEE Joumul of

Solid-State Circuits, vol. 24, pp 62-70, 1989

[2] Q. Huang and R Rogenmoser, "Speed ûptimization of Edge-Triggereà CMOS

Circuits for Gigahen Single-Phase Clocks", IEEEE Journal of Solid-State Circuits,

vol. 3 1 , pp 456-465,1996


Appendix 8: Clock Distribution Page 82

APPENDM B

Clock Distribution

One of the problems in bigger designs is the clochg scheme. There are two main

solutions: a central powerful clock buffer or a tree of distributed srnall buffers, as seen in

Figure B. 1. Single Driver

I

Figure B. I Clock Distribution

The soiution adopted in this thesis involved uskg distributed buffers. Since no

automated tool was used, the delays were kept equal for equivaleat branches (same num-

ber of buffers) by analyzing the load on the clock input for each block. Sizing formulas [l]

were then used to minimize the number of inverters. For an inverter, the delay from input

to output could be written:

t - $LH + $HL ri,

P 2 E - a=- 3

Where t p ~ ~ and $,m are the delays due to nse and fall cime, CL is the l d capaci-

tance, IE, and $ are gain factors, H, and are the carrier mobilities, and W and L are the

A 2.5 Gbls CM06 AddDrop Muttiplexer for ATM University of Toronto

Appendix 0: Cl& Distribution Page û3

width and length of the transistor. In the general case when N such inverters are co~ected

together, a structure similar to the one presented in Figure B.2 appears.

N Stage Buffer

Figure B.2 N - Stage Buffer [l]

The equations deducted for this case are:

Where u represents how many times the transistor size of the next buffer is larger

than the previous one, and is the propagation delay of the minimum size stage. The

conclusion that uOpt = e is used extensively when designing the clock tree.

A 2.5 GWs CMOS Add-Drop Muitiplexer br ATM University of Toronto

Appendix 0: Clock Distribution Page 84

References

[1] J. M. Rabaey, "Digital Integrated Circuits - A Design Perspective", New Jersey,

Rentice - Hall, 1996

A 2.5 GWs CMOS Add-Drop Muîtiplexer for ATM University of Toronto

Appendix C: Test Setup Description Page 85

Test Setup Description

In the functional testing process the VXI Test Head Fixturing Software was used.

It allows a versatile setting and fixturing of the Device Under Test @UT). Viarious posi-

tions of the device can be explored interactively, rninimizing the connection length. The

chosen h a 1 position used in this measurement met these cnteria. In Figure Ce 1 and Figure

C.2 the fixturing of the ADM and pin connection correspondence used is shown.

Figure C.l FURuing of the ADM

- -

A 2.5 Gbls CMOS AddoDrop Muttiplexer fw ATM University of Toronto


Module 1 nodule 2

P o d 0 i A muid. aipbt TiirLag P d O/OL [Tirla01

P o r t o T I output alkz L i I /C Unuud CDnttol 6 : le unuaœi Cantrnl 5 4 1 M E Unuad Cmtro l 4 1: I f C Unuaaâ Coatml 3 1: I/C UQU& Cantro1 Ir I / C Unuaod Coatrol 1 01 rnitput alkl

RDti N/C n r i r n r l i1qnaLt RGi i / C &urnaL LlqnaL t

I E UC.L -RiiPIT

a bas 1- 4 a ? a D > &GD 1 w41, i w4¶* I wu* b 48Qb

;O &Ob IL &* I S C i U 8 ta C U I

ii i" I;i , n IIJ ai8 4 Y t u a i t 4 ?a 16% a81 4 mm l n ain 4 m tll Li? > U l¶b 114 1 n lei l e ¶ I n tao t b r 1 )t 147 t e l I

P d J i D Outaida Lœft Data Pod 1/73 [ P i t t . r n 1/01

Pore a O: Output adci> 1: output del> 1: autvut &CL,

O: 1npuc u t r m 1: input urbpb 2; Input 1: Inmur

cstwra

Cor+ L n/C r/c n / c Output ad<@> output r d s n Output bàçb> output ad&> output &<4* * / C n c r r n i l 6Lqnall */C h u m a l I lqna l l

Pod I r D a t a P d

O: X: ~apuc taput

2: Input J i Input 4: lnput S i Iapuc 6: Input 7: Input

-01: H I C C L I i *pz

Port 3 O: Input amllnv t: rnput u t i r a a; Iapuc Cnthlk 1: Input U U a i r i lnouc ut&

Pod 3 r C Outaid. Ught Data Pod 3/01 [ P i t t u u I n ]

loct O O: Input c l o i t t: input outsl, 1: toput outCD 3 : illpUt OUt<3> 4 1 IOpUC OUt<4> Sr lnput out<J> r i Input o u t s e 7: Input 0ut4R

- a r t 8 s u ta raa l I lqnaI 1 CLI; r#c Rtoraa l I lp tuLt

a i 1: Oucpuc i/c

1: autput 1: output 4: output s i Output 1: autput I I ôutput

-01; Ils CLIi I/C

Figure C.2 Tested Connectors Correspondence



Table A. 1 gives the correspondence

assigned pin direction: input or output.

Table A.1: Chip Pin Correspondence

between the real chip pin count and the

Table A.1: Ch@ Pin Correspondence

1 4 1 output 1 d r 4 > 1 37 1 output l &Wb

Pin

35

1 38 1 Output 1 tstwrs 1

1 43 1 Output 1 tstblk 1

VPe Output

1 44 1 Output 1 tstdsl 1

Real

tstept

-- -

23 Output out<6> 24 Output out<%

A 2.5 Gb/s CMOS Add-Drop Muitiplexer for ATM Univenw of Toronto

28 31 32 33 34

Output

output Output output output

outcl> c10st caval socout tstmat


Table A.2 gives the correspondence between VXI Test Head and HP Modules pins.

The table is divided in modules, pods and ports. Each Module has two poàs and each pod

bas two ports. Table A.2: Test Head - HP Modules

Fixturing Correspondence Table A.2: Test Head - HP Modules

Frxhving Correspondence

Pin 1 'I)p 1 Real 1 Bit 1 HP

Module O P d O (Right) - Pott O I poà 1 (~ight) - Port 1

Module 1 Pod 2 (Left) - Port 2

Module 2 P d 4 (Left) - Port 2

1 10 1 out 1 dKZ> ( 1 1 ou2424r

Pod 2 (Left) - Port 3 40 1 out 1 tstrso 1 O 1 ou1234b

Pod 4 (Left) - Port 3 r-- 1 48 1 out 1 ceiiav 1 O 1 o u 2 4 3 6 35 1 out tstept 3 ou1230>

1

36 1 out tstspa 4 ou123<4> 1 43 1 out 1 tstblk 1 2 1 ou2434b 1 44 1 out 1 tstdsl 1 3 1 ou2434>

1 46 1 out 1 tstmk 1 5 1 0 ~ 2 4 3 4 ~ 1 Pod 1 (Right) - Port O 1 1 21 1 out 1 out<8> 1 6 1 ou243<6>

1 Pod 3 (Right) - Port O

1 31 1 out 1 clost 1 O 1 ou23(k0>

27 out out<2> 2 01123- 26 out out<3> 3 ou23(k3>

- - .- -- . -

A 2.5 Gb/s CMOS AddOrop Muitiplexer for ATM University of Toronto


Table A 2 Test Head - HP Modules Frturing Correspondence

Table A.2: Test Head - HP Modules Fixturing Correspondence

1 Pod 3 (Right) - Port 1 1

Pin 1

25

The Test Head uses a ZIF socket with a rnatrix of 16 x 16 accessible connections.

The comection between the socket and the "Tnner Wiring Anay" - visible connectors

closest to the socket - is hardwired. The user can only customize the comection between

the "Inner W h g Array" and the "Outer Wiring Amy". Customizing the interconnections

dows to minimize the length of the wues interactively.


T)qx out

Real

out.4>

Bit

4

HP

ou230<4>

a 2.5 gbls cmos add drop multiplexer€¦ · a 2.5 gws cmos add - drop multiplexer for atm master...

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