A 20/30 Gbps CMOS Backplane Driver with Digital Pre-emphasis

•Paul Westergaard, Timothy Dickson, and Sorin Voinigescu•University of Toronto•Canada

Outline

• Motivation• Design Goals• Circuit Description and Design • Experimental Results• Summary and Conclusion

MotivationApplication • Serial inter-chip communications over

backplanes at 20-Gb/s. Unfulfilled Needs • CMOS implementation over 10-Gbps• > 30 dB dynamic range, low-power • Programmable width and height pre-

emphasis to increase receiver simplicityPrior Art• Previous CMOS backplane drivers have

only achieved 10 Gb/s data rate.

Design Goals • 30-Gb/s main path operation without pre-emphasis • 20-Gb/s fully featured operation with

– ‘digital’ pre-emphasis – eye-crossing– output swing control

• High Sensitivity (<10 mVpp per side)• Large output swing (>350 mVpp per side)• 50-Ohm input/output matching• 1.5 V supply• 130 nm CMOS implementation

Circuit Design and Description

Biasing for peak fT and NFMIN

Peak fT bias

0.3mA/um

Min. NFMIN

0.15mA/um

Multi-stage amplifiers with signal path transistors biased at half peak fT

Circuit Architecture

• Multi-stage amplifier implementation• Input stage biased and sized for high

gain and low noise• Inductive broad-banding in every

inverter stage to reduce power and increase speed

• Main (higher-speed) and pre-emphasis paths are parallelized

Block Diagram

InputMatching

& Comparator

PulseWidth

Control

Vin

DelayBuffers Digital

Differentiator

Vout

OutputDriver

InputMatching

& Comparator

PulseWidth

Control

Vin

DelayBuffers Digital

Differentiator

Vout

OutputDriver

VinPVinN

VoutPVoutN

IbiasM1 M2

160 ohm 160 ohm

80 ohm 80 ohm 90 ohm 90 ohm

400 pH 400 pH 400 pH 400 pH

M1, M2 w = 36um, l = 0.13um Finger widths = 2um

12 mA

Input Matching and Low-Noise

Comparator

Eye-crossing Control

inN inP Voffset+ -

VmidDIFF

Vout+

-

Ibias = 1.2mA M1 M2 M3 M4 M5 M6

4.8mA Ioffset = 4.8mA 12mA

Vdd = 1.5V

100 ohm

700 pH

100 ohm

700 pH

110 ohm

900 pH

110 ohm

900 pH

M1 - M4 w = 24um, l = 0.13umM5, M6 w = 32um, l = 0.13um

Finger width = 2um

InputMatching

& Comparator

PulseWidth

Control

Vin

DelayBuffers Digital

Differentiator

Vout

OutputDriver

*D. S. McPherson, S. Voinigescu et alIEEE GaAs IC Symp. - Oct. 2002

Digital Pre-emphasis Delay Circuit Input

Matching& Comparator

PulseWidth

Control

Vin

DelayBuffers Digital

Differentiator

Vout

OutputDriver

DelayBuffers Digital

Differentiator

Vout

OutputDriver

++

Digital Differentiator

VoutN

Vdd

VoutP

IN IN IN IN

INdly INdlyINdly INdly

Vdd

Ibias = 2mA

Iswch = 10mAIswch = 10mA

M1 M2 M3 M4 M5 M6

M7 M8 M9 M10

Vdd = 1.5V

50 ohm50 ohm

M1 to M10 w = 32um, l = 0.13umM11, M12 w = 10um, l = 0.13um

Finger widths = 2um

InputMatching

& Comparator

PulseWidth

Control

Vin

DelayBuffers Digital

Differentiator

Vout

OutputDriver

IN

INdly

IN

INdly

VoutP

VoutN

VoutP

VoutNIN.INdly

IN.INdly

IN.INdly

IN.INdly

Inductor design considerations

• Inductor broadband “2-” model model extracted for design from ASITIC simulations.

• Multi-layer ( 2 or 3 metals) design used to minimize inductor area (400, 700, 900 pH used)

• Largest inductor side is 44 um (900 pH)

Experimental Results

Chip Photograph

1.0 mm

0.5

mm

DigitalDifferentiator

DelayBuffers

OutputDriver

InputMatching

& Comparator

PulseWidth

Control

Input/Output Return Loss

Measured Eye-diagrams: 0.3Vp-p output

20 Gb/s 25 Gb/s

30 Gb/s

Sensitivity

20 Gb/s 30 Gb/s

Input: 21mVpp one side onlyOutput: 80mVpp per side

20-Gbs Eye with Pre-emphasis

Output Swing Control @20Gbps

Input: 200mVpp one side only

Output: 170mVpp Output: 340mVpp

Output Swing Control @30 Gbps

Output: 170mVpp Output: 270mVpp

(Gain at 30 Gb/s!)

Input: 200mVpp one side only

30%-70% Crossing Control @20 Gbs

70%30%

50%

40%-60% Crossing Control @ 25 Gbs

60%40%

50%

Summary and Conclusion

Performance SummaryParameter Measured val.

Technology 130nm CMOSSupply Voltage 1.5 VPower Dissipation 150 mWOutput Swing @ 20 Gb/s 170-350 mVp-pPre-emphasis @ 20 Gb/s 30%/10%Crossing Control @ 20Gb/s 30% to 70%Eye sensitivity @ 20 Gb/s 20(10) mVppDynamic Range @ 20 Gb/s 30 dBNoise Figure(10GHz,15GHz) 16.5 dB, 17 dBS11/S22 up to 50 GHz <-12 dB

Conclusion• First CMOS driver above 20 Gb/s• Novel digital pre-emphasis• High sensitivity, dynamic range• Large output swing• Eye-crossing control• Communications between chips and

backplanes is feasible at 20 Gb/s in 130-nm CMOS technology

Acknowledgements

• Rudy Beerkens and Boris Prokes of STMicroelectronics Ottawa

• STMicroelectronics for fabrication• Micronet and Gennum Corporation

for financial support• Quake Technologies for access to 40

Gb/s BERT