a 20 db, 200 khz soi-cmos capacitive feedback op-a r high ... · d offers extre cmos trans rature -...
TRANSCRIPT
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Abstract—Thedback op-amown-hole-drillimperature (>1
wo-stages wherrcuit is adopteain and high mperature apOI-CMOS tech00 °C shows trcuit stays to 5c gain stays to or those tempearts to increas
Index Termsigh temperaturcuit.
High temperutomotive, aelectronics for t elevated tempplication is ollecting, loggnclination, temiggest challeown-hole-drillemperature (>ver 2 km dep1]-[2].
Silicon techusiness. The uircuits to be faow power conxhibit many eakage increaeduction. Amourrent at higheduces circuit auses the losseriously, destechnology sigliminating theegion and subroperties of buesigns from bu
Manuscript receThe authors are
cience, Technolog
A
his paper presmp for electroing applicati170 °C) regimre first stage is ed to maintain
cut-off frequpplication. A hnology was chthat transcond50 uS within ± constant valuerature range.
se from 240 kH
s—SOI-CMOSure electronics
I. INTR
rature electronerospace, nucthose applicat
mperature. Eleto explore
ging and procemperature anenge in daling applicati
>170°C) encoupth below th
hnology domuse of bulk-Cabricated on a nsumption. Hdrawbacks a
ase, thresholdong these drawh temperature
performances of charge sttroy the chignificantly ree reverse-biasebstrate/well, ulk-CMOS teculk CMOS to
eived August 24, e with Institute of gy, and Research)
20 dB, Op-A
sents an SOIonic data acqion which o
me. The op-amfolded cascodeno degradatio
uency of the commercially
hosen. Measureductance of th2 % accuracy
e of 19.8 dB (2 Otherwise hig
Hz at 0 °C to 32
S, capacitive s, constant-gm
RODUCTION nics finds manclear and dotions require aectronics for modern oil/gessing data su
nd pressure oata acquisitiion is also thuntered at gre
he surface of
minates todayCMOS allows
single die, anHowever bulk-at high temped voltages shwbacks, excesis the most s
e due to loss tored at dynamip due to leduces the leed diodes betand it has m
chnology, so iSOI CMOS.
2012; revised SepMicroelectronics), Singapore.
200 kHAmp fo
Jeongwo
I-CMOS capaquisition systeoperates at
mp is designed e. A constant-gmon of the closed
op-amp for y available 1ements from 0 he constant-gmand the closed% less from 2
gh cut-off frequ20 kHz at 200 °
feedback, op-m current refe
ny applicationown-hole dria reliable operdown-hole-dr
gas wells thruch as headingof the strata.ion systems he high opereat depth typithe earth/sea
y’s semicondanalog and d
nd offers extre-CMOS transerature - junhift, and moss junction leaserious probleof bias curre
mic node, or atch-up [3].
eakage currentween source/most of the it is easy to mi
ptember 11, 2012s, A*STAR (Agen
Hz SOIr High
ook Koh, M.
acitive em in
high to be
m bias d loop
high 1 um °C to
m bias d-loop 20 dB) uency °C.
-amp, erence
s like illing. ration rilling rough g and The
for rating ically a bed
ductor digital emely istors
nction obility akage em. It ent or more SOI
nt by /drain good
igrate
2. ncy for
IndesigtechnGenecircugate feedbconsdesigtransgain
Indemousingappli
II.
A.Th
ordedue tleakacurreSOI devicleakaop-a
FidepetransincreobsePMOleakareduleakadepe
I-CMOTempe
Annamalai A
n addition to gn techniqueniques availaerally such meuit. Examples
biasing, subback cancellat
stant-gm biasingn [4]. Constasconductance of op-amp is
n this paper wonstration of g constant-gication.
TECHNOLOG
Leakage Curhe junction lr) in SOI-CMto the reducedage towards tent is then thetransistors, thce length [5]age current o
amp and constaig. 1 and 2 endent junctiosistors from 0eases in both terve no furtheOS transistor bage current i
uction for alage current oendence.
Fig. 1. Jun
OS Capaerature
Arasu, and M
technology cis to be consi
able to mitigethods depends are ZTC (zebstrate biasingtion, and cons
ng is the most ant-gm biasinggm of op-ampobtained.
we will preseSOI-CMOS
gm bias circ
Y CONSIDERA
rrent eakage curren
MOS transistord junction areathe substrate. e generation this volume de]. Therefore of SOI-CMOant-gm bias cishow simul
on leakage cu°C to 200°C. transistors witer increase ofbeyond 150 °Cin NMOS trl temperaturef PMOS tran
nction leakage cur
acitive Applic
Minkyu Je
considerationidered. There gate the abod on the specifero temperatug feedback, stant-gm biasinrelevant techn
g makes “temp and thus stab
ent design ancapacitive fe
cuit for hig
ATIONS FOR HT
nt is remarkar than bulk-CMa and the abseSince the do
term in the deecreases with
it is worthwOS transistors
rcuit. ation results urrent in NMThe junction
th temperaturef junction leaC. It is also fouransistor decres. Otherwis
nsistor show l
rrent in NMOS tr
Feedbacation
, analog circare many oth
ove drawbackfic structure oure coefficienleakage curre
ng. Among thenique to op-am
mperature-stablbile closed-lo
nd experimeneedback op-amgh temperatu
T APPLICATIO
ably smaller MOS transistoence of diffusiominant leakaepleted region the reduction
while examinis for design
of gate-lengMOS and PMO
leakage curree increasing. Wakage current und that junctireases with tse the junctilittle gate-leng
ansistor.
ack
cuit her ks.
of a nts) ent em mp le”
oop
ntal mp ure
N
(3 ors ion age in of
ing of
gth OS ent We
in ion the ion gth
International Journal of Information and Electronics Engineering, Vol. 3, No. 1, January 2013
35DOI: 10.7763/IJIEE.2013.V3.260
B
decodrpa
patra
letrachNchwtharfomsh
Fig. 2.
B. Channel LThe output
etermine oponductance orain-source carameter λ as
And it is wearameter is inansistors [6]. Fig. 3 and Fi
ength modulaansistor with vhannel length
NMOS and PMhannel length
when comparedhat PMOS traround 1.5 timeor all temper
modulation parhorter gate len
Fig. 3. Chann
Fig. 4. Chann
Junction leakage
Length Modulconductance
en-loop gainof a MOS urrent IDS an
g
ell known thatnversely propo
ig. 4 show temtion parametevarious gate leh modulation
MOS transistorh modulation d to NMOS traansistor with es more channratures. Morerameter is obtngths.
nel length modula
nel length modul
current in PMOS
lation Parameis one of
n of op-amtransistor is nd channel l
λ · IDS
t the channel ortional to ga
mperature depeer (λ) for Nengths. As tem
parameter ds. PMOS transparameter foansistor. Inter4 to 6 um g
nel length moe than 2 timtained in PM
ation parameter o
ation parameter o
S transistor.
eter parameters w
mp. The oexpressed
length modul
length modulate length of
endence of chNMOS and Pmperature incrdecreases insistor shows h
or all temperarestingly it is fgate length sdulation param
me channel leOS transistor
of NMOS transist
of PMOS transist
which output using lation
1
lation MOS
annel MOS
reases, both
higher atures found shows meter ength
r with
tor.
tor.
C.W
NMOdesigjunctparam
Trassumeffec
Wmobmob
Fibias
Inthrou
Wassum
Inwritt
No
Gate LengthWe have found
OS and PMOgn through cotion leakage meter.
III. DESIGransconductanming negligibct, is given by
When bias currility, transconility degradatiig. 5 shows thecircuit is base
n (3) VGS is gugh RB.
With keeping ming Vth,M1=V
F
n the design wten as
ow we get gm
h for Design d that the gatOS transistorsonsiderations o
current and
GN OF CONSTA
nce gm of Nble channel leny [7]
2
ent ID is madenductance gm ion and thus te constant-gm ed on
,
gate-source v
IB=IREF, neVth,M2, we hav
2⁄
Fig. 5. Constant-g
we have 4 for K
2
m as
te length 4 us are good bof temperature
channel len
ANT-GM BIASNMOS in satngth modulati
e inversely prois ideally ind
emperature-inbias circuit in
, ·
voltage and IB
eglecting boe
1√
gm Bias Circuit.
K in (4) and n
1⁄
1
um to 6 um fbaseline for te dependencegth modulati
S CIRCUIT turation regioion and the bo
oportional to tdependent of tndependent. n the design. T
B is the curre
ody effect a
1√
now current IB
for the of on
on, ody
2
the the
The
3
ent
and
4
B is
5
6
International Journal of Information and Electronics Engineering, Vol. 3, No. 1, January 2013
36
From (6) it is known transconductance gm will be stable
over temperature when RB has a zero-temperature coefficient.
IV. DESIGN OF OP-AMP Fig. 6 shows the op-amp core in the design. The op-amp
core is a two stage miller amplifier where the 1st stage has a folded cascode PMOS input stage for high dc gain. A PMOS input stage is selected. PMOS transistor has better threshold voltage mismatch property, lower flicker noise, and a quite comparable current driving capability compared to its counterpart NMOSFET in 1.0 um SOI Technology [7]-[8]. The second stage is a PMOS input inverting amplifier with NMOS cascode current source and thus the op-amp has less output resistance. In addition the second stage is designed to drive high capacitance for high temperature measurement environment - long cable from DUT (device under test) in hot chamber may induce large capacitance.
Fig. 7 shows the capacitive feedback op-amp. If C2 is variable capacitance as in a capacitive MEMS accelerometer, the capacitive feedback op-amp is called capacitance-voltage converter (CVC), a widely used MEMS accelerometer analog interface circuit [9]. The capacitive feedback op-amp is a prototype for an analog frontend in a MEMS accelerometer acoustic telemetry receiver part for down-hole drilling application. The capacitive feedback op-amp is designed to have an amplification of 20 dB in the frequency range from 200 Hz to 200 kHz from 0 °C to 200 °C.
Fig. 8 shows the open-loop ac gain and phase of the op-amp as temperature increases from 0 °C to 200 °C. The op-amp ac gain stays a relative constant value of around 112 dB and its phase margin also stays a relative constant value of 63 degree. Otherwise unity-gain-bandwidth of the op-amp increases from 3.4 MHz at 0 °C to 3.9 MHz at 200 °C. The op-amp consumes more current as temperature increases. These results are listed in TABLE
Fig. 6. Folded cascode two stage op-amp
Fig. 7. Capacitive feedback op-amp
.
Fig. 8. Open-loop ac gain and phase of the op-amp.
TABLE I:SIMULATION RESULTS OF THE OP-AMP.
Temp [oC]
Open-loop Gain [dB]
PM [°]
UGB [MHz]
Current Consumption
[mA] 0 111.3 64.2 3.4 0.9 25 111.6 64.0 3.5 1.0 50 111.8 63.9 3.6 1.2 75 111.9 63.7 3.6 1.3
100 111.9 63.6 3.7 1.5 125 111.9 63.5 3.8 1.7 150 111.8 63.5 3.8 1.9 175 111.9 63.5 3.9 2.0 200 111.9 63.5 3.9 2.3
V. MEASUREMENT RESULTS The capacitive feedback op-amp with constant-gm bias
circuit is fabricated in 1 um SOI-CMOS technology and Fig. 9 shows the chip photo. Measurements were made in temperature chamber from 0 °C to 200 °C. Current consumption starts to increase from 0.9 mA under 5 V at 0 °C to 2.2 mA under 5 V at 200 °C. Fig. 10 shows the measured transconductance of M1 in constant-gm bias circuit (Fig. 5). The transconductance of the constant-gm bias circuit shows 50 uS within ± 2 % accuracy in the temperature range Fig. 11 shows the measured closed-loop ac gain plot of the capacitive feedback op-amp (Fig. 7). The closed-loop ac gain stays a constant value of 19.8 dB (2 % less from 20 dB) in the temperature range. Low frequency cut-off of the capacitive feedback op-amp stays 150 Hz in the temperature range otherwise high cut-off frequency starts to increase from 240 kHz at 0 °C to 320 kHz at 200 °C.
Fig. 9. Chip micrograph of the op-amp.
Temperature increases0°C to 200°C (50°C step)
Temperature increases0°C to 200°C (50°C step)
International Journal of Information and Electronics Engineering, Vol. 3, No. 1, January 2013
37
of
Fig. 10
Fig. 11. Clos
This paper pf the SOI-CM
. Measured transc
se-loop ac gain pl
VI. CO
presents desigMOS constant
conductance of M
lot of capacitive f
ONCLUSION gn and experimt-gm biased ca
M1 in Fig. 5.
feedback op-amp
mental verificapacitive feed
.
cation dback
op-aelectappliconsto 2.consin thconstempthe tincre
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]X
[9]
amp over a tetronic data aication. Me
sumption start.2 mA under stant-gm bias che temperaturstant value ofperature rangetemperature rease from 240
S. P. Rountree etSystems and Ap2000. J. Koh et al, “AFeedback Op-AmApplication,” IntCircuit, 2012. M. Willander et Hall, London, 19X. Yu, “High-TeAcquisition,” Ph2006. J. P. Eggermont eapplications up topp. 179-186, 199B. Razavi, “DMcGraw-Hill. M. N. Ericson etDepleted SOI NIEEE Aerospace Design Manual, X-FAB SemicondN. Yazdi et alaccelerometers,” 2004.
emperature raacquisition syeasurement s to increase f5 V at 200 °Ccircuit shows re range (3) f 19.8 dB (2 e (4) low cut-orange (5) high0 kHz at 0 °C t
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off frequency h cut-off freqto 320 kHz at
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International Journal of Information and Electronics Engineering, Vol. 3, No. 1, January 2013
38