A 128-channel event-driven readout ASIC for the R3B

Tracker

TWEPP 2015, Lisbon

Lawrence Jones

ASIC Design GroupScience and Technology Facilities Council

Rutherford Appleton Laboratory

Superconducting Fragment Separator (Super-FRS) at FAIR, GSI

High-energy branch

Nuclear reactions using high-energy radioactive beams.

Introduction

R3B Experiment

Reactions with Relativistic Radioactive Beams - R3B

Target recoil detector measures light charged particles and gamma rays

Silicon Tracker surrounds the target together with CALIFA calorimeter

R3B silicon tracker

Silicon microstrip sensor

Dual-sided silicon strip sensorsConsists of 3 layers120,000 channels100 micron thickness for the inner layer and 300 micron thickness for the two outer layers.

Introduction

R3B ASICs

Detector Geometry

50um pitch

Double-sided (n & p) stereoscopic strips

Strip length varies depending on position

Capacitance – few pF to 80pF

Data rate – Dependent on position in detector. Worst case: 5kHz/channel

Occupancy – Dependent on position in detector. Worst case: 15%

ASICs on p side at high voltage

Proton rate is ~100s of Hz

Delta electron (background) rate ~100s of kHz (some reactions)

Worst case count rate limited by ADC occupancy

Califa calorimeter will see the protons but not the electrons

Califa produces a “proton detected” validation signal to the ASIC

Tells ASIC to only buffer events when validation is high

The front end must cope with the100kHz electron rate even if the data is not read out

The front end must also recover from 1GeV signals caused by beam misalignment

High dynamic range 50MeV (2V), low threshold 100keV (2mV)

Transistor mismatch

Challenges

Specification

Functional128 ChannelsDetector capacitance: up to 80pFSignal polarity: selectableEnergy range (silicon strips): 50MeVDC input couplingLeakage current compensation: up to 100nASelectable shaping time: 0.5s – 8 sNoise: ~7keV + 0.15keV/pF (RMS) at 2us shapingData Driven readoutADC: 12 bit SAR, ~1 Msample/sNearest neighboursInput Clock Frequency: 100MHz or 200MHzDaisy chainable (50MHz)Manchester coded output (selectable)15 bit Timestamp (5ns or 10ns)On-chip bandgap and DACs for bias generationPower consumption: 7mW /ChannelPower supply: 3.3V

PhysicalProcess: AMS 0.35um CMOSSize: 12.9mm x 6.2mm

R3B ASIC Block Diagram

……

…..

.

Preamplifier Shaper

Gain Amplifier

Peak Hold

Comparator

Comparator

Time StampCounter

AnalogueMultiplexer

12 bit ADC

CalibrationMask

Time Stamp Clock

Energy Threshold

Time Stamp Threshold

CalibrationVoltage Level

CalibrationControls

128 Channels

Signal

I2C Interface

128 bit OR

…….

Trigger

Channel Control Logic

Gain Amplifier

Hit

fro

m

Nei

ghb

our

Hit

to

Nei

ghb

our

Chip Control Logic

DataBuffer

Va

lidat

ion

Hit

fro

m

Nei

ghb

our

Hit

to

Nei

ghb

our

200/

100M

Hz

50M

Hz

Dat

a

Dat

aV

alid

Rea

dEna

ble

50M

Hz

Dat

a

Dat

aV

alid

Rea

dEna

ble

Control Registers

Energy

Timestamp

Channel Readout

Dai

sy C

hain

Rea

dout

Interface & Registers

Test Pulse Circuit

Preamps Shapers x10 amps Com

ps

PHTes

t Channel logic ADC I2C

Control Logic

Bandgap & Bias DACs

R3B ASIC Layout

+

-

-

+

RST

Detector

Cf = 1.41pF

VPRE

TrimmedVPREMiller Comp Control

Ibias

Icom

p

To Shaper

Leakage Compensation Circuit

Constant Current Feedback

Overload Protection

PreamplifierDetector DC coupled, capacitance up to 80pF

Two feedback circuits, one for leakage current compensation up to 100n. Either can be powered down

Programmable compensation to minimise the rise time and keep the amplifier stable over the different strip capacitance

Range 50MeV (silicon strips)

Pulsed reset, to recover from delta electrons

Switchable polarity feedback

Programmable bias between 0.5V and 2.5V

Overload recovery for 1GeV signals.

Trimmable bias to feedback to compensate for mismatches in the preamp

Electrons mode

1.3pF

1.3pF

2.6pF

5.2pF

10.4pF240k

1M

RST

500f

500f

1p

2p

4p

RST

From Preamp

To Peak Hold

VSHA

380k

ShaperDifferential amplifier

CR-RC

Bias programmable between 0.5V and 2.5V

Pulsed reset

Programmable shaping time between 0.5us and 8us (4 bit)

12

1.1pF Resistive Feedback

RST

110fF

From Preamp/Shaper

To Comparator

VPRE10 / VSHA10

x10 Amplifier

Low threshold requires gain before comparators

Differential amplifier

Gain set by capacitors

Large value resistive feedback to avoid drift when no signals

Bias programmable between 0.5V and 2.5V

Pulsed reset

Peak Hold

Dual polarity peak hold circuit One amp used as buffer Common capacitor to save space

S a m p l e B

Sa

mp

le

S a m p l e B

S a m p l e

Hit

B

Rs

t

C P H

C S H

S a m p l e

F r o mS h a p e r

T o A n a l o g u eM u l t i p l e x e r

1 s t a g e d i f f a m p

1 s t a g e d i f f a m p

V P H

V O U T

V S H A

T r i c k l e C u r r e n t

V S H A

V P H

V O U T

Hi t

Samp le

Rs t

Peak Hold (holes mode)One amp used in peak hold circuitOther amp used as bufferTrickle current keeps circuit biased when there is no signal to avoid it drifting due to leakage currentsTrickle current removed when a signal occurs

Preamp

Preamp Reset

Shaper

Shaper Reset

Peak Hold

HitSamplePeak Hold Reset

Analog Mux Out

PH Sample

Simulation of analogue data path

Hit synchronised here

Hit occurs here

Programmable dependingon peaking time

1MHZ Clk

Sample

PreampRst

ShaperRst

Peak Hold RstB

Programmable

Minimum (1)

(2)

(3)

(0)

ShaperOutput Timing

Programmable sample time to account for shaping time

Programmable Peak hold reset length (also resets digital)

Preamp and shaper have fixed length resets

12 bit successive approximation ADC

4 MSBs from resistor string

8 LSBs from capacitor array

Runs at

1 Msample/s

Variable clock period

Comparator Input

ADCDV

RUN

CLK

……

…...

Preamplifier Shaper

Gain Amplifier

Peak Hold

Comparator

Comparator

Time StampCounter

AnalogueMultiplexer

12 bit ADC

CalibrationMask

Time Stamp Clock

Energy Threshold

Time Stamp Threshold

CalibrationVoltage Level

CalibrationControls

128 Channels

Signal

I2C Interface

128 bit OR

…….

Trigger

Channel Control Logic

Gain Amplifier

Hit

from

N

eigh

bour

Hit

to

Nei

ghbo

ur

Chip Control Logic

DataBuffer

Val

idat

ion

Hit

from

N

eigh

bour

Hit

to

Nei

ghbo

ur

200/

100M

Hz

50M

Hz

Dat

a

Dat

aVal

id

Rea

dEna

ble

50M

Hz

Dat

a

Dat

aVal

id

Rea

dEna

ble

Control Registers

Channel Control LogicDetects Hits and sequences sampling of data. Runs at 1Mhz clock

Controls the resetting of the analogue channels

Reads out data stored in channels to ADC and FIFO

Generate an OR of all hits which can be transmitted off chip as a trigger

Chip Control LogicGenerates clocks

Reads out ADC and FIFO

Shifts data off-chip

Controls daisy chaining

3

Clk

Ou

t

Da

taO

ut

DA

Vin

RE

No

ut

Clk

In

Da

taIn

DA

Vo

ut

RE

Nin

2

Clk

Ou

t

Da

taO

ut

DA

Vin

RE

No

ut

Clk

In

Da

taIn

DA

Vo

ut

RE

Nin

1

Clk

Ou

t

Da

taO

ut

DA

Vin

RE

No

ut

Clk

In

Da

taIn

DA

Vo

ut

RE

Nin

0

Clk

Ou

t

Da

taO

ut

DA

Vin

RE

No

ut

Clk

In

Da

taIn

DA

Vo

ut

RE

Nin

F i r s t

L a s t

C l k S e l

F i r s t

L a s t

C l k S e l

F i r s t

L a s t

C l k S e l

F i r s t

L a s t

C l k S e l

1

1

0

0

0

0

0

0

0

0

1

0

0

00

Ch ip 0

Ch ip0 Ch ip 1

Ch ip0 Ch ip1 Ch ip2

Ch ip 0 Ch ip1 Ch ip2 Ch ip3

DAVout0

DAVout1

DAVout2

DAVout3

RENout0

RENout1

RENout2

RENout3

DataOut0

DataOut1

DataOut2

DataOut3

Daisy ChainOne chip is Master - can generate 50MHz clock

All DAV (data available) signal are ORed as they pass down chain

REN (readout enable) signals stay high until sequence complete

Master finishes the readout cycle once the REN signal returns from the end

Data can be Manchester Coded to allow for capacitive coupling from HV domain

Programmable number of data packets per chip (0-255)

Binary

MC

CLK50MHz

Ma

ste

r

MC output

9 -b i ts - 0 07 -b i ts - 0 14 -b i ts - 0

2 start bits (11)

10 bit chip address

7 bit channel address

15 bit timestamp

12 bit ADC data

1 hi

t bit

1 st

op b

it (0

)

11 -b i ts - 0

1 2 3 4 5 6 7 98 10 11 12 13 14 15 16 17 1918 20 21 22 23 24 25 26 27 2928 30 31 32 33 34 35 36 37 3938 40 41 42 43 44 45 46 47 48

Data Format

Start bits “11”

10 bit chip address

7 bit channel address

15 bit timestamp

12 bit ADC data

1 bit hit status

Stop bit “0”

Timestamp correction If Hit Bit =1 - Indicates the timestamp comparator has fired

If Hit Bit = 0 - Indicates the timestamp comparator has not fired

In this case the timestamp is generated by the slower energy comparator and needs correcting

Timestamp threshold has to be set higher than energy due to noisier chain

In case of small signals, the timestamp may not fire. In case of large signals when reading neighbours (charge sharing)

Example – channels 16 and 24 are hit and have correct timestamp (274)

Neighbours timestamps are generated by the energy comparator which is passed to the neighbours (285)

Trimming of Energy Threshold

Before trimming After trimming

Channel Number

Th

resh

old

Se

ttin

g

118

138

128

158

148

98

108

0 20 40 60 80 100 120

Channel Number

118

138

128

158

148

98

108

0 20 40 60 80 100 120

Th

resh

old

Se

ttin

g

Sweep threshold across noise and histogram number of hits for each channel

No

rma

lise

d c

ou

nt

Threshold

x10Amp

Shaper

Vbias

Trim

HIT

LinearityA

DC

cod

e

Test pulse amplitude code

HolesElectrons

Non-Linearity

Non-linearity <1 %

Obtained using the on-chip test pulse circuit

ADC Non-linearity

INL = 2LSB

DNL = 0.6 LSB

Obtained by bypassing the front end

Noise

Energy(keV)

Input Capacitance (pF)

Noise measured at output of ADC with ADC noise removed

Test with mixed-alpha source

Source position in middle of detctor

Vacuum (2.5x10-7 bar)

N-side is face up, P-side face down

Test with mixed-alpha source

N-side P-side

No charge sharing corrections

Can identify the three energy peaks on the N-side

Present status of the R3B ASIC

R3B ASIC is under test in conjunction with the silicon sensors

Channel readout and daisy chaining are fully functional

It’s possible to trim the comparators for energy and timestamp

ADC is operational with no missing codes - INL 2LSB, DNL 0.6LSB

Linearity is good to 99%

Noise: 7keV (RMS) for short strips, 20keV for long strips at 2s shaping

Timestamp working

Daisy chaining fully functional

Tests are continuing

Present status of the R3B Tracker

4 full outer detectors with 32 ASICs on each are complete4 chains per side of detector, 2 are fully bonded, tested and workingInner layer and one outer layer will be fully assembled and tested by March 20163rd layer will be added at a later date

Thanks to the R3B tracker collaboration

Contact Details

Lawrence JonesIC Design Engineer, ASIC Design Group

Science and Technology Facilities CouncilRutherford Appleton Laboratory,Harwell Campus,DidcotOX11 0QXUnited Kingdom

Tel +44(0)1235 446508 Fax +44(0)1235 445008Email: lawrence.jones@stfc.ac.uk

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