97 digital electronics chap10 lecture 2 bjt

8/18/2019 97 Digital Electronics Chap10 Lecture 2 BJT

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Chap.10 Digital Integrated Circuits


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10-1 Introduction — Logic IC

ASIC:

Application Specific Integrated Circuits

ASIC:

Application Specific Integrated Circuits


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10-1 Introduction

IC di'ita( (o'ic fa&i(ie% ) RTL Re%i%tor-tran%i%tor (o'ic

) DTL Diode-tran%i%tor (o'ic ) TTL Tran%i%tor -tran%i%tor (o'ic ) ECL E&itter-cou*(ed (o'ic )

!"

eta(-o+ide %e&iconductor ) C !" Co&*(e&entar, eta(-o+ide%e&iconductor


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Positve logic and Negative logic

o%iti.e (o'ic/ i% %et to e inar, 1

e'ati.e (o'ic/ L i% %et to e inar, 1


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10-2 Feature

T e feature to e concerned of IC (o'ic fa&i(ie%/ ) fan-out

T e no of %tandard (oad% can e connected to t e out*ut of t e 'ateit out de'radin' it% nor&a( o*eration

"o&eti&e% t e ter& loading i% u%ed ) o er di%%i*ation

T e *o er needed , t e 'ateE+*re%%ed in &

) ro*a'ation de(a,

T e a.era'e transition-delay ti e for t e %i'na( to *ro*a'ate fro&in*ut to out*ut en t e inar, %i'na( c an'e% in .a(ue ) oi%e &ar'in

T e un anted %i'na(% are referred to a% noise oi%e &ar'in i% t e a!i u noise added to an in*ut %i'na( of adi'ita( circuit t at doe% not cau%e an unde%ira (e c an'e in t e

circuit out*ut


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Co puting "an-out

89&in: IL

#L

I$

#$

I

I

I

I out Fan =−


8/32 William Kleitz Di'ita( E(ectronic% it ; DL9


9/32 William Kleitz Di'ita( E(ectronic% it ; DL9


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Po er dissipation

CC CC D

CCLCC$ CC

4 avg I avg P

I I avg I

×=

+=

8:8:

28:

>74008:

>8:

391

TTL%tandardFor

=

=

==

IC inavg P 5otal

avg P

3 I 3 I

D

D

CCLCC$


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Propagation delay

50? ;

50? ;

50? ;

50? ;

For %tandard TTL

>8:

1197=

==

avg t

nst nst

P

PL$ P$L


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#ther delay ti es

) Ri%e Ti&e

fro& 10? u* to $0? (e.e( ) Fa(( Ti&e

fro& $0? do n to 10? (e.e(


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Noise argin


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Noise argin

i' -%tate noi%e &ar'in@0 4

Lo -%tate noi%e &ar'in@0 4


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10-6 Feature o" 7 5

BJT ) n*n or *n*

) "i or Ae ) "i i% u%ed &ain(, ) n*n i% &o%t *o*u(ar


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5a'le 10-15ypical npn 5ransistor Para eters

Re'ion ; BE :;8 ; CE :;8 CurrentRe(ation

Cutoff 0 6 !*encircuit

IB@IC@0

cti.e 0 6-0 7 0 # IC @ FEIB

"aturation 0 7-0 # 0 2 IB IC FE


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Feature o" npn-type 7 5

$ 4 L4

4

4 Lh

4 $ 8 ,

4 4 8 ,

ii

o

F(

7

CC C

==

=

==

=Ω=

=Ω=

andfor

>Find

20950

5922

591


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Diode 9 sy 'ol and characteristic


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10- ,5L and D5L circuits

RTL ) Re%i%tor TL

) L/ 0 2;9 / 1G3 6;DTL ) Diode TL ) L/ 0 2;9 / 4G5;


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,5L--N#,


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D5L--N3ND


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:odi"ied D5L


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10- 5ransistor-5ransistor Logic :TTL8

T e ori'ina( a%ic TTL 'ate a% a %(i' ti&*ro.e&ent o.er t e DTL 'ateT ere are %e.era( TTL %u fa&i(ie% or %erie% of t eTTL tec no(o',Ei' t TTL %erie% a**ear in Ta (e 10-2

a% a nu& er %tart it 74 and fo((o % it a%uffi+ t at identifie% t e %erie% t,*e9 e ' 7404974"#69 74 L"161T ree different t,*e% of out*ut confi'uration%/ ) 1 o*en-co((ector out*ut ) 2 Tote&-*o(e out*ut )

3 T ree-%tate :or tri%tate8 out*ut


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#pen-collector 55L ;ate


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#pen-Collector ;ates For ing a Co on 7us Line

In t i% ca%e

H @ >


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55L ;ate ith 5ote -Pole #utput


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+chott8y 55L ;ate


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5hree-state 55L ;ate


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10-& ( itter-Coupled Logic =(CL>

on%aturated di'ita( (o'ic fa&i(,ro*a'ation rate a% (o a% 1-2n%

%ed &o%t(, in i' %*eed circuit% oi%e i&&unit, and *o er di%%i*ation i% t e or%t ofa(( (o'ic fa&i(ie%

i' (e.e( -0 #;9 Lo (e.e( -1 #;

Inc(udin' ) Differentia( in*ut a&*(ifier ) Interna( te&*erature and .o(ta'e co&*en%ated ia% net or ) E&itter-fo((o er out*ut%


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(CL 7asic ;ate


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;raphic +y 'ols o" (CL ;ates

97 digital electronics chap10 lecture 2 bjt

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