9.1

Lab 8: A Calculator Using Stack Memory

• A simple computer design example• A control unit (FSM)• Changes from Lab 7

– use single port RAM– modify the datapath– a different control unit

• NO (fetch + push)• NO (fetch + exec + pop)

9.2

The block diagram of Lab 7• A dual-port RAM

Dual-portRAM

IR B A

ALU

stack

inst.

Stackpointer

Programcounter mux mux

9.3

Design Changes• Modify the block diagram

– datapath

– controls require a few changes

• push/pop and fetch cannot be done in parallel

– mux controls

– clk_en for registers and counters

Single-port

RAMIR B A

ALU

stack

inst.

Stackpointer

Programcounter mux mux

mux

9.4

• Single-port RAM– 16 * 9 bits

– inputs• DI: data input• WE: write_enable (active high)• WCLK: synchronous RAM -

positive-edge triggered• A: address

– outputs• DO: Data output

• RAM_ADDR– Fetch: PC

– PUSH_POP_ ==1: STP

– PUSH_POP_ ==0: STP-1

9.5

• Stack pointer (no change)– push/write operation

• address = stack pointer ++

– pop/read operation• address = -- stack_pointer

• Program counter– except that CLK_EN needs to be

controlled

– CLK_EN is activated when an instruction is fetched

9.6

Data Flow

9.7

Controls• Inputs

– RESET: power-on reset

– IR: instruction register

– STP: stack pointer

• Outputs– AB_SEL: select the inputs for

registers A and B

• 0/1= push/pop (exec)

– A_CLK_EN, B_CLK_EN• Latch regs A and B

– EOF_ = ~(IR == 1FF)

– ERROR_: syntax error

– IR_CLK_EN: latch IR and PC ++

– STP_up_dn_: 0/1 = pop/push

– STP_CLK_EN: real push/pop

9.8

Operations and Controls• Operations

– fetch– shift– push– pop– execution

• fetch: IR_CLK_EN• shift: B_CLK_EN, (A_CLK_EN), !AB_SEL• push: STK_UP_DN_, STK_CLK_EN• pop: !STK_UP_DN_, STK_CLK_EN,

A_CLK_EN, AB_SEL• execution: AB_SEL, B_CLK_EN• halt: ! All_CLK_EN

9.9

The Control Unit of Lab 7• States

– S0– S1

• IR– S2

• IR, B– S3

• IR, B, A– S4

• IR, B, A, STK– Error– Halt

• Operations– fetch– shift– push/pop– execution

OPR

Fetch, sh_AB ,push

9.10

The Control Unit of Lab 8• States that need no changes

– S0

– S1: IR– S2: IR, B– Halt– Error

• States that need changes– S3: IR, B, A– S4

• Design options– After an execution

• To fetch or to pop?

Need to be changed !!

9.11

Final Design

9.12

Operations• Pipelining (sort of)

– Fetch Exec– Fetch Exec– but,

• Fetch is stalled, if execution requires memory access• in this case, execution may require two clock cycles

– one for operand fetch; the other for execution

• Execution– operation code

• if REGA, execute the operation ( and fetch in parallel)• else pop data from the stack to A register (fetch is

stalled), and execute in the next clock cycle (and fetch in parallel)

– data• if A register contains data, push to the stack (a memory

write)– fetch is stalled

• IR->B->A