8834.system software 1

7/30/2019 8834.System Software 1

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Introduction to System Software

System Software

1

Kuldeep Sharma ,Assistant Professor, CSED, Chitkara University, Himachal Pradesh


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System Software

Application software

used by end-user

System software

text editor, compiler, debugger

machine dependent

A system software programmer must know thetarget machine structure

2 www.chitkara.edu


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Basic Features and Design Options

Fundamental features

regardless of what machine is being used.

Major design options

a software designer needs to be aware of theavailable options in order to make intelligentdecisions

3 www.chitkara.edu


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System Software

and Machine Architecture

Machine dependent system software

Machine code

Instruction formats

Addressing mode

Registers

Machine independent system software

Code optimization

General design and logic of an assembler

4 www.chitkara.edu


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Simplified Instructional Computer

System Software

5



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The Simplified Instructional Computer

(SIC)

SIC is a hypothetical computer that includes the

hardware features most often found on real machines

Two versions of SIC

standard model XE version

The two versions have been designed to be upwardcompatible.

6 www.chitkara.edu.in


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SIC Machine Architecture - 1

Memory

8-bit bytes

3 consecutive bytes form a word

215 bytes in the computer memory

Registers(each register is 24 bits in length)

Mnemonic Number Special use

A 0 Accumulator; used for arithmetic operations

X 1 Index register; used for addressing

L 2 Linkage register; JSUB

PC 8 Program counter

SW 9 Status word, including CC



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SIC Machine Architecture - 2

Data Formats

Integers are stored as 24-bit binary numbers;

2s complement used for negative values

No floating-point hardware

Instruction Formats

Addressing Modes

opcode (8) address (15)x

Mode Indication Target address calculation

Direct x=0 TA=address

Indexed x=1 TA=address+(X)



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SIC Machine Architecture 3

Instruction Set

load and store: LDA, LDX, STA, STX, etc.

integer arithmetic operations: ADD, SUB, MUL, DIV, etc.

comparison: COMP

conditional jump instructions: JLT, JEQ, JGT

subroutine linkage: JSUB, RSUB

Input and Output

Input and output are performed by transferring 1 byte at atime to or from the rightmost 8 bits of register A

The Test Device (TD) instruction tests whether theaddressed device is ready to send or receive a byte of data

Read Data (RD)

Write Data (WD)



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SIC Programming Examples



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Data movement No memory-memory move instruction

3-byte word: LDA, STA, LDL, STL, LDX, STX

1-byte: LDCH, STCH Storage definition

WORD, RESW

BYTE, RESB



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Arithmetic

Arithmetic operations are performed usingregister A, with the result being left in register A

Looping (TIX)

(X)=(X)+1 compare with operand

set CC



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SIC/XE

SIC is upwards compatible with SIC/XE.

Memory arranged in bytes (Max = 220 bytes).

Can do floating point arithmetic.

Has more registers.

Has additional addressing modes.

Can do I/O in parallel with computation.


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RegistersMnemonic Register Comment

3 B Base Register (for addressing)

4 S General Purpose Register

5 T General Purpose Register

6 F Floating point Accumulator (48-bits)


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Data Formats

SIC/XE supports integers and characters in

the same manner as SIC.

Introduces new 48-bit floating point type.

1-bit sign bit

11-bit exponent

36-bit fraction


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Floating point format in SIC/XE

0


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Instruction Formats

Number of addresses is larger. (220 as compared to 215).

Some instructions do not require operands.

Format 1:

Format 2:

Format 3:

Format 4:

Op (1 byte)

Op (1 byte) R1 R2

Op (6 bit) n bxi p e Disp (12 bit)

Op (6 bit) n bxi p e Address(20 bit)


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Formats (contd)

n=1, i=0: The word at the target address is the

address of the operand.

n=0,i=1: The address is used as the operand.

n=i: value at address is taken as operand. (backwardcompatibility with SIC when used in Format 3)

x=0,1: enables/disables Indexed mode (as in SIC).


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Formats (contd)

b=1,p=0: Implies Base Relative Mode .

b=0,p=1: Implies Program Counter RelativeMode.

e determines whether mode 3 or mode 4 isin use.

e=0: Mode 3 is in use. e=1: Mode 4 is in use.


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Addressing Modes

Base Relative: b=1, p=0

Target Address = B + disp

Program Counter Relative: b=0,p=1

Target Address = PC+disp

If b=p=0, then the address/disp field is taken as theaddress.

Indexed addressing may be used with both these modes(x=0,1).


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Instructions

Instructions to Load/Store new registers

LDB, STB,

Floating point Arithmetic

ADDF, SUBF, MULF, DIVF

Register Instructions

ADDR, SUBR, MULR, DIVR, RMO

I/O instructions TIO, SIO, HIO


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SIC/XE Machine Architecture

Input/Output

SIO, TIO, HIO: start, test, halt the operation of I/Odevice .

data movement

immediate addressing for SIC/XE

Looping (TIXR)

(X)=(X)+1

compare with register specified set CC



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SIC Programming Example



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Complex Instruction Set Computers

System Software

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Traditional (CISC) Machines

Complex Instruction Set Computers (CISC)

complicated instruction set

different instruction formats and lengths

different addressing modes e.gVAX (1978) or PDP-11(1970) from

DEC(Digital Equipment Corporation)

e.g. Intel x86 family



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VAX Architecture - 1

Virtual Address EXtension

Memory All addresses arebyte address

word (2bytes), longword(4bytes),

quadworad (8bytes),octaword (16bytes)

All VAX programs

operate in avirtual addressspace of 232 bytes

One half is used forsystem space

The other half is calledprocess space, and isdefined for each program

VAX A hit t 2


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16 general purpose registers:R0~R15

each register is 32-bit long

R15 (PC): Program Counter

R14 (SP): Stack Pointer R13 (FP): Frame Pointer

R12 (AP): Argument Pointer

R6~R11: general

R0~R5: are used by some

instructions PSL: process status longword

Registers

Data Formats


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Data Formats

Integers: byte, word, longword, quadword, or octaword

Negative integers: 2s complement representation

Floating-point: 4~16bytes

packed decimal: (C:positive, D:negative, F:unsigned)

zoned decimal: (digits are represented with ASCII codes)

e.g. +53842, 53842C (packed), 35333834C2 (zoned)

e.g. -6071, 6071D(packed), 363037D1

numeric format: trailing numeric, leading separate numeric

4 4 4 4 4 S

0011 4 0011 4 S 4


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Instruction Formats

variable -length instruction format

Addressing Modes

register mode

register deferred mode

autoincrement and autodecrement modes

several base relative addressing modes

program-counter relative modes

indirect addressing mode (called deferred modes)

immediate operands


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VAX Architecture -5

Instruction Set

Goal: symmetric with respect to data type The instruction mnemonics are formed by

a prefix that specifies the type of operation

a suffix that specifies the data type of the operands

a modifier that gives the number of operands involved

e.g. ADDW2, MULL3, CVTWL

A single instruction for

saves a designated set of registers

passes a list of arguments to the procedure maintains the stack, frame, and argument pointers

sets a mask to enable error traps for arithmetic operations


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VAX Architecture -6

Input and Output

I/O device controllers

Each controller has a set of control/status anddata registers, which are assigned locations inthe physical address space (called I/O space)

No special instructions are required to accessregisters in I/O space

The association of an address in I/O space

with a physical register in a device controlleris handled by the memory managementroutines


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Pentium Pro Architecture - 1

Memory

physical level: byte addresses, word, doubleword

logical level: segments and offsets

The segment/offset address specified by theprogrammer is translated into a physical addressby the x86 MMU(Memory Management Unit)


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Registers

General-purpose registers:( 32-bit Long)

EAX, EBX, ECX, EDX: data manipulation

ESI, EDI, EBP, ESP: address

Special-purpose registers:

EIP: pointer to next instruction

FLAGS: status word

CS: code segment register

CS contains the currently executing code

SS: stack segment register

SS contains address of current stack segment

DS, ES, FS, and GS: Addresses of data segments

Segment Registers are used to locate segments in memory Floating-point unit (FPU):

it contains eight 80-bit data registers

Registers reserved for system programs

16-bit segment registers


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Data Formats

Integers: 8-, 16-, 32-bit binary numbers

negative values: 2s complement

FPU can also handle 64-bit signed integers

The least significant part of a numeric value is stored at thelowest-numbered address (little-endian)

binary coded decimal (BCD)

unpacked: 0000____0000____0000____...0000____

packed: |____|____|____|____|____|____|..|____|____|

Floating-point data formats

single-precision: 32 bits=24+7-bit exponent+sign bit double-precision: 64 bits=53+10-bit exponent+sign bit

extended-precision: 80 bits=64+15-bit exponent+sign bit

h


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prefix(optional) containing flags that modify the

operation of instruction specify repetition count, segment register, etc.

opcode (1 or 2 bytes)

operands and addressing modes

InstructionFormats

TA=(base register)+(index register)*(scalefactor)+displacement

base register: any general-purpose registers

index register: any general-purpose registers except ESP

scale factor: 1, 2, 4, 8 displacement: 8-, 16-, 32- bit value

eight addressing modes

Addressing

Modes

i hi


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400 different machineinstructions

R-to-R instructions, R-to-Minstructions, M-to-M instructions

immediate values,

special purposeinstructions for high-levelprogramming language

entering and leaving procedures,

checking subscript values againstthe bounds of an array

Input is performed byinstructions that transferone byte, word, ordoubleword from an I/Oregister EAX

Repetition prefixes allowthese instructions totransfer an entire string ina single operation

Instruction

Set

Inputand

Output


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Reduced Instruction Set Computers

System Software

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RISC M hi


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RISC Machines

Three RISC machines

SPARCfamily

PowerPCfamily

Cray T3E

Ult SPARC 1


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UltraSPARC - 1

Sun Microsystems (1995)

SPARC stands for scalable processor architecture

SPARC, SuperSPARC, UltraSPARC

Memory Registers

Data formats

Instruction Formats

Addressing Modes

Ult SPARC 2


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UltraSPARC - 2

Byte addresses

two consecutive bytes form halfword

four bytes form a word

eight bytes form doubleword

Alignment

halfword are stored in memory beginning at byte address that aremultiples of 2

words begin at addresses that are multiples of 4

doublewords at addresses that are multiples of 8

Virtual address space

UltraSPARC programs can be written using 264 bytes

Memory Management Unit

Ult SPARC 3


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UltraSPARC - 3

~100 general-purpose registers any procedure can access only 32 registers

(r0~r31)

first 8 registers (r0~r8) are global, i.e. theycan be access by all procedures on thesystem (r0 is zero)

other 24 registers can be visualized as awindow through which part of the registerfile can be seen

program counter (PC)

the address of the next instruction to beexecuted

condition code registers

other control registers

Registers

Ult SPARC 4


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UltraSPARC - 4

integers are 8-, 16-, 32-, 64-bit binarynumbers

2s complement is used for negative values

support both big-endian and little-endianbyte orderings

(big-endian means the most significantpart of a numeric value is stored at thelowest-numbered address)

three different floating-point data formats

single-precision, 32 bits long (23 + 8 + 1)

double-precision, 64 bits long (52 + 11 +

1) quad-precision, 78 bits long (63 + 16 + 1)

DataFormats

Ult SPARC 5


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UltraSPARC - 5

Three Instruction Formats

32 bits long

the first 2 bits identify whichformat is being used

Format 1: call instruction

Format 2: branch instructions Format 3: remaining instructions

Ult SPARC 6


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UltraSPARC - 6

Addressing Modes

immediate mode

register direct mode

memory addressing

Mode Target address calculation

PC-relative* TA= (PC)+displacement {30 bits,signed}

Register indirect TA= (register)+displacement{13 bits, signed}

with displacement

Register indirect indexed TA= (register-1)+(register-2)

*PC-relative is used only for branch instructions

UltraSPARC 7


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UltraSPARC - 7

Instruction Set


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UltraSPARC - 8

Input and Output

a range of memorylocations is logicallyreplaced by device

registers

each I/O device hasa unique address, or

set of addresses

no special I/Oinstructions are

needed

PowerPC Architecture 1


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PowerPC Architecture - 1

POWER stands for

PerformanceOptimization withEnhanced RISC

History

IBM (1990) introduced POWERin 1990 with RS/6000

IBM, Apple, and Motorolaformed an alliance to develop

PowerPC in 1991 The first products were

delivered near the end of 1993

Recent implementationsinclude PowerPC 601, 603, 604



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Memory

halfword, word, doubleword, quadword

may instructions may execute moreefficiently if operands are aligned at astarting address that is a multiple of theirlength

virtual space 264 bytes

fixed-length segments, 256 MB fixed-length pages, 4KB

MMU: virtual address -> physical address



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Registers

32 general-purpose registers, GPR0~GPR31

FPU

condition code register reflects the result of certainoperations, and can be used as a mechanism for testing andbranching

Link Register (LR) and Count Register (CR) are used bysome branch instructions

Machine Status Register (MSR)



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PowerPC Architecture -4

Data Formats

integers are 8-, 16-, 32-, 64-bit binary numbers

2s complement is used for negative values

support both big-endian (default) and little-

endian byte orderings three different floating-point data formats

single-precision, 32 bits long (23 + 8 + 1)

double-precision, 64 bits long (52 + 11 + 1) characters are stored using 8-bit ASCII codes



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Seven Instruction Formats

32 bits long

the first 6 bits identify specify the opcode

some instruction have an additional extended opcode

the complexity is greater than SPARC

fixed-length makes decoding faster and simple than VAX andx86



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Addressing Modes

immediate mode, register direct mode memory addressing


Register indirect TA=(register)

Register indirect with indexed TA=(register-1)+(register-2)

Register indirect with TA=(register)+displacement {16 bits,signed}

immediate indexed

branch instruction


Absolute TA= actual address

Relative TA= current instruction address + displacement {25 bits, signed}

Link Register TA= (LR)

Count Register TA= (CR)



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PowerPC Architecture- 7

Instruction Set

200 machine instructions

more complex than most RISC machines

e.g. floating-point multiply and add instructionsthat take three input operands

e.g. load and store instructions may automaticallyupdate the index register to contain the just-computed target address

pipelined execution

more sophisticated than SPARC

branch prediction



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Input and Output two different modes

direct-store segment: map virtual address space toan external address space

normal virtual memory access

Cray T3E Architecture - 1


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Cray Research, Inc. (1995)

Massively parallel processing system (MPP)

Scientific computing

T3E

16~2048 processing elements (PE)

three-dimensional network

each PE consists of a DEC Alpha EV5 RISCmicroprocessor, local memory, and performance-accelerating control logic



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Local Memory

64MB ~ 2GB

physically distributed, logically sharedmemory

byte, word, longword, quadword

64-bit virtual addresses



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32 general-purposeregisters,GPR0~GPR31

32 floating-pointregisters, F0~F31

F31 always containthe value zero

program counter PC

other status and

control registers

Registers



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y

Data Formats

two different types of floating-point dataformats

one for compatibility with VAX

the other for IEEE standard formats characters are stored using 8-bit ASCII codes

since there are no byte load or storeoperations, characters that are to bemanipulated separately are usually storedone per longword



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Cray T3E Architecture 5

Five Basic Instruction Formats

32 bits long

the first 6 bits identify specify the opcode

some instruction have an additional function field

Cray T3E Architecture- 6


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y

Addressing Modes

immediate mode, register direct mode memory addressing


PC-relative TA=(PC)+displacement {23bits, signed}

Register indirect with TA=(register)+displacement{16 bits, signed}

displacement

register indirect with displacement mode is used for load and

store operations and for subrountine jumps PC-relative mode is used for conditional and unconditionalbranches



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y

Instruction Set

130 machine instructions

no byte or word load and store instructions


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CISC vs RISC

System Software

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CISC


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Complex Instruction Set Computer

Large number of complex instructions

Low level

Facilitate the extensive manipulation of low-level computational

elements and events such as memory, binary arithmetic, andaddressing.

CISC Examples


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p

Examples of CISC processors are the

System/360(excluding the 'scientific' Model 44),

VAX,

PDP-11,

Motorola 68000 family

Intel x86 architecture based processors.

Pros


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Pro s

Emphasis on hardware

Includes multi-clock complex instructions

Memory-to-memory:"LOAD" and "STORE are incorporated

in instructions

Small code sizes, high cycles per second

Transistors used for storing complex instructions

Cons


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Con s

That is, the incorporation of older instruction sets into newgenerations of processors tended to force growing complexity.

Many specialized CISC instructions were not used frequentlyenough to justify their existence.

Because each CISC command must be translated by the

processor into tens or even hundreds of lines of microcode, ittends to run slower than an equivalent series of simplercommands that do not require so much translation.

The CISC Approach


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The CISC Approach

MULT 2:3, 5:2

RISC


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RISC

Reduced Instruction Set Computer

Small number of instructions

instruction size constant

bans the indirect addressing mode

retains only those instructions that can be overlapped andmade to execute in one machine cycle or less.

RISC Examples


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RISC Examples

Apple iPods (custom ARM7TDMI SoC)

Apple iPhone (Samsung ARM1176JZF)

Palm and PocketPC PDAs and smartphones (Intel XScalefamily, Samsung SC32442 - ARM9)

Nintendo Game Boy Advance (ARM7)

Nintendo DS (ARM7, ARM9)

Sony Network Walkman (Sony in-house ARM based chip)

Some Nokia and Sony Ericsson mobile phones

Pros


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o s

Emphasis on software

Single-clock, reduced instruction only

Register to register:"LOAD" and "STORE are independentinstructions

Low cycles per second, large code sizes

Spends more transistors on memory registers

The RISC Approach


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pp

LOAD A, 2:3

LOAD B, 5:2PROD A, B

STORE 2:3, A

Performance


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Performance


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The CISC approach attempts tominimize the number ofinstructions per program,sacrificing the number of cycles perinstruction. RISC does the opposite,reducing the cycles per instructionat the cost of the number of

instructions per program.

8834.system software 1

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