87 ghz static frequency divider in an inp-based mesa dhbt technology
DESCRIPTION
87 GHz Static Frequency Divider in an InP-based Mesa DHBT Technology. S. Krishnan, Z. Griffith, M. Urteaga, Y. Wei, D. Scott, M. Dahlstrom, N. Parthasarathy and M. Rodwell Department of Electrical and Computer Engineering, University of California, Santa Barbara. - PowerPoint PPT PresentationTRANSCRIPT
87 GHz Static Frequency Divider in an InP-based Mesa DHBT Technology
S. Krishnan, Z. Griffith, M. Urteaga, Y. Wei,
D. Scott, M. Dahlstrom, N. Parthasarathy and M. Rodwell
Department of Electrical and Computer Engineering,
University of California, Santa Barbara
[email protected] 805-893-8044 GaAsIC, October 2002—Monterey, CA
Why Static Frequency Dividers (SFD)?
MS flip-flops are very widely-used high speed digital circuits:Master-Slave Flip-Flop with inverting feedback
Connection as 2:1 frequency divider provides simple test method
Standard benchmark of logic speed: Performance comparisons across technologies
Dynamic, super-dynamic, frequency dividers: Higher maximum frequency than true static dividers Narrow-band operation more limited applications
High Speed technology performance: HRL: > 100 GHz divider—this conference with E2CL
UCSB: 75 GHz static dividers using InAlAs/InGaAs TS-HBTsHRL: 72.8 GHz static dividers using InAlAs/InGaAs HBTs
• f does not predict logic speed
• fmax does not predict logic speed
• Large signal operation involves switching time constants
Why Static Dividers, and what makes them fast
clock clock clock clock
inin
out
out
MS latch: key digital element : resynchronizes data to clock often sets system maximum clock
ctsinterconne and , ,,
,
, ,
:include sdelay termt Significan
logiccbcb
logiclogic
excbbjebcbi
b
jecb
RCRCRC
V
IR
I
VC
I
VC
Mesa DHBT Epitaxial Layer Structure
InP Emitter n+ doped
P+ InGaAs Base: 52 meV Band gap grading
2000 Å n- InP Collector
Material Doping (cm-3) Thickness ()
n-InGaAs 1∙1019 300
n-InGaAlAs 1∙1019 90
n-InP 1∙1019 900
n-InP 8∙1017 300
n-InGaAlAs 8∙1017 233
p-InGaAlAs 2∙1018 66
p-InGaAs 4∙1019 (Be) 400
n-InGaAs 2.25∙1016 100
n-InGaAlAs 2.25∙1016 240
n-InP 5.66∙1018 30
n-InP 2.25∙1016 1630
n-InGaAs 1∙1019 250
n-InP 1∙1019 1250
InP SI N/A
mesaIC Process: Key Features
Slide 1
mesaIC Process: Key Features
Slide 2
mesaIC Process: Key Features
Slide 3
mesaIC Process: Key Features
Slide 4
mesaIC Process: Key Features
Slide 5
mesaIC Process: Key Features
Slide 6
mesaIC Process: Key Features
Slide 7
mesaIC Process: Key Features
Slide 8
mesaIC Process: Key Features
Slide complete
mesaIC Process: overview
• Both junctions defined by selective wet-etch chemistry
• Narrow base mesa allows for lowAC to AE ratio
• Low base contact resistance—Pd based ohmics with C < 10-7 ∙cm2
• Collector contact metal and metal ‘1’ used as interconnect metal
• NiCr thin film resistors = 40 /
• MIM capacitor, with SiN dielectric… -- used only for bypass capacitors
• Low loss, low r = 2.7 microstrip wiring environment
• Microstrip wiring environment….
• has predictable characteristic impedance
• controlled-impedance interconnects within dense mixed signal IC’s
• ground plane eliminates signal coupling that occurs through on-wafer gnd-return inductance
DC and RF measurements
• Common emitter characteristics• Device geometry: emitter metal = 0.7 8.0 m2, real device = 0.6 ∙ 7.0 m2
• Collector to emitter area ratio, AC / AE = 4.5
• f = 205 GHz, fmax = 210 GHz
• Measurement condition:VCE = 1.2 Volts, Jc = 2.5 mA/m2
• IB = 50 A per step
• DC beta = 20• Self heating present—not observed in previous runs with same material
Circuit diagram: Static Frequency Divider
Circuit Details….
• ECL topology
• JEF = 2.0 mA / m2
• Jsteering = 2.5 mA / m2
• VEE = - 4.5 Volts
• Microstrip interconnects
• Output voltage for acquire and hold components, V = 300mV
• Output buffer used for measurement isolation, Vout 300 mV
Hold ckt
Acquire ckt
clock clock
clockclock
out
out
Q1 Q2Q3 Q4 Q5 Q6
Q7 Q8
Q9Q10
Q11Q12
Q13 Q14
Q15Q15 Q16
Q1,Q2,Q5,Q6,Q9 & Q11 : 0.6*7 m2
Q3,Q4,Q7,Q8,Q10 & Q12 : 0.6*5 m2
device gemoetries : emitter junction areas
Q1,Q2,Q5,Q6,Q9 & Q11 : 1.7*11 m2
Q3,Q4,Q7,Q8,Q10 & Q12 : 1.7*9 m2
device gemoetries : collector junction areas
Component ValuesRef = 395 ohmRclk=220 ohmRclk,ef=280 ohmRin = 90 ohmRl = 90 ohmVee = -3.5 V
Ref RefRefRef
RefRefRefRef
Rclk
Rclk
Rclk,ef
Rclk,efRclk,ef
Rclk,ef
Rin Rin
Rin Rin
Rl
RlRl
Rl Rl
RlRl
Rl
Chip Photograph: 87 GHz Divider
Synthesizer clk Divider Output
DC bias
DC clkDevice Count = 32
Die Area = 0.7 x 0.7 mm2
Measurements: DC – 40 GHz setup
• Clock input 0 dm
• Divider Operation from 4 GHz to 40 GHz
• Measurement establishes fully static nature of divider
Output waveform @ 2 GHz; fclk = 4 GHz
VEE
DC clk
Out
Sampling oscilloscopeDC - 40 GHz Synthesizer
Clk
0 dm
Measurements: 50 – 75 GHz setup
Output waveform @ 37.5 GHz; fclk = 75 GHz
• Clock input 0 dm
• Divider Operation from 50 GHz to 75 GHz
VEE
DC clk
Out
Sampling oscilloscope
DC - 40 GHz Synthesizer
Clk
0 dmFrequency tripler
16.67 – 25 GHz
50 – 75 GHz
Measurements: 75 – 110 GHz setup
• Clock input 9.7 dm
• Divider Operation from 75 GHz to 87 GHz
Output waveform @ 43.5 GHz; fclk = 87 GHz
VEE
DC clk
Out
Sampling oscilloscopeClk
9.7 dm20 – 40 GHz Amp
Frequency tripler
75 – 110 GHz Amp
DC - 40 GHz Synthesizer
Conclusions
Accomplishments:• Demonstrated a fully static, static frequency divider in a
narrow triple-mesa DHBT process—up to 87 GHz
Future Direction:
• Reduce device parasitics (rex, rbb) and wiring capacitance
• Increased current density (JE) reduces
• Continued lateral scaling of base contact to decrease AE / AC ratio – lower CCB
Acknowledgements:
• This work was support by the Office of Naval Research (ONR--N00014-01-1-0024) and by Walsin Lihwa / UC
Core
C
logiccbload
logiccb
J
ΔVCR
I
ΔVC )(F/m2τ