8407 slides topic7-npc

7/22/2019 8407 Slides Topic7-NPC

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Topic 7

Multilevel Neutral Point Clamped (NPC) Inverters

Textbook: Bin Wu, High-Power Converters and AC Drives, Wiley-IEEE Press, 2006

Three-Level NPC Inverter Based MV Drive, Courtesy of ABB (ACS1000)

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Power Converter Systems

2

Topic 7Multilevel Neutral Point Clamped (NPC) Inverter


Lecture Topics

Three-level NPC Inverter

Space Vector Modulation

Neutral Point Voltage Control

High-level NPC Inverter

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Inverter Configuration

Clamping diodes: DZ1 and DZ2 (Phase A)

1dC

1S

2S

3S

4S

A

B

CZ

2dC

1D

2D

3D

4D

1ZD

2ZD

E

E

Zi

dV

Ai

OBi

Ci


Topic 7 Multilevel NPC Inverters

Three-Level NPC Inverter

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Switching State

Complementary Switch pairs:

S1and S3; S2and S4;

Device Switching Status(PhaseA)Switching

State

1S 2S 3S 4S

Inverter Terminal

Voltage

ZAV

P On On Off Off E

O Off On On Off 0

N Off Off On On E




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Gate Signal Arrangements

Inverter phase voltage vAZ has three levels: E, 0 and E

2

ONONONOPOPOPO

0

1gv

2gv

3gv

4gv

AZv

E+

E




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Inverter Output Waveforms

2

E+AZ

v

BZv

CZv

ABv

0

0

0

0

t

t

t

t

BZAZAB vvv =

E

E2+

E2

E+




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Space Vectors

Three-phase voltages

0)()()( =++ tvtvtvCOBOAO

Two-phase voltages

=

)(

)(

)(

3

4sin

3

2sin0sin

3

4cos

3

2cos0cos

3

2

)(

)(

tv

tv

tv

tv

tv

CO

BO

AO

Space vector representation

)()()( tvjtvtV

+=r

(2) (3)

[ ]3/43/20 )()()(32)(

j

CO

j

BO

j

AO etvetvetvtV ++=

r

where xjxe jx sincos +=

(3)

(1)

(2)

(4)



Space Vector Modulation (SVM)

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Switching state [POO] on-state switches:

Phase A: upper two switches [P]

Phase B: lower two switches [O]

Phase C: lower two switches [O]

dBOdAO VtvVtv

3

1)(,

3

2)( ==

dCO Vtv

3

1)( =and

Substituting (5) to (4) gives a space vector

(5)

(6)0

132 jdeVV =

r

Space Vectors (Example)

from which

Total switching states: 27

Total space vectors: 19




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Space Vectors Diagram

19 space vectors:

Zero vector: V0Small vectors: V1 V6Medium vectors: V

7 V

12Large vectors: V13 V18

dVV

3

213=r

6/

3

37

jedVV =r

3/

3

214

jedVV =r

0Vr

3Vr

2Vr

4Vr

5Vr

8Vr

6Vr

15Vr

18Vr

12Vr

11Vr

10Vr

9Vr

17Vr

16Vr

3/1 dVV =r




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SpaceVector

Switching State Vector ClassificationVector

Magnitude

0Vr

[PPP][OOO] [NNN] Zero Vector (ZV) 0

P-type N-type

PV1

r

[POO]1Vr

NV1

r

[ONN]

PV2

r

[PPO]

2Vr

NV2

r

[OON]

PV3

r

[OPO]

3Vr

NV3

r

[NON]

PV4

r

[OPP]

4Vr

NV4

r

[NOO]

PV5

r

[OOP]

5Vr

NV5

r

[NNO]

PV6

r

[POP]

6Vr

NV6

r

[ONO]

Small Vector (SV)

P-type Small Vector (PSV)

N-type Small Vector (NSV)

dV3

1

Switching States and Space Vectors

Redundancy: Zero vector three switching states

Small vectors two states per vector




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Space

VectorSwitching State Vector Classification

Vector

Magnitude

7Vr

[PON]

8Vr

[OPN]

9Vr

[NPO]

10Vr

[NOP]

11Vr

[ONP]

12Vr

[PNO]

Medium Vector (MV) dV

3

3

13Vr

[PNN]

14Vr

[PPN]

15Vr

[NPN]

16Vr

[NPP]

17Vr

[NNP]

18Vr

[PNP]

Large Vector (LV) dV3

2

No redundant switching states for medium or large vectors

Switching States and Space Vectors




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Sector Definition

1Vr

13Vr

7Vr

14Vr

0Vr

3Vr

2Vr

4Vr

5Vr

8Vr

6Vr

15Vr

18Vr

12Vr

11V

r

10Vr

9Vr

17Vr

16Vr

refVr

Vref: Reference vector, rotating in space at a certain speedAll other vectors are stationary




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SVM Principle

For a given length and position in space, Vref can be approximated

by three nearby stationary vectors;

Based on the chosen stationary vectors, switching states are

selected and gate signals are generated;

When Vrefpasses through sectors one by one, different sets of

switches are turned on or off;

When Vrefrotates one revolution in space, the inverter output

voltage varies one cycle over time;

The inverter output frequency corresponds to the rotating speed

of Vref;

The inverter output voltage can be adjusted by the magnitude of Vref.




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Dwell Time Calculation

4

bT PNNcT

bT

3

PON

PPN

PPO

OON

1

aT

ONN

POO

2

cT

39

13Vr

7Vr

1Vr

14Vr

0Vr

2Vr

refVr

aT

Use volt-second balancing principle

Select three nearest stationary vectors

721 and, VVVrrr

Sector I

=++

=++

scba

srefcba

TTTT

TVTVTVTVrrrr

271

Four Regions

Dwell time is the duty-cycle time

of selected switches during the

sampling period Ts .

(a)




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Dwell Time Calculation

=

+=

=

])3

(sin21[

]1)3

(sin2[

]sin21[

asc

asb

asa

mTT

mTT

mTT

Ta , Tb and Tc dwell times for V1 , V7and V2

d

ref

a

V

Vm 3= modulation index

From equation (a)




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Switching Sequence (Seven-segment)

General Design Requirements

a) The transition from one switching state to the next involves only

two switches in the same inverter leg, one being turned on and

the other turned off; and

b) The transition for Vrefmoving from one sector (or one region)

to the next requires no or minimum number of switchings.

Note:

The switching sequence design is not unique, but the above

requirements should be satisfied for switching frequency

minimization.




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Voltage Vector NV2r

7Vr

14Vr

PV2

r

14Vr

7Vr

NV2

r

Dwell Time4

cT

2

bT

2

aT

2

cT 2

aT

2

bT

4

cT

PhaseA O P P P P P O

PhaseB O O P P P O OSwitching

State

Phase C N N N O N N N

,0]O[,]P[ ==E E=]N[ .

Assuming Vrefis in Region 4 of Sector I,

three vectors are selected: V2 , V7and V14




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2

aT

BZv

AZv

CZv

E+

4

cT

2

bT

sT

ABv

E+

E

E+

2

cT

2

bT

4

cT

NV2r

7Vr

14Vr

PV2

r

14Vr

7Vr

NV2

r

2

aT

Switching sequence requirementa) is satisfied




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14Vr

15Vr

17Vr

18Vr

13Vr

16Vr

refVr

refVr

Switching sequence requirementb) is satisfied

2/2/ 1, fff spdevsw +=

ssp Tf /1=

Device switching frequency:

Sampling frequency:

Fundamental frequency:

1f




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AZv

ABv

0

1gv

4gv

0

2 3

Simulated Waveforms (Seven-segment)

f1 = 60Hz, Ts = 1/1080 sec,ma = 0.8, fsw = 570Hz

vAB is not half wave symmetrical; andcontains both even- and odd-order harmonics




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Simulated Waveforms (Seven-segment)

f1 = 60Hz, Ts = 1/1080 sec,ma = 0.8, fsw = 570Hz

dAZ VV n /

dAB VV n /




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dnAB VV /

am

am

dnAB VV /

Harmonic Content (Seven-segment)




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Laboratory Prototype at Ryerson




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Measured Waveforms

AZv

ABv

8.0)a( =am 9.0)b( =am

d

n

V

VAB

d

n

V

VAZ




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Measured waveforms (with even-order harmonic elimination)

AZv

ABv

8.0)a( =am 9.0)b( =am

d

n

V

VAB

d

n

V

VAZ




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Neutral Point Voltage Deviation

The neutral point voltage vz can be controlled byP- and N-types of small vectors

ZdV dV

dV dV

++

+ +

1dC

2dC

1dC

2dC

1dC

2dC

1dC

2dC

Zv

+

Zv

+

Zv+

Zv+

Zi

Zi

Z

ZZ

A

B

C

A

B

C

A

B

C

A

B

C

Zv]POO[affectednot]PPP[ Zv

Zv]ONN[ definednot]PON[ Zv

dV

+

Zv

+

1dC

2dC

Z

A

B

C

affectednot]PNN[ Zv




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aNaPa TTT +=

( )

( )

=

+=

tT

T

tT

T

aaN

aaP

12

12 11 T

Neutral Point Deviation

Level

Motoring Mode0>di

Regenerating Mode0 )( 21 0>t 0

)( 12 0t

ddd Vvv dV ).




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R is used on purpose to make the dc voltage unbalance.

1dv

(sec)t

)(V

21, dd vv

2dZ vv =

A

Z

2dv

Zi

dV

1dv

R




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Inverter Topologies

1S

2S

3S

1S

A

1D

22 D

2D

E

E

dV E

E

E

dV

E

E

A

2S

3S

21D

1S

2S

3S

4S

1S

2S

3S

4S

1D

X

22 D

33 D

31D

22 D

3D

X

Y

Y

Z

dC

dC

P

N

ANv ANv

N

P

Ai Ai



High Power NPC Inverters

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Switching State

Switch Status

Four-level Inverter

1S 2S 3S 1S 2S 3S

ANv

1 1 1 0 0 0 3E

0 1 1 1 0 0 2E

0 0 1 1 1 0 E

0 0 0 1 1 1 0

Five-level Inverter

1S 2S 3S 4S 1S 2S 3S 4S ANv

1 1 1 1 0 0 0 0 4E

0 1 1 1 1 0 0 0 3E

0 0 1 1 1 1 0 0 2E0 0 0 1 1 1 1 0 E

0 0 0 0 1 1 1 1 0




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Component Count

Voltage

LevelSwitches

Clamping

Diodes*

dc

capacitors

m 6(m-1) 3(m-1)(m-2) (m-1)

3 12 6 2

4 18 18 3

5 24 36 4

6 30 60 5

* The clamping diodes have the same voltage rating as

other switches.

Note:

The number of clamping diodes increases substantially

with the voltage level.




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IPD Modulation (four-level)

3gv

2gv

1gv

ANv

ABv

1crv

2crv

3crv

dAB VV n /




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Harmonic Content (four-level, IPD Modulation)

am

dAB VV n /




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APOD Modulation (four-level)

1crv

2crv

3crv

ABv

Ai

2 3

dn VVAB /




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Harmonic Content (four-level, APOD Modulation)

0.2 0.4 0.6aM

0.1

0.2

0.3

00

x

y 612.0=

x

y

n=1

n=13,17

n=11

n=19

0.8

d

n

V

VAB




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The 3-level NPC inverter widely used in MV drives

Main features

- Low device count

- Good harmonic profile

- Suitable for medium voltage operation

The practical use of 4- or 5-level NPC inverters not reported

Main reasons

- Difficulties in dc capacitor voltage control

- Large number of clamping diodes



Summary

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Topic 7

Multilevel Neutral Point Clamped Inverters

EE8407

8407 slides topic7-npc

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