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8253 Programmable Interval Timer

A Programmable Interval Timer (PIT) is a counter which triggers an interrupts when they reach their programmed

count. The 8253 consists of three counters: Counter 0, Counter 1, and Counter 2.

Each counter has 2 input pins:CLK (Clock Input) and GATE, and one pin for output:OUT.

Clock This is the clock input for the counter. The counter is 16 bits.

Out This single output line is the signal that is the final programmed output of the device.

Gate This input can act as a gate for the clock input line, or it can act as a start pulse, depending on the programmed

mode of the counter.

Three independent 16-bit programmable counters (timers).Each capable in of counting in binary or BCD

8253 Architecture

8253 Block Diagram

Data Bus Buffer : This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system data bus. TheData bus buffer has three basic functions.1. Programming the modes of 8253/54.2. Loading the count registers.3. Reading the count values.Read/Write Logic : The Read/Write logic has five signals : RD, WR, CS and the address lines A0 and A1 . In theperipheral I/O mode, the RD, and WR signals are connected to IOR and IOW, respectively. In memory-mapped I/O, theseare connected to MEMR and MEMW. Address lines A0 and A1 of the CPU are usually connected to lines A0 and A1 ofthe 8253/54, and CS is tied to a decoded address. The control word register and counters are selected according to thesignals on lines A0 and A1

signals on lines A0 and A1.

8253 Control word Format

8253 modes

Mode 0 : Interrupt on terminal count

1) The output will be initially low after the mode set operation.2) After the count is loaded into the selected count Registerthe output will remain low and the counter will count. 3) When the terminal count is reached the output will go high andremain high until the selected count is reloaded.

1) Gate = 1 enables counting.2) Gate = 0 disables counting.Note : Gate has no effect on OUT.

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Note : Gate has no effect on OUT.

MODE 1 : Hardware Retriggerable One-shot

1) The output will be initially high 2) The output will go low on the CLK pulse following the rising edge at the gate

input. 3) The output will go high on the terminal count and remain high until the next rising edge at the gate input.

MODE 2 : Rate generatorThis mode functions like a divide by-N counter.1) The output will be initially high.2) The output will go low for one clock pulse before the terminal count.

3) The output then goes high, the counter reloads the initial count and the process is repeated.4) The period from one output pulse to the next equals the number of input counts in the count register.

Gate Disable:1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ).2) If Gate goes low during an low output pulse, output is set immediately high.A trigger reloads the count and the normal sequence is repeated.

MODE 3 : Square Wave Rate Generator1) Initially output is high. 2) For even count, counter is decremented by 2 on the falling edge of each clock pulse. When

the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count andthe whole process is repeated.3) If the count is odd and the output is high the first clock pulse (after the count is loaded) decrements the count by 1.Subsequent clock pulses decrement the clock by 2. After timeout, the output goes low and the full count is reloaded. Thefirst clock pulse (following the reload) decrements the count by 3 and subsequent clock pulse decrement the count bytwo. Then the whole process isrepeated. In this way, if the count is odd, the output will be high for (n+1)/2counts and low for (n-1)/2 counts.

Gate Disable:If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while output is low, output is set highimmediately. After this, When Gate goes high, the counter is loaded with the initial count on the next clock pulse and thesequence is repeated.

MODE 4 : Software Triggered Strobe.

1) The output will be initially high 2) The output will go low for one CLK pulse after the terminal count (TC).

Gate Disable:If Gate is one the counting is enabled otherwise it is disabled. The Gate has no effect on the output.

MODE 5 : Hardware triggered strobe (Retriggerable).

1) The output will be initially high. 2) The counting is triggered by the rising edge of the Gate. 3) The output will go low forone CLK pulse after the terminal count (TC).If the triggering occurs on the Gate input during the counting, the initial count is loaded on the next CLK pulse and the

counting will be continued until the terminal count is reached.

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