80856 pin diagram - wikimedia commonsopcode 4f h is placed on data lines ale rd wr 0, 0, 1 74ls353...
TRANSCRIPT
80856 PIN DIAGRAM
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select
signal
0100 1111 (4F H)
ON
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
0100 1111 (4F H)
1 1 1ALE RD WR
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
µP Puts 2005 H address on Address BUS (A15-A0)
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0 µP Puts 2005 H address on Address BUS (A15-A0)
ENABLE of 2005 H Memory location (Register) gets 1
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
0100 1111 (4F H) 1 1 1ALE RD WR
0100 1111 (4F H) 1 1 1ALE RD WR
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as ADDRESS BUS ALONG WITH A15-A8
1 1 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as DATA BUS to read content of 2005 H
location
0 0 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
0
0100 1111 (4F H)
0 0 1ALE RD WR
0100 1111 (4F H)
DEMULTIPLEXING THE BUS AD7- AD0
AD7 - AD0 to be used as DATA BUS to read content of 2005 H
location
0 0 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-1 (FIRST CLOCK CYCLE)
1, 1, 1ALE RD WR Microprocessor Control Unit
Generates
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-1 (FIRST CLOCK CYCLE)
1, 1, 1ALE RD WR Microprocessor Places 2005 H Address on Address bus (A15 – A0)
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
1, 1, 1ALE RD WR
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-1 (FIRST CLOCK CYCLE)
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-2 (SECOND CLOCK CYCLE)
Microprocessor Control Unit generates: 0, 0, 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-2 (SECOND CLOCK CYCLE)
Microprocessor Control Unit generates: 0, 0, 1ALE RD WR
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-3 (THIRD CLOCK CYCLE)
Opcode 4F H is placed on data lines
0, 0, 1ALE RD WR
74LS353
OCTAL
LATCH
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-3 (THIRD CLOCK CYCLE)
Opcode 4F H is placed on data lines
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-4 (FOURTH CLOCK CYCLE)
Opcode 4F H goes to INSTRUCTION DECODER
And get Executed 0, 1, 1ALE RD WR
74LS353
OCTAL
LATCH
Ignoring Chip Select signal
MICROPROCESSOR COMMUNICATION & BUS TIMING
STEP-4 (FOURTH CLOCK CYCLE)
Opcode 4F H goes to INSTRUCTION DECODER
And get Executed 0, 1, 1ALE RD WR
/
34
IO M
PIN
0 & 1
29 &33
S S
PIN
8085 REMAINING PINS