80286Architecture- Introduction

Instruction Unit

(IU)

PIPELINING

BU

IU

EU

AU

BU

Performs all memory and I/O reads and writes,

Prefetches instruction bytes

Controls transfer of data to and from processor extension devices

IU

IU

Fully Decodes up to three prefetched instructions and holds them in a queue

Where the execution unit can access them

EU

EU

16-bit ALU to execute instructions

AU

Computes the physical addresses that will be sent out to memory or I/O by the BU

Base Reg

Protection

Info

Protection

Logic

Selected

Address

Execution Unit

Registers

ALU

Multiplier

BIU

Address

DriversData

Buffers

Instruction

Prefetch

Code

Queue

Instruction

Unit

Translator

Inst

Queue

Address Unit

Address

Information

Data

Instructions

Code

Decoded

Instructions

Address

Data

Control

80286Pin Out

80286A23 – A0

D15 – D0

BHE’

HOLD

HLDA

CLK

RESET

READY’

INTR

NMI

LOCK’

M/IO’

S1’

S0’

COD/INTA’

PEREQ

PEACK’

BUSY’

ERROR’

BUS CONTROL SIGNALS

COD/INTA’ M/IO’ S1’ S0’ Bus Cycle

0 0 0 0 INTA

0 0 1 1 None, Not a status cycle

0 1 0 0 HALT/SHUTDOWN(A1)

0 1 0 1 MEMR

0 1 1 0 MEMW

0 1 1 1 None, Not a status cycle

1 0 0 1 IOR

1 0 1 0 IOW

1 0 1 1 None, Not a status cycle

1 1 0 1 Instruction Read

1 0 1 1 None, Not a status cycle

REGISTERS

MSW

TS EM MP PE

Flag Register

NT IO PL OF DF IF TF SF ZF AF PF CF

80386PIN OUT

80386

A31 – A2

D31 – D0

BE0’

BE1’

BE2’

BE3'

HOLD

HLDA

CLK2RESETREADY’

BS16’

INTR

NMI

LOCK’

M/IO’

R’/W

D/C’

PEREQ’

BUSY’

ERROR’

NA’

ADS’

80386Architecture

80386 - ARCHITECTURE

BIU

Interface to the outside world -Responsible for Fetching instruction

Reading and writing of data for memory

Inputting and outputting of data for input/output peripherals

Information transfers over the microprocessor bus De-multiplexed bus

386DX

32-bit data bus

Real-mode: 20-bit address, 1M-byte physical address space

Protected-mode: 32-bit address bus, 4G-byte physical address space

PREFETCH UNIT

Instruction Stream queue

Whenever the queue is not full, prefetch the next sequential instructions

Queue—16-byte; 4-byte/memory cycle

Prioritizes bus accesses—data operands highest priority

FIFO instruction queue

Holds bytes of instruction code until the decode unit is ready to accept them

Bus unit “Idle state” - If queue is full and the execution unit is not requesting access to data in memory, BIU does not perform bus cycles

DECODE UNIT

Offloads the responsibility of instruction decoding from the execution unit.

Reads machine code instructions from the output side of the instruction queue

Decodes the instructions into the microcode instruction format used by the execution unit

Contains an instruction queue that holds 3 fully decoded instruction

Decoded instructions are held until requested by the execution unit

EXECUTION UNIT

Responsible for executing instructions

Arithmetic/logic unit (ALU)

Performs the operation identified by the instruction: ADD, SUB,AND, etc.

Flags register

Holds status and control information

General-purpose registers

Holds address or data information

Special multiply, shift, and barrel shift hardware

Accelerate multiply, divide, and rotate operations

SEGMENTATION & PAGING UNIT

Memory management & Protection Status

80486Architecture & Pin Out

ALU

BUS

INTERFACE

F.P. Register

File

Floating

point Unit

Register

File

Barrel

ShifterSegmentation

Unit

Descriptor

Register

Limit and

Attribuite PLA

Translation

Lookaside

Buffer

Paging Unit

8k Byte

Cache

Cache

Unit Address

Drivers

Write

Buffers

Data Bus

Treansceivers

Bus Control

Request

Sequencer

Burst Bus

Control

Bus Size

Control

Cache

Control

Parity Generation

and Control

Prefetcher

32 Byte Code

Queue

Instruction

Decode

Control and

Protection

test Unit

Control

Rom

Code

Stream

Physical

Address

Decode

Instruction

Path

Micro -

Instruction

32 – bit Data Bus

32 – bit Data Bus

Linear Address Bus

Base /

Index

Bus

Displacement Bus

32

32

32

3232

32

32

24

128

32

2

20

A2 – A 31

BE0# - BE3#

PCHK# DP0-DP3

KEN#

FLUSH#

AHOLD,

EADS#

D0 - D31

BRDY#

BLAST#

80486

A31 – A2

D31 – D0

BE0’BE1’BE2’BE3'

M/IO’R’/WD/C’

BS8’BS16’A20M’

ADS’

BREQBOFF’

CLK2RESETREADY’

HLDAHOLD

DP0’DP1’DP2’DP3‘PCHK’

BRDY’BLAST’

INTR

NMI

FLUSH’

KEN’

FERR’

IGNE’

PCDPWT

EADS’

AHOLD’

PLOCK

LOCK’