7th Int. Workshop

Applications in Electronics Pervading Industry, Environment & Society

APPLEPIES 201911-13 September, School of Engineering, University of Pisa, www.applepies.eu

Round Table:

Trend in Italy on EuroHPC & the European Processor Initiative

CINECA E4 STMicroelectronics UniBologna UniPisa

2021 – H2

PCIe board (WS compatible)

with < RHEA β version

ARM MPPA

eFPGA EPAC

HBM

memories

DDR

memories

PCIe gen5

linksHSL

links

D2D links

to adjacent

chiplets

EPAC

STX

VPU

VRP

Bridge to GPP

Bridge to GPP

UNIBO DEI EEES laboratory research excellence is on HW and SW co-design of energy-efficient computing system.

The HPC team’s research focuses on methods and tools for monitoring and power management of large-scale computing systems

The Compilers & Runtime team’s research focuses on the programming support for heterogenous computing systems

The Digital Design team’s research focuses on the design of cutting edge computing architectures and their silicon implementation

based on the parallel-ultra-low power (PULP) open-source hardware platform

The Edge AI team’s research focuses on the development of AI-enabled IoT and smart sensors systems and applications

UNIBO contribution to EPI

• UNIBO activities focus on the design of the HW and SW power management subsystem of the EPI processors.

• UNIBO activities focus on the design of the HW and programming support for offloading and supporting computation on the EPI

specialized accelerators.

CONTRIBUTION TO EPI

Power Controller

VRM

BMCPE

S

Operating System

Application

System Management / RM

GovernorsIn band

Hints/Prescription

Power Cap Energy vs. Througput

DIMM

RJ45

Syste

m M

anagem

ent

/ RM

Out of bandNode Power Cap

RAS

Main Archi. Blocks w. :- Sensors (PVT, Util, archi)- Controls (f,Vdd,Vbb,PG,CG)

- In band a.k.a low latency / user-space telemetry (power, perf, …)- O.S. PM governors:

- cpufreq/ cpuidle- Based on O.S. metrics- Slow & often unused

- Low latency PM requests and/or suggestions

- From the Application/run-time

- Power cap => Max perf @ P<Pmax- Energy => Min Energy @ f=f*- Throughput => F > Fmax @ T,P<Max

- Out-of-band – zero overhead telemetry

- Node Pcap – Max perf @ Pnode<Pmax- RAS – error and conditions reporting

EPI

chip

24

Private consortium under public control:

• 67 universities

• 9 public research entities

• 3 university hospitals

• MIUR Our numbers:

100M€ turnover

21th in the TOP500

800 employees

in BO, MI, Roma, NA

Main activities• Supercomputing for research• IT Support to MIUR• IT Support to universities• Technology transfer

•

•

•

•

•

•

25

CONTRIBUTION TO EPI

26

Japan (2022)

U.S. (2021-2023)

China (2021-2022)Xiaomi, ShenWei, Hygon

EuroHPC (2023)

Aurora 21 (Cray/Intel + GPUs)

Frontier (Cray/Intel + GPUs)

Fugaku (Fujitsu/ARM)

Hygon x86 (AMD-Chinese Joint Venture) + Manycore

accelerators (Matrix-2000+?)

27

2009 2012 2016 2019/2020 2021 2023-2025 2025-2027

IBM SP6

Power6

Fermi

IBM BGQ

PowerA2

Marconi

Lenovo

Xeon+KNL

Marconi

PPI4HPC

ICEI - PPIHBP

Leonardo

Pre-exascale with

EuroHPC

contribution

Post-Marconi

Exascale pilot

technology

Exascale with EuroHPC

Procurement in

progress

100TF1MW

2PF1MW

11PF+9PF

3.5MW

50PF+20PF

~4MW

20x

5x

5x

1x

(latency cores)

Paradigm

change

10x

(in total)

> 250 PF> 20PF

~10MW

EuroHPC

Tier-1Exascale

PilotContainer orchestration

(IP over low latency

network)

1ExaF~20MW

EuroHPCConverging architecture

(containerized + traditional

HPC schedulers)

28

PUE < 1.1ECMWF

Computer Rooms:

10 MW (2020) → 20 MW

(2023)

250-300 petaFLOPS

Estimated to end up in the

top 3 spots of Top500

E4 Computer Engineering

Since 2002, E4 Computer Engineering has been innovating and actively encouragingthe adoption of new computing and storage technologies. Because new ideas are soimportant, we invest heavily in research and hence in our future. Thanks to ourcomprehensive range of hardware, software and services, we are able to offer ourcustomers complete solutions for their most demanding workloads in: HPC, Big-Data,AI, Deep Learning, Data Analytics, Cognitive Computing and for any challengingStorage and Computing requirements.

29

Silver Levelhttps://openpowerfoundation.org/Cosimo Gianfreda

Member of the Steering Board http://www.etp4hpc.eu

Member of the Consortiumhttp://european-processor-initiative.com

Member of CERN openlabhttps://openlab.cern/

https://www.openfoam.com/

Member of HiPEAC

https://www.hipeac.net/

Member of the OEHI (Open Edge and HPC Initiative)http://www.open-edge-hpc-initiative.org/

Member of the MaXCenter of Excellencehttp://www.max-centre.eu/

E4 Computer Engineering

E4 Computer Engineering

2021 – H2

PCIe board with < RHEA β version

CONTRIBUTION TO EPI

• Technological leadership in a key sector

• Create a European ecosystem for microelectronics:

• Engineers, IP’s, foundries, technologies

• Create a European ecosystem for exascale-class applications

• Create an Italian ecosystem of expertise & knowledge

• We have to retain our talents

• Drive the completeness of the Italian and European industry

• Our industrial system faces a worldwide competition

The value of EPI for the industry

STMicroelectronics is a key player in the Server & Data Center Power Management arena and brings innovation by:

• Developing new ICs/IPs to support the advanced power management features of the newest CPU, DDR and ASIC chipset

ensuring best in class fast load transient response, high precision voltage positioning and accurate telemetry;

• Enabling new Architecture & Applications to achieve higher conversion efficiency and density required by the modern power

Server and Data Center services.

STMicroelectronics contribution to EPI

• ST activities focus on the development of a new generation of power conversion ICs dedicated to 48V power architecture

in order to significantly reduce the total cost of ownership in ultra-high-efficiency HPC based on EPI processor;

• ST enables also the development of the advanced power management for the EPI processor which is based on the adoption of

STMicroelectronics Power Management ICs.

ST CONTRIBUTION TO EPI

ST 48V SERVER & DATA CENTER

POWER MANAGEMENT

STC (unregulated)48V

MU

LTIP

HA

SE D

IGIT

AL

CO

NTR

OLL

ER

STBuck(regulated)

Isolated ResonantArchitecture

2° Stage (12V input)

Single Stage

SPS

SPS

SPS

SPS

SPS

SPS

SPS

SPSDu

al Sta

ge

Co

nv

ers

ion

Dire

ct

Co

nv

ers

ion

1° Stage (IBC*)*Intermediate Bus Conversion

SPS = Smart Power Stage

12V

CPU/DDR/ASIC

48V

Powering Server & Modern Data Center via the highest efficiency & density solutions

Complete solutions for Direct or Dual Stage CPU / DDR / ASIC power management

in 48V ecosystem

CPU/DDR/ASIC

Safety Critical

Industry 4.0

& Robotics

AeroSpace

Automotive

Servers

& Cloud

HPCCore

Drivers

sovereignty

AI

accelerators

AI accelerators (Posits)

DNN & ML and crypto benchmarking on ARM 64b

On-chip TRNG & CSPRNG

Crypto accelerators for hashing, symmetric key and public key crypto

Vertical chain for Secure OTA update of FW/SW

Safety & security of the MCU – HPC monitoring link

CONTRIBUTION TO EPI

1st EPI chip

Crypto Accelerators & on-chip TRNG/CSPRNG

TRNG (FiRo/GaRo oscillator based) & CSPRNG

Crypto accelerators, up to 300 Gbps real-time encryption/decryption

in 7 nm (needed to exploit HBM)

Configurable AES 126b/256b keys with 9 chipper modes

Configurable SHA2/SHA3 up to 512b hash functions

ECC-based public key crypto accelerators (ECDH, ECSIE,

ECDSA,..)

Open SSL Benchmarks on multi-core 64b ARM

X 3 order of magnitude gain thanks to crypto accelerators

Crypto accelerator ad-hoc policies integrated on-chip

Keys storage and management

Crypto configuration ad-hoc policy

Secure channels

V2X

Embedded

HPCV2X

V2X channel security & 5G on EPI

Over the Air SW/FW Update - Vertical chain

Post-quantum resistant

App SW (attributed based)

eLinux OS coexisting with RTOS

Hypervisor

EPI HW with crypto accelerators

5G resource control & adaptive allocation

spectrum, beam-forming/steering, channels,

power, goodput (modulation, coding,..)

Data Type (tot_bits, exp_bits) Accuracy on 10,000 images

Float32 98,88%

Posit16,2 98,88%

Posit14,2 98,85%

Posit12,2 98,66%

Posit10,0 98,69%

Posit8,0 97,24%

Posit Processing Unit

vs FPUMachine Learning test

(K-NN & A-NN classifiers)

Same or better accuracy with

halved bit-size

Posit Processing Unit vs FPUDNN tests

(MNIST, CIFAR, CoCo, Yolo, Alexnet,

Imagenet, GTRSB,…)

Posit has similar accuracy of Float with

complexity reduction x4

Float16

Posit8

(exp: 1bit)

Float32

Posit16

(exp: 3bit)

Posit Processing Unit available as

SW-library or IP macrocell

(HLS on FPGA or 7nm IC)

Float to Posit conversion

for data storage saving

Posit as compressed float

Accelerators for AI computing

OPEN DISCUSSION

Trend in Italy on EuroHPC & the European

Processor Initiative

Round Table:

Trend in Italy on EuroHPC & the European Processor Initiative

Federico Ficarelli, CINECA

Fabrizio Magugliani, E4

Alberto Rossi, STMicroelectronics

Andrea Bartolini, UniBologna

Sergio Saponara, UniPisa