74ahc74; 74ahct74 dual d-type flip-flop with set and … · 74ahc74; 74ahct74 dual d-type flip-flop...
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DATA SHEET
Product specificationSupersedes data of 1999 Sep 23
2004 Apr 29
INTEGRATED CIRCUITS
74AHC74; 74AHCT74Dual D-type flip-flop with set andreset; positive-edge trigger
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
FEATURES
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Balanced propagation delays
• Inputs accepts voltages higher than VCC
• For 74AHC74 only: operates with CMOS input levels
• For 74AHCT74 only: operates with TTL input levels
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOSdevice and is pin compatible with low power Schottky TTL(LSTTL). It is specified in compliance with JEDECstandard No. 7A.
The 74AHC74; 74AHCT74 is a dual positive-edgetriggered, D-type flip-flop with individual data (D) inputs,clock (CP) inputs, set (SD) and reset (RD) inputs; alsocomplementary Q and Q outputs.
The set and reset are asynchronous active LOW inputsand operate independently of the clock input. Informationon the data input is transferred to the Q output on theLOW-to-HIGH transition of the clock pulse. The D inputsmust be stable one set-up time prior to the LOW-to-HIGHclock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuithighly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC
2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
SYMBOL PARAMETER CONDITIONSTYPICAL
UNIT74AHC74 74AHCT74
tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V
nCP to nQ, nQ 3.7 3.3 ns
nSD, nRD to nQ, nQ 3.7 3.7 ns
fmax maximum clock pulse frequency 170 160 MHz
CI input capacitance VI = VCC or GND 4.0 4.0 pF
CPD power dissipation capacitance CL = 50 pF; f = 1 MHz;notes 1 and 2
12 16 pF
2004 Apr 29 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
FUNCTION TABLES
Table 1 See note 1
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH transition;
Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
ORDERING INFORMATION
PINNING
INPUT OUTPUT
nSD nRD nCP nD nQ n Q nQn+1 nQn+1
L H X X H L L H
H L X X L H H L
L L X X H H − −H H ↑ L − − L H
H H ↑ H − − H L
TYPE NUMBERPACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74AHC74D −40 °C to +125 °C 14 SO14 plastic SOT108-1
74AHCT74D −40 °C to +125 °C 14 SO14 plastic SOT108-1
74AHC74PW −40 °C to +125 °C 14 TSSOP14 plastic SOT402-1
74AHCT74PW −40 °C to +125 °C 14 TSSOP14 plastic SOT402-1
PIN SYMBOL DESCRIPTION
1 1RD asynchronous reset-direct input (active LOW)
2 1D data input
3 1CP clock input (LOW-to-HIGH, edge-triggered)
4 1SD asynchronous set-direct input (active LOW)
5 1Q true flip-flop output
6 1Q complement flip-flop output
7 GND ground (0 V)
6 2Q complement flip-flop output
9 2Q true flip-flop output
10 2SD asynchronous set-direct input (active LOW)
11 2CP clock input (LOW-to-HIGH, edge-triggered)
12 2D data input
13 2RD asynchronous reset-direct input (active LOW)
14 VCC supply voltage
2004 Apr 29 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Fig.1 Pin configuration.
handbook, halfpage
MNA417
74
1
2
3
4
5
6
7 8
14
13
12
11
10
9
1RD
1D
1CP
1SD
1Q
1Q
GND 2Q
2Q
2SD
2CP
2D
2RD
VCC
Fig.2 Logic diagram.
MNA418
handbook, halfpage
RD
FF
SD
4 10
Q1Q2Q
1Q
2Q
59
212
311
6
8Q
1SD
CP2CP1CP
2D1D
D
2SD
1 13
1RD 2RD
Fig.3 IEC logic symbol.
handbook, halfpage
MNA419
6
3
2C1
4S
1D1
R
5
8
11
12C1
10S
1D13
R
9
Fig.4 Functional diagram.
handbook, halfpage
RD
FF
SD
4
Q1Q
1Q
52
3
6Q
1SD
CP1CP
1DD
1 1RD
MNA420
RD
FF
SD
10
Q2Q
2Q
912
11
8Q
2SD
CP2CP
2DD
132RD
2004 Apr 29 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Fig.5 Logic diagram (one flip-flop).
handbook, full pagewidth
MNA421SD
CP
RD
D
C
C
Q
C
CC
C
C
C
Q
C
C
2004 Apr 29 5
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
SYMBOL PARAMETER CONDITIONS74AHC74 74AHCT74
UNITMIN. TYP. MAX. MIN. TYP. MAX.
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VI input voltage 0 − 5.5 0 − 5.5 V
VO output voltage 0 − VCC 0 − VCC V
Tamb operating ambient temperature −40 +25 +125 −40 +25 +125 °Ctr, tf input rise and fall times VCC = 3.3 V ± 0.3 V − − 100 − − − ns/V
VCC = 5 V ± 0.5 V − − 20 − − 20 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +7.0 V
VI input voltage −0.5 +7.0 V
IIK input diode current VI < −0.5 V; note 1 − −20 mA
IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA
IO output source or sink current VO = −0.5 V to VCC + 0.5 V − ±25 mA
ICC, IGND VCC or GND current − ±75 mA
Tstg storage temperature −65 +150 °CPtot power dissipation Tamb = −40 °C to +125 °C; note 2 − 500 mW
2004 Apr 29 6
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
DC CHARACTERISTICS
Type 74AHC74At recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITOTHER VCC (V)
Tamb = 25 °C
VIH HIGH-level input voltage 2.0 1.5 − − V
3.0 2.1 − − V
5.5 3.85 − − V
VIL LOW-level input voltage 2.0 − − 0.5 V
3.0 − − 0.9 V
5.5 − − 1.65 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −50 µA 2.0 1.9 2.0 − V
IO = −50 µA 3.0 2.9 3.0 − V
IO = −50 µA 4.5 4.4 4.5 − V
IO = −4.0 mA 3.0 2.58 − − V
IO = −8.0 mA 4.5 3.94 − − V
VOL LOW-level output voltage VI = VIH or VIL
IO = 50 µA 2.0 − 0 0.1 V
IO = 50 µA 3.0 − 0 0.1 V
IO = 50 µA 4.5 − 0 0.1 V
IO = 4 mA 3.0 − − 0.36 V
IO = 8 mA 4.5 − − 0.36 V
ILI input leakage current VI = VCC or GND 5.5 − − 0.1 µA
IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±0.25 µA
ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 2.0 µA
CI input capacitance − − 3 10 pF
2004 Apr 29 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage 2.0 1.5 − − V
3.0 2.1 − − V
5.5 3.85 − − V
VIL LOW-level input voltage 2.0 − − 0.5 V
3.0 − − 0.9 V
5.5 − − 1.65 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −50 µA 2.0 1.9 − − V
IO = −50 µA 3.0 2.9 − − V
IO = −50 µA 4.5 4.4 − − V
IO = −4.0 mA 3.0 2.48 − − V
IO = −8.0 mA 4.5 3.8 − − V
VOL LOW-level output voltage VI = VIH or VIL
IO = 50 µA 2.0 − − 0.1 V
IO = 50 µA 3.0 − − 0.1 V
IO = 50 µA 4.5 − − 0.1 V
IO = 4 mA 3.0 − − 0.44 V
IO = 8 mA 4.5 − − 0.44 V
ILI input leakage current VI = VCC or GND 5.5 − − 1.0 µA
IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±2.5 µA
ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 20 µA
CI input capacitance − − − 10 pF
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITOTHER VCC (V)
2004 Apr 29 8
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage 2.0 1.5 − − V
3.0 2.1 − − V
5.5 3.85 − − V
VIL LOW-level input voltage 2.0 − − 0.5 V
3.0 − − 0.9 V
5.5 − − 1.65 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −50 µA 2.0 1.9 − − V
IO = −50 µA 3.0 2.9 − − V
IO = −50 µA 4.5 4.4 − − V
IO = −4.0 mA 3.0 2.40 − − V
IO = −8.0 mA 4.5 3.70 − − V
VOL LOW-level output voltage VI = VIH or VIL
IO = 50 µA 2.0 − − 0.1 V
IO = 50 µA 3.0 − − 0.1 V
IO = 50 µA 4.5 − − 0.1 V
IO = 4 mA 3.0 − − 0.55 V
IO = 8 mA 4.5 − − 0.55 V
ILI input leakage current VI = VCC or GND 5.5 − − 2.0 µA
IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10.0 µA
ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 40 µA
CI input capacitance − − − 10 pF
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITOTHER VCC (V)
2004 Apr 29 9
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Type 74AHCT74At recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITOTHER VCC (V)
Tamb = 25 °CVIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V
VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −50 µA 4.5 4.4 4.5 − V
IO = −8.0 mA 4.5 3.94 − − V
VOL LOW-level output voltage VI = VIH or VIL
IO = 50 µA 4.5 − 0 0.1 V
IO = 8 mA 4.5 − − 0.36 V
ILI input leakage current VI = VIH or VIL 5.5 − − 0.1 µA
IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GNDper input pin; other inputs atVCC or GND; IO = 0 A
5.5 − − ±0.25 µA
ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 2.0 µA
∆ICC additional quiescent supplycurrent per input pin
VI = VCC − 2.1 V; other inputs atVCC or GND; IO = 0 A
4.5 to 5.5 − − 1.35 mA
CI input capacitance − − 3 10 pF
Tamb = −40 °C to +85 °CVIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V
VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −50 µA 4.5 4.4 − − V
IO = −8.0 mA 4.5 3.8 − − V
VOL LOW-level output voltage VI = VIH or VIL
IO = 50 µA 4.5 − − 0.1 V
IO = 8 mA 4.5 − − 0.44 V
ILI input leakage current VI = VIH or VIL 5.5 − − 1.0 µA
IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GNDper input pin; other inputs atVCC or GND; IO = 0 A
5.5 − − ±2.5 µA
ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 20 µA
∆ICC additional quiescent supplycurrent per input pin
VI = VCC − 2.1 V; other inputs atVCC or GND; IO = 0 A
4.5 to 5.5 − − 1.5 mA
CI input capacitance − − − 10 pF
2004 Apr 29 10
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Tamb = −40 °C to +125 °CVIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V
VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −50 µA 4.5 4.4 − − V
IO = −8.0 mA 4.5 3.70 − − V
VOL LOW-level output voltage VI = VIH or VIL
IO = 50 µA 4.5 − − 0.1 V
IO = 8 mA 4.5 − − 0.55 V
ILI input leakage current VI = VIH or VIL 5.5 − − 2.0 µA
IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GNDper input pin; other inputs atVCC or GND; IO = 0 A
5.5 − − ±10.0 µA
ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 40 µA
∆ICC additional quiescent supplycurrent per input pin
VI = VCC − 2.1 V; other inputs atVCC or GND; IO = 0 A
4.5 to 5.5 − − 1.5 mA
CI input capacitance − − − 10 pF
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITOTHER VCC (V)
2004 Apr 29 11
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
AC CHARACTERISTICS
Type 74AHC74GND = 0 V; tr = tf ≤ 3.0 ns; see Fig.8.
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITWAVEFORMS CL
Tamb = 25 °C
VCC = 3.0 V to 3.6 V; note 1
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF − 5.2 11.9 ns
50 pF − 7.4 15.4 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF − 5.4 12.3 ns
50 pF − 7.7 15.8 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 80 125 − MHz
50 pF 50 75 − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 6.0 − − ns
set or reset pulse width LOW see Fig.7 50 pF 6.0 − − ns
trem removal time set or reset see Fig.7 50 pF 5.0 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 6.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0.5 − − ns
VCC = 4.5 V to 5.5 V; note 2
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF − 3.7 7.3 ns
50 pF − 5.2 9.3 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF − 3.7 7.7 ns
50 pF − 5.3 9.7 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 130 170 − MHz
50 pF 90 115 − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 5.0 − − ns
set or reset pulse width LOW see Fig.7 50 pF 5.0 − − ns
trem removal time set or reset see Fig.7 50 pF 3.0 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 5.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0.5 − − ns
2004 Apr 29 12
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Tamb = −40 °C to +85 °C
VCC = 3.0 V to 3.6 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF 1.0 − 14.0 ns
50 pF 1.0 − 17.5 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF 1.0 − 14.5 ns
50 pF 1.0 − 18.0 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 45 − − MHz
50 pF 70 − − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 7.0 − − ns
set or reset pulse width LOW see Fig.7 50 pF 7.0 − − ns
trem removal time set or reset see Fig.7 50 pF 5.0 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 7.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0.5 − − ns
VCC = 4.5 V to 5.5 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF 1.0 − 8.5 ns
50 pF 1.0 − 10.5 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF 1.0 − 9.0 ns
50 pF 1.0 − 11.0 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 110 − − MHz
50 pF 75 − − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 5.0 − − ns
set or reset pulse width LOW see Fig.7 50 pF 5.0 − − ns
trem removal time set or reset see Fig.7 50 pF 3.0 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 5.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0.5 − − ns
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITWAVEFORMS CL
2004 Apr 29 13
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Notes
1. Typical values are measured at VCC = 3.3 V.
2. Typical values are measured at VCC = 5.0 V.
Tamb = −40 °C to +125 °C
VCC = 3.0 V TO 3.6 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF 1.0 − 15.0 ns
50 pF 1.0 − 19.5 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF 1.0 − 15.5 ns
50 pF 1.0 − 20.0 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 45 − − MHz
50 pF 70 − − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 7.0 − − ns
set or reset pulse width LOW see Fig.7 50 pF 7.0 − − ns
trem removal time set or reset see Fig.7 50 pF 5.0 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 7.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0.5 − − ns
VCC = 4.5 V to 5.5 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF 1.0 − 9.5 ns
50 pF 1.0 − 12.0 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF 1.0 − 10.0 ns
50 pF 1.0 − 12.5 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 110 − − MHz
50 pF 75 − − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 5.0 − − ns
set or reset pulse width LOW see Fig.7 50 pF 5.0 − − ns
trem removal time set or reset see Fig.7 50 pF 3.0 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 5.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0.5 − − ns
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITWAVEFORMS CL
2004 Apr 29 14
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Type 74AHCT74GND = 0 V; tr = tf ≤ 3.0 ns; see Fig.8.
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITWAVEFORMS CL
Tamb = 25 °C; note 1
VCC = 4.5 V to 5.5 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF − 3.3 7.8 ns
50 pF − 4.8 8.8 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF − 3.7 10.4 ns
50 pF − 5.3 11.4 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 100 160 − MHz
50 pF 80 140 − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 5.0 − − ns
tW(st)(rst) set or reset pulse width LOW see Fig.7 50 pF 5.0 − − ns
trem removal time set or reset see Fig.7 50 pF 3.5 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 5.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0 − − ns
Tamb = −40 °C to +85 °C
VCC = 4.5 V to 5.5 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF 1.0 − 9.0 ns
50 pF 1.0 − 10.0 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF 1.0 − 12.0 ns
50 pF 1.0 − 13.0 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 80 − − MHz
50 pF 65 − − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 5.0 − − ns
tW(st)(rst) set or reset pulse width LOW see Fig.7 50 pF 5.0 − − ns
trem removal time set or reset see Fig.7 50 pF 3.5 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 5.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0 − − ns
2004 Apr 29 15
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Note
1. Typical values are measured at VCC = 5.0 V.
Tamb = −40 °C to +125 °C
VCC = 4.5 V to 5.5 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.6 15 pF 1.0 − 10.0 ns
50 pF 1.0 − 11.0 ns
propagation delay nSD, nRD to nQ, nQ see Fig.7 15 pF 1.0 − 13.0 ns
50 pF 1.0 − 14.5 ns
fmax maximum clock pulse frequency see Fig.6 15 pF 80 − − MHz
50 pF 65 − − MHz
tW clock pulse width HIGH or LOW see Fig.6 50 pF 5.0 − − ns
tW(st)(rst) set or reset pulse width LOW see Fig.7 50 pF 5.0 − − ns
trem removal time set or reset see Fig.7 50 pF 3.5 − − ns
tsu set-up time nD to nCP see Fig.6 50 pF 5.0 − − ns
th hold time nD to nCP see Fig.6 50 pF 0 − − ns
SYMBOL PARAMETERTEST CONDITIONS
MIN. TYP. MAX. UNITWAVEFORMS CL
2004 Apr 29 16
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
AC WAVEFORMS
Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, thenCP to nD hold times, the output transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to change for predictable output performance.
handbook, full pagewidth
MNA422
thtsu
th
tPHL
tPHL
tW
tPLH
tPLH
tsu1/fmax
VM
VM
VM
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output
TYPEVI INPUT
REQUIREMENTSVM INPUT VM OUTPUT
74AHC74 GND to VCC 50 % VCC 50 % VCC
74AHCT74 GND to 3.0 V 1.5 V 50 % VCC
2004 Apr 29 17
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Fig.7 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widthsand the nRD to nCP removal time.
handbook, full pagewidth
MNA423
trem
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
TYPEINPUT OUTPUT
VI VM VM
74AHC74 GND to VCC 50 % VCC 50 % VCC
74AHCT74 GND to 3.0 V 1.5 V 50 % VCC
2004 Apr 29 18
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
Fig.8 Load circuitry for switching times.
TEST S1
tPLH/tPHL open
tPLZ/tPZL VCC
tPHZ/tPZH GND
handbook, full pagewidth
openGND
VCC
VCC
VI VO
MNA183
D.U.T.
CLRT
RL =
1 kΩPULSE
GENERATOR
S1
Definitions for test circuit:
RL = load resistance.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
2004 Apr 29 19
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
PACKAGE OUTLINES
UNITA
max. A1 A2 A3 bp c D(1) E(1) (1)e HE L L p Q Zywv θ
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.750.250.10
1.451.25
0.250.490.36
0.250.19
8.758.55
4.03.8
1.276.25.8
0.70.6
0.70.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.00.4
SOT108-1
X
w M
θ
AA1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
v M A
(A )3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.0690.0100.004
0.0570.049
0.010.0190.014
0.01000.0075
0.350.34
0.160.15
0.05
1.05
0.0410.2440.228
0.0280.024
0.0280.012
0.01
0.25
0.01 0.0040.0390.016
99-12-2703-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2004 Apr 29 20
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
UNIT A1 A2 A3 bp c D (1) E (2) (1)e HE L L p Q Zywv θ
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.150.05
0.950.80
0.300.19
0.20.1
5.14.9
4.54.3
0.656.66.2
0.40.3
0.720.38
80
o
o0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.750.50
SOT402-1 MO-15399-12-2703-02-18
w Mbp
D
Z
e
0.25
1 7
14 8
θ
AA1
A2
Lp
Q
detail X
L
(A )3
HE
E
c
v M A
XA
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
Amax.
1.1
pin 1 index
2004 Apr 29 21
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;positive-edge trigger
74AHC74; 74AHCT74
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet waspublished. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVELDATA SHEET
STATUS(1)PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for productdevelopment. Philips Semiconductors reserves the right to change thespecification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.Supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to change the specification withoutnotice, in order to improve the design and supply the best possibleproduct.
III Product data Production This data sheet contains data from the product specification. PhilipsSemiconductors reserves the right to make changes at any time in orderto improve the design, manufacturing and supply. Relevant changes willbe communicated via a Customer Product/Process Change Notification(CPCN).
DEFINITIONS
Short-form specification The data in a short-formspecification is extracted from a full data sheet with thesame type number and title. For detailed information seethe relevant data sheet or data handbook.
Limiting values definition Limiting values given are inaccordance with the Absolute Maximum Rating System(IEC 60134). Stress above one or more of the limitingvalues may cause permanent damage to the device.These are stress ratings only and operation of the deviceat these or at any other conditions above those given in theCharacteristics sections of the specification is not implied.Exposure to limiting values for extended periods mayaffect device reliability.
Application information Applications that aredescribed herein for any of these products are forillustrative purposes only. Philips Semiconductors makeno representation or warranty that such applications will besuitable for the specified use without further testing ormodification.
DISCLAIMERS
Life support applications These products are notdesigned for use in life support appliances, devices, orsystems where malfunction of these products canreasonably be expected to result in personal injury. PhilipsSemiconductors customers using or selling these productsfor use in such applications do so at their own risk andagree to fully indemnify Philips Semiconductors for anydamages resulting from such application.
Right to make changes Philips Semiconductorsreserves the right to make changes in the products -including circuits, standard cells, and/or software -described or contained herein in order to improve designand/or performance. When the product is in full production(status ‘Production’), relevant changes will becommunicated via a Customer Product/Process ChangeNotification (CPCN). Philips Semiconductors assumes noresponsibility or liability for the use of any of theseproducts, conveys no licence or title under any patent,copyright, or mask work right to these products, andmakes no representations or warranties that theseproducts are free from patent, copyright, or mask workright infringement, unless otherwise specified.
2004 Apr 29 22
© Koninklijke Philips Electronics N.V. 2004 SCA76All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com . Fax: +31 40 27 24825For sales offices addresses send e-mail to: [email protected] .
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands R44/03/pp23 Date of release: 2004 Apr 29 Document order number: 9397 750 13118