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Single/Dual/Quad 18MHz,Low Noise, Rail-to-Rail Output,

CMOS Op Amps

The LTC6240/6241/LTC6242 are single, dual and quadlow noise, low offset, rail-to-rail output, unity gain stableCMOS op amps that feature 1pA of input bias current. Inputbias current is guaranteed to be 1pA max on the singleLTC6240. The 0.1Hz to 10Hz noise of only 550nVP-P, alongwith an offset of just 125V are significant improvementsover traditional CMOS op amps. Additionally, noise isguaranteed to be less than 10nV/Hz at 1kHz. An 18MHzgain bandwidth, and 10V/s slew rate, along with the widesupply range and low input capacitance, make them perfect

for use as fast signal processing amplifiers.These op amps have an output stage that swings within30mV of either supply rail to maximize the signal dynamicrange in low supply applications. The input common moderange extends to the negative supply. They are fully speci-fied on 3V and 5V, and an HV version guarantees operationon supplies up to 5V.

The LTC6240 is available in the 8-pin SO and the 5-pin SOT-23 packages. The LTC6241 is available in the 8-pin SO, andfor compact designs it is packaged in a tiny dual fine pitch

leadless (DFN) package. The LTC6242 is available in the16-pin SSOP as well as the 5mm 3mm DFN package.

n Photo Diode Amplifiersn Charge Coupled Amplifiersn Low Noise Signal Processingn Medical Instrumentationn High Impedance Transducer Amplifier

n 0.1Hz to 10Hz Noise: 550nVP-Pn Input Bias Current:

0.2pA (Typ at 25C)1pA Max (LTC6240)

n Low Offset Voltage: 125V Maxn Low Offset Drift: 2.5V/C Maxn Gain Bandwidth Product: 18MHzn Output Swings Rail-to-Railn Supply Operation:

2.8V to 6V LTC6240/LTC6241/LTC6242

2.8V to 5.5V LTC6240HV/LTC6241HV/LTC6242HVn Low Input Capacitancen H-Grade Temperature Range: 40C to 125Cn Single LTC6240 in 5-Pin Low Profile (1mm)

ThinSOT Package and 8-Pin SO for PCB Guard Ringn Dual LTC6241 in 8-Pin SO and Tiny DFN Packagesn Quad LTC6242 in 16-Pin SSOP and 5mm 3mm

DFN Packages

Low Noise Single-Ended Input to Differential Output Amplifier Noise Voltage vs Frequency

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of LinearTechnology Corporation. ThinSOT is a trademark of Linear Technology Corporation.All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

DESCRIPTIONFEATURES

APPLICATIONS

+

R2200k

C110pF

C210pF

+2.5V

2.5V

6241 TA01a

R44.99k

R1200k

VIN

VOUT+

VOUT1/2

LTC6241

+

1/2

LTC6241

C310pF

R34.99k

C4

10pF

FREQUENCY (Hz)

20

10

NOISEVOLTAGE(nV/Hz)

30

40

50

60

1 100 1k 100k

6241 TA01b

010 10k

TA = 25CVS = 2.5VVCM = 0V

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Total Supply Voltage (V+ to V)LTC6240/LTC6241/LTC6242 ...................................7VLTC6240HV/LTC6241HV/LTC6242HV ....................12V

Input Voltage .......................... (V+ + 0.3V) to (V 0.3V)Input Current ........................................................ 10mAOutput Short-Circuit Duration (Note 2) ............ IndefiniteOperating Temperature Range

LTC6240C/LTC6241C/LTC6242C ..........40C to 85CLTC6240I/LTC6241I/LTC6242I .............40C to 85CLTC6240H/LTC6241H/LTC6242H ....... 40C to 125C

(Note 1)

Specified Temperature Range (Note 3)LTC6240C/LTC6241C/LTC6242C .............. 0C to 70CLTC6240I/LTC6241I/LTC6242I .............40C to 85C

LTC6240H/LTC6241H/LTC6242H ....... 40C to 125CJunction Temperature ........................................... 150C

DHC, DD Package ............................................. 125CStorage Temperature Range ..................65C to 150C

DHC, DD Package .............................. 65C to 125CLead Temperature (Soldering, 10 sec)...................300C

ABSOLUTE MAXIMUM RATINGS

LTC6240 LTC6240

OUT 1

V 2

TOP VIEW

S5 PACKAGE5-LEAD PLASTIC TSOT-23

+IN 3

5 V+

4 IN+

TJMAX = 150C, JA = 250C/W

1

2

3

4

8

7

6

5

TOP VIEW

NC

V+

OUT

NC

NC

IN

+IN

V

S8 PACKAGE8-LEAD PLASTIC SO

+


LTC6241 LTC6241

TOP VIEW

DD PACKAGE8-LEAD (3mm s 3mm) PLASTIC DFN

5

6

78

4

3

21OUT A

IN A

+IN A

V

V+

OUT B

IN B

+IN BB

A

TJMAX = 125C, JA = 43C/WUNDERSIDE METAL CONNECTED TO V

(PCB CONNECTION OPTIONAL)

1

2

3

4

8

7

6

5

TOP VIEW

V+

OUT B

IN B

+IN B

OUT A

IN A

+IN A

V

S8 PACKAGE8-LEAD PLASTIC SO

B

A


LTC6242 LTC6242

16

15

14

13

12

11

10

9

17

1

2

3

4

5

6

7

8

OUT D

IN D

+IN D

V

+IN C

IN C

OUT C

NC

OUT A

IN A

+IN A

V+

+IN B

IN B

OUT B

NC

TOP VIEW

DHC PACKAGE16-LEAD (5mm s 3mm) PLASTIC DFN

B

A

C

D

TJMAX = 125C, JA = 43C/WUNDERSIDE METAL CONNECTED TO V (PCB CONNECTION OPTIONAL)

GN PACKAGE16-LEAD PLASTIC SSOP

1

2

3

4

5

6

7

8

TOP VIEW

16

15

14

13

12

11

10

9

OUT A

IN A

+IN A

V+

+IN B

IN B

OUT B

NC

OUT D

IN D

+IN D

V

+IN C

IN C

OUT C

NC

B

A

C

D


PIN CONFIGURATION

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LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6240CS5#PBF LTC6240CS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 0C to 70C

LTC6240HVCS5#PBF LTC6240HVCS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 0C to 70C

LTC6240IS5#PBF LTC6240IS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 40C to 85C

LTC6240HVIS5#PBF LTC6240HVIS5 #TRPBF LTCRS 5-Lead Plastic TSOT-23 40C to 85C

LTC6240HS5#PBF LTC6240HS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 40C to 125C

LTC6240HVHS5#PBF LTC6240HVHS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 40C to 125C

LTC6240CS8#PBF LTC6240CS8#TRPBF 6240 8-Lead Plastic SO 0C to 70C

LTC6240HVCS8#PBF LTC6240HVCS8#TRPBF 6240HV 8-Lead Plastic SO 0C to 70C

LTC6240IS8#PBF LTC6240IS8#TRPBF 6240I 8-Lead Plastic SO 40C to 85C

LTC6240HVIS8#PBF LTC6240HVIS8#TRPBF 240HVI 8-Lead Plastic SO 40C to 85C

LTC6240HS8#PBF LTC6240HS8#TRPBF 6240H 8-Lead Plastic SO 40C to 125C

LTC6240HVHS8#PBF LTC6240HVHS8#TRPBF 240HVH 8-Lead Plastic SO 40C to 125C

LTC6241CDD#PBF LTC6241CDD#TRPBF LBPD 8-Lead (3mm 3mm) Plastic DFN 0C to 70C

LTC6241HVCDD#PBF LTC6241HVCDD#TRPBF LBRR 8-Lead (3mm 3mm) Plastic DFN 0C to 70C

LTC6241IDD#PBF LTC6241IDD#TRPBF LBPD 8-Lead (3mm 3mm) Plastic DFN 40C to 85C

LTC6241HVIDD#PBF LTC6241HVIDD#TRPBF LBRR 8-Lead (3mm 3mm) Plastic DFN 40C to 85C

LTC6241CS8#PBF LTC6241CS8#TRPBF 6241 8-Lead Plastic SO 0C to 70C

LTC6241HVCS8#PBF LTC6241HVCS8#TRPBF 6241HV 8-Lead Plastic SO 0C to 70C

LTC6241IS8#PBF LTC6241IS8#TRPBF 6241I 8-Lead Plastic SO 40C to 85C

LTC6241HVIS8#PBF LTC6241HVIS8#TRPBF 241HVI 8-Lead Plastic SO 40C to 85C

LTC6241HS8#PBF LTC6241HS8#TRPBF 6241H 8-Lead Plastic SO 40C to 125C

LTC6241HVHS8#PBF LTC6241HVHS8#TRPBF 241HVH 8-Lead Plastic SO 40C to 125C

LTC6242CDHC#PBF LTC6242CDHC#TRPBF 6242 16-Lead (5mm 3mm) Plastic DFN 0C to 70C

LTC6242HVCDHC#PBF LTC6242HVCDHC#TRPBF 6242HV 16-Lead (5mm 3mm) Plastic DFN 0C to 70C

LTC6242IDHC#PBF LTC6242IDHC#TRPBF 6242 16-Lead (5mm 3mm) Plastic DFN 40C to 85C

LTC6242HVIDHC#PBF LTC6242HVIDHC#TRPBF 6242HV 16-Lead (5mm 3mm) Plastic DFN 40C to 85C

LTC6242CGN#PBF LTC6242CGN#TRPBF 6242 16-Lead Plastic SSOP 0C to 70C

LTC6242HVCGN#PBF LTC6242HVCGN#TRPBF 6242HV 16-Lead Plastic SSOP 0C to 70C

LTC6242IGN#PBF LTC6242IGN#TRPBF 6242I 16-Lead Plastic SSOP 40C to 85C

LTC6242HVIGN#PBF LTC6242HVIGN#TRPBF 242HVI 16-Lead Plastic SSOP 40C to 85C

LTC6242HGN#PBF LTC6242HGN#TRPBF 6242H 16-Lead Plastic SSOP 40C to 125C

LTC6242HVHGN#PBF LTC6242HVHGN#TRPBF 242HVH 16-Lead Plastic SSOP 40C to 125C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to:http://www.linear.com/leadfree/For more information on tape and reel specifications, go to:http://www.linear.com/tapeandreel/

ORDER INFORMATION

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AVAILABLE OPTIONS

PART NUMBER AMPS/PACKAGE SPECIFIED TEMP RANGE SPECIFIED SUPPLY VOLTAGE PACKAGE PART MARKING

LTC6240CS5 1 0C to 70C 3V, 5V SOT-23 LTCRR

LTC6240CS8 1 0C to 70C 3V, 5V SO-8 6240

LTC6240HVCS5 1 0C to 70C 3V, 5V, 5V SOT-23 LTCRS

LTC6240HVCS8 1 0C to 70C 3V, 5V, 5V SO-8 6240HV

LTC6240IS5 1 40C to 85C 3V, 5V SOT-23 LTCRR

LTC6240IS8 1 40C to 85C 3V, 5V SO-8 6240I

LTC6240HVIS5 1 40C to 85C 3V, 5V, 5V SOT-23 LTCRS

LTC6240HVIS8 1 40C to 85C 3V, 5V, 5V SO-8 240HVI

LTC6240HS5 1 40C to 125C 3V, 5V SOT-23 LTCRR

LTC6240HS8 1 40C to 125C 3V, 5V SO-8 6240H

LTC6240HVHS5 1 40C to 125C 3V, 5V, 5V SOT-23 LTCRS

LTC6240HVHS8 1 40C to 125C 3V, 5V, 5V SO-8 240HVH

LTC6241CS8 2 0C to 70C 3V, 5V SO-8 6241

LTC6241CDD 2 0C to 70C 3V, 5V DD LBPDLTC6241HVCS8 2 0C to 70C 3V, 5V, 5V SO-8 6241HV

LTC6241HVCDD 2 0C to 70C 3V, 5V, 5V DD LBRR

LTC6241IS8 2 40C to 85C 3V, 5V SO-8 6241I

LTC6241IDD 2 40C to 85C 3V, 5V DD LBPD

LTC6241HVIS8 2 40C to 85C 3V, 5V, 5V SO-8 241HVI

LTC6241HVIDD 2 40C to 85C 3V, 5V, 5V DD LBRR

LTC6241HS8 2 40C to 125C 3V, 5V SO-8 6241H

LTC6241HVHS8 2 40C to 125C 3V, 5V, 5V SO-8 241HVH

LTC6242CGN 4 0C to 70C 3V, 5V GN 6242

LTC6242CDHC 4 0C to 70C 3V, 5V DHC 6242

LTC6242HVCGN 4 0C to 70C 3V, 5V, 5V GN 6242HVLTC6242HVCDHC 4 0C to 70C 3V, 5V, 5V DHC 6242HV

LTC6242IGN 4 40C to 85C 3V, 5V GN 6242I

LTC6242IDHC 4 40C to 85C 3V, 5V DHC 6242

LTC6242HVIGN 4 40C to 85C 3V, 5V, 5V GN 242HVI

LTC6242HVIDHC 4 40C to 85C 3V, 5V, 5V DHC 6242HV

LTC6242HGN 4 40C to 125C 3V, 5V GN 6242H

LTC6242HVHGN 4 40C to 125C 3V, 5V, 5V GN 242HVH

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ELECTRICAL CHARACTERISTICS (LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are atTA = 25C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S80C to 70C40C to 85C

l

l

40 125250300

VVV

LTC6242 GN0C to 70C40C to 85C

l

l

50 150275300

VVV

LTC62400C to 70C40C to 85C

l

l

50 175300350

VVV

LTC6241 DD, LTC6242 DHC0C to 70C40C to 85C

l

l

100 550650725

VVV

VOS Match Channel-to-Channel (Note 5) LTC6241 S80C to 70C

40C to 85C

l

l

40 160300

375

VV

VLTC6242 GN0C to 70C40C to 85C

l

l

50 185325400

VVV


l

l

150 650700750

VVV

TC VOS Input Offset Voltage Drift (Note 6) l 0.7 2.5 V/C

IB Input Bias Current (Notes 4, 7) LTC6241, LTC6242l

0.275

pApA

LTC6240l

0.2 175

pApA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242 l 0.2 75 pApA

LTC6240l

0.2 175

pApA

Input Noise Voltage 0.1Hz to 10Hz 550 nVP-P

en Input Noise Voltage Density f = 1kHz 7 10 nV/Hz

in Input Noise Current Density (Note 8) 0.56 fA/Hz

RIN Input Resistance Common Mode 1012

CIN Input CapacitanceDifferential ModeCommon Mode

f = 100kHz3.53

pFpF

VCM Input Voltage Range Guaranteed by CMRR l 0 3.5 V

CMRR Common Mode Rejection 0V VCM 3.5V l 80 105 dBCMRR MatchChannel-to-Channel (Note 5) l 76 95 dB

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AVOL Large Signal Voltage Gain VO = 1V to 4VRL = 10k to VS/20C to 70C40C to 85C

l

l

425300200

1600 V/mVV/mVV/mV

VO = 1.5V to 3.5VRL = 1k to VS/20C to 70C40C to 85C

l

l

906050

215 V/mVV/mVV/mV

VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mAISINK = 5mA

l

l

l

740

190

3075325

mVmVmV

VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mAISOURCE = 5mA

l

l

l

1145

190

3075325

mVmVmV

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 80 104 dBPSRR MatchChannel-to-Channel (Note 5) l 74 100 dB

Minimum Supply Voltage (Note 10) l 2.8 V

ISC Short-Circuit Current l 15 30 mA

IS Supply Current per Amplifier LTC6241, LTC62420C to 70C40C to 85C

l

l

1.8 2.22.32.4

mAmAmA


l

l

2 2.42.52.6

mAmAmA

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l 13 18 MHz

SR Slew Rate (Note 11) AV = 2, RL = 1k l 5 10 V/sFPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l 0.53 1.06 MHz

ts Settling Time VSTEP = 2V, AV = 1, RL = 1k, 0.1% 1100 ns


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VOS

Input Offset Voltage (Note 4) LTC6241 S80C to 70C40C to 85C

l

l

40 175275325

VVV


l

l

60 200275325

VVV


l

l

50 200325375

VVV


l

l

100 550650725

VVV

VOS Match Channel-to-Channel (Note 5) LTC6241 S80C to 70C40C to 85C

l

l

40 200325400

VVV


l

l

60 225325400

VVV


l

l

150 650700750

VVV



0.275

pApA

LTC6240l

0.2 175

pApA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242l

0.275

pApA

LTC6240l

0.2 175

pApA


CMRR Common Mode Rejection 0V VCM 1.5V l 78 100 dB

CMRR MatchChannel-to-Channel (Note 5) l 76 95 dB

AVOL Large Signal Voltage Gain VO = 1V to 2VRL = 10k to VS/20C to 70C40C to 85C

l

l

14010075

600 V/mVV/mVV/mV

VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mA

l

l

365

30110

mVmV

VOH

Output Voltage Swing High (Note 9) No LoadISOURCE = 1mA

l

l

470

30120

mVmV

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 80 104 dB

PSRR MatchChannel-to-Channel (Note 5) l 74 100 dB


ISC Short-Circuit Current l 3 6 mA

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VOS Input Offset Voltage (Note 4) LTC6241 S8

0C to 70C40C to 85Cl

l

50 175

275325

V

VV


l

l

60 200275325

VVV


l

l

60 250350400

VVV


l

l

100 550650725

VVV

VOS Match Channel-to-Channel (Note 5) LTC6241 S80C to 70C40C to 85C

l

l

50 200325400

VVV


l

l

60 225325400

VVV


l

l

150 650700750

VVV



0.575

pApA

LTC6240l

0.5 175

pApA


0.275

pApA

LTC6240l

0.2 175

pApA

Input Noise Voltage 0.1Hz to 10Hz 550 nVP-P

(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 0V unless otherwise noted.



IS

Supply Current per Amplifier LTC6241, LTC62420C to 70C40C to 85C

l

l

1.4 1.71.81.9

mAmAmA


l

l

1.5 1.92

2.1

mAmAmA


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ELECTRICAL CHARACTERISTICS (LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes thespecifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 0Vunless otherwise noted.


en Input Noise Voltage Density f = 1kHz 7 10 nV/Hz

in Input Noise Current Density (Note 8) 0.56 fA/Hz

RIN Input Resistance Common Mode 1012

CIN Input CapacitanceDifferential ModeCommon Mode

f = 100kHz3.53

pFpF


CMRR Common Mode Rejection 5V VCM 3.5V l 83 105 dB

CMRR MatchChannel-to-Channel (Note 5) l 76 95 dB

AVOL Large Signal Voltage Gain VO = 3.5V to 3.5VRL = 10k0C to 70C

40C to 85C

l

l

775600

500

2700 V/mVV/mV

V/mVRL = 1k0C to 70C40C to 85C

l

l

1509075

360 V/mVV/mVV/mV


l

l

l

1545

360

3075

550

mVmVmV


l

l

l

1545

360

3075

550

mVmVmV

PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V l 85 110 dB

PSRR MatchChannel-to-Channel (Note 5) l 82 106 dB

Minimum Supply Voltage (Note 10) l 2.8 VISC Short-Circuit Current l 15 35 mA

IS Supply Current per Amplifier LTC6241, LTC62420C to 70C40C to 85C

l

l

2.5 3.23.33.7

mAmAmA


l

l

2.7 3.33.43.8

mAmAmA


SR Slew Rate (Note 11) AV = 2, RL = 1k l 5.5 10 V/s

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l 0.58 1.06 MHz

ts Settling Time VSTEP = 2V, AV = 1, RL = 1k, 0.1% 900 ns

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(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)The l denotes the specifications which apply from 40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, 0V, VCM = 2.5Vunless otherwise noted.

ELECTRICAL CHARACTERISTICS


VOS

Input Offset Voltage (Note 4) LTC6241 S8l

40 125400

VV

LTC6242 GNl

50 150400

VV

LTC6240l

50 175450

VV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8l

40 160400

VV

LTC6242 GNl

50 185400

VV



0.21.5

pAnA

LTC6240l

0.2 12.5 pAnA


0.2150

pApA

LTC6240l

0.2 1750

pApA


CMRR Common Mode Rejection 0V VCM 3.5V l 78 dB

CMRR MatchChannel-to-Channel (Note 5) l 74 dB

AVOL Large Signal Voltage Gain VO = 1V to 4VRL = 10k to VS/2

l

425200

1600 V/mVV/mV

VO = 1.5V to 3.5VRL = 1k to VS/2

l

9040

215 V/mVV/mV


l

l

l

3085325

mVmVmV


l

l

l

3085

325

mVmVmV

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 78 dB

PSRR MatchChannel-to-Channel (Note 5) l 74 dB


ISC Short-Circuit Current l 15 mA

IS Supply Current per Amplifier LTC6241, LTC6242l

1.8 2.22.4

mAmA

LTC6240l

2 2.42.8

mAmA

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l 12 MHz

SR Slew Rate (Note 11) AV = 2, RL = 1k l 4.5 V/s

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l 0.48 MHz

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ELECTRICAL CHARACTERISTICS (LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)The l denotes the specifications which apply from 40C to 125C, otherwise specifications are at TA = 25C. VS = 3V, 0V, VCM = 1.5Vunless otherwise noted.


VOS Input Offset Voltage (Note 4) LTC6241 S8 l 40 175400 VV

LTC6242 GNl

60 200400

VV

LTC6240l

50 200450

VV


40 200400

VV

LTC6242 GNl

60 225400

VV



0.21.5

pAnA

LTC6240l

0.2 12.5

pAnA


0.2150

pApA

LTC6240l

0.2 1750

pApA




AVOL Large Signal Voltage Gain VO = 1V to 2VRL = 10k to VS/2

l

140

65

600 V/mV

V/mVVOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mAl

l

30130

mVmV

VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mA

l

l

30130

mVmV


PSRR Match Channel-to-Channel(Note 5) l 74 dB


ISC Short-Circuit Current l 2.5 mA

IS Supply Current per Amplifier LTC6241, LTC6242l

1.4 1.71.9

mAmA

LTC6240l

1.5 1.92.1

mAmA


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(LTC6240HVH/LTC6241HVH/LTC6242HVH) The l denotes the specificationswhich apply from 40C to 125C, otherwise specifications are at TA = 25C. VS = 5V, VCM = 0V unless otherwise noted.ELECTRICAL CHARACTERISTICS


VOS Input Offset Voltage (Note 4) LTC6241 S8l

50 175

400

V

VLTC6242 GNl

60 200400

VV

LTC6240l

60 250450

VV


50 200400

VV

LTC6242 GNl

60 225400

VV



0.51.5

pAnA

LTC6240l

0.5 12.5

pAnA


0.2150

pApA

LTC6240l

0.2 1750

pApA




AVOL Large Signal Voltage Gain VO = 3.5V to 3.5VRL = 10k

l

775350

2700 V/mVV/mV

RL = 1kl

15060

360 V/mVV/mV


l

l

l

3085600

mVmVmV


l

l

l

3085600

mVmVmV


PSRR MatchChannel-to-Channel (Note 5) l 82 dB


ISC Short-Circuit Current l 15 mAIS Supply Current per Amplifier LTC6241, LTC6242

l

2.5 3.23.7

mAmA

LTC6240l

2.7 3.33.8

mAmA


SR Slew Rate (Note 11) AV = 2, RL = 1k l 5 V/s

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l 0.53 MHz

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Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.

Note 2: A heat sink may be required to keep the junction temperaturebelow the absolute maximum rating when the output is shortedindefinitely.

Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/LTC6242HVC are guaranteed to meet specified performance from 0C to70C. They are designed, characterized and expected to meet specifiedperformance from 40C to 85C, but are not tested or QA sampled atthese temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI,LTC6242I/LTC6242HVI are guaranteed to meet specified performancefrom 40C to 85C. All versions of the LTC6240H/LTC6241H/LTC6242Hare guaranteed to meet specified performance from 40C to 125C.

Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protectiondevices are used extensively internal to the LTC6240/LTC6241/LTC6242;

however, high electrostatic discharge can damage or degrade the device.Use proper ESD handling precautions.

Note 5: Matching parameters are the difference between the two amplifiersA and D and between B and C of the LTC6242; between the two amplifiersof the LTC6241. CMRR and PSRR match are defined as follows: CMRRand PSRR are measured in V/V on the matched amplifiers. The differenceis calculated between the matching sides in V/V. The result is convertedto dB.

Note 6: This parameter is not 100% tested.

Note 7: Bias current at TA = 25C is 100% tested and guaranteed for theLTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are

expected to achieve the same performance as the LTC6240S8. All parts areguaranteed to meet specifications over temperature.

Note 8: Current noise is calculated from the formula: in = (2qIB)1/2 whereq = 1.6 1019 coulomb. The noise of source resistors up to 50Gdominates the contribution of current noise. See also Typical PerformanceCharacteristics curve Noise Current vs Frequency.

Note 9: Output voltage swings are measured between the output andpower supply rails.

Note 10: Minimum supply voltage is guaranteed by the power supplyrejection ratio test.

Note 11: Slew rate is measured in a gain of 2 with RF = 1k and RG =500. On the LTC6240/LTC6241/LTC6242, VS = 2.5V, VIN is 1V andVOUT slew rate is measured between 1V and +1V. On the LTC6240HV/LTC6241HV/LTC6242HV, VIN is 2V and VOUT slew rate is measuredbetween 2V and +2V.Note 12: Full-power bandwidth is calculated from the slew rate:

FPBW = SR/VP-P.

ELECTRICAL CHARACTERISTICS

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Input Bias Currentvs Common Mode Voltage

VOS Distribution LTC6241 VOS Distribution LTC6241VOS Temperature CoefficientDistribution LTC6241

Supply Current vs Supply Voltage

Offset Voltagevs Input Common Mode Voltage

Input Bias Currentvs Common Mode Voltage

VOS Temperature CoefficientDistribution LTC6240VOS Distribution LTC6240

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT OFFSET VOLTAGE (V)

0

NUMBEROFUNITS

10

30

40

50

90

6241 G01

20

60

70

80

70 50 30 10 7030 5010

VS = 2.5VSO-8 PACKAGE


0

NUMBEROFUNITS

40

120

6241 G02

20

60

100

80

350 250 150 50 350150 25050

VS = 2.5VDD PACKAGE

DISTRIBUTION (V/C)

0

NUMBEROFUNITS

4

16

14

12

6241 G03

2

6

10

8

1.0 0.6 0.2 0.2 1.81.0 1.40.6

VS = 2.5V2 LOTS55C TO 125C


0

PERCENTOFUNITS

5

10

15

35

6241 G04

20

25

30

7090110 50 30 10 7030 5010

VS = 2.5V

DISTRIBUTION (V/C)

0

NUMBEROFUNITS

2

6

8

10

18

6241 G05

4

12

14

16

0.6 0.2 1.81.41.00.60.2

VS = 5V, 0VCM = 2.5V2 LOTS40C TO 125CSO-8 AND SOT23PACKAGES

TOTAL SUPPLY VOLTAGE (V)

0

2.0

2.5

3.0

6 10

6241 G06

1.5

1.0

2 4 8 12

0.5

0

SUP

PLYCURRENTPERAMP(mA)

3.5

TA = 55C

TA = 125C

TA = 25C

INPUT COMMON MODE VOLTAGE (V)

0.5

OFFSETVOLTAG

E(V)

300

200

250

150

100

050

50

100

150

200

250

3003.0

6241 G07

0 0.5 1.5 2.5 3.51.0 2.0 4.54.0

VS = 5V, 0V

TA = 55C

TA = 125C

TA = 25C

COMMON MODE VOLTAGE (V)0 1.0 2.0 3.0 4.00.5 1.5 2.5 3.5 4.5 5.0

INPUTBIASCURR

ENT(pA)

1000

100

10

0.1

1

6241 G08

VS = 5V, 0V

TA = 85C

TA = 125C

TA = 25C

COMMON MODE VOLTAGE (V)0.8 0.6 0.2 0.2 0.60.4 0 0.4 0.8 1.0

INPUTBIASCURR

ENT(pA)

700

100

200

300

400

500

600

400

300

200

100

0

6241 G09

VS = 5V, 0V

TA = 85C

TA = 125CTA = 25C

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Output Saturation Voltagevs Load Current (Output High)

Gain Bandwidth and PhaseMargin vs Temperature Open Loop Gain vs Frequency

Input Bias Current vs TemperatureOutput Saturation Voltagevs Load Current (Output Low)

Gain Bandwidth and PhaseMargin vs Supply Voltage

Slew Rate vs TemperatureCommon Mode Rejection Ratiovs FrequencyOutput Impedance vs Frequency


TEMPERATURE (C)25 45 65 85 10535 55 75 95 115 125

INPUTBIASCURRENT(pA)

6241 G10

VCM = VS/2

VS = 5V

VS = 10V

1000

100

10

0.1

1

LOAD CURRENT (mA)

0.01

OUTPUTLOWS

ATURATIONVOLTAGE(V)

0.1

0.1 10 100

6241 G11

0.0011

10

1

VS = 5V, 0V

TA = 125C

TA = 55C

TA = 25C

LOAD CURRENT (mA)

OUTPUTHIGHSATURATIONVOLTAGE(V)

0.1

0.1 10 100

6241 G12

0.011

10

1

VS = 5V, 0V

TA = 125C

TA = 55C

TA = 25C

TEMPERATURE (C)55 35 5 45 8515 25 65 105 125

GAINBANDWIDTH(MHz) P

HASEMARGIN(DEG)

70

30

40

50

60

0

10

20

30

40

6241 G13

CL = 5pFRL = 1k

PHASE MARGIN

GAIN BANDWIDTH

VS= 1.5V

VS = 5V

VS = 1.5V

VS= 5V

FREQUENCY (Hz)10k 100k 10M1M 100M

GAIN(dB)

PHASE(DEG)

20

010

10

20

30

40

50

60

70

80

80

4060

20

0

20

40

60

80

100

120

6241 G14

CL = 5pFRL = 1kVCM = VS/2

PHASE

GAINVS = 1.5V

VS = 5V

VS = 1.5V

VS= 5V

TOTAL SUPPLY VOLTAGE (V)0 4 82 6 10 12

GAINBANDWIDTH(MHz) P

HASEMARGIN(DEG)

70

60

40

50

0

10

20

30

6241 G15

TA = 25CCL = 5pFRL = 1k

PHASE MARGIN

GAIN BANDWIDTH

TEMPERATURE (C)55 35 5 45 8515 25 65 105 125

SLEWR

ATE(V

/s)

4

6

8

10

12

14

16

18

20

6241 G16

AV = 2RF = 1k, RG = 500CONDITIONS: SEE NOTE 12

VS = 5V RISING

VS

= 5V FALLING

VS = 2.5V FALLING

VS = 2.5V RISING

FREQUENCY (Hz)

OUTPUTIMPEDAN

CE()

10k 1M 10M

6241 G17

100k

TA = 25CVS = 2.5V

AV = 10

AV = 1

0.01

10

10k

1

0.10

100

1k

AV = 2


COMMONMODEREJE

CTION(dB)

10

0

10

20

30

40

50

60

70

100

90

80

6241 G18

TA = 25C

VS = 2.5V

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Input Capacitance vs Frequency

Minimum Supply VoltageOutput Short-Circuit Currentvs Power Supply Voltage Open Loop Gain

Open Loop Gain Open Loop Gain

Channel Separation vs FrequencyPower Supply Rejection Ratiovs Frequency

Offset Voltage vs Output Current


POWERSUPPLYREJECTIONRATIO(dB)

90

80

70

60

50

40

30

20

10

01k 100k 1M 100M10k 10M

FREQUENCY (Hz)

6241 G20

TA = 25CVS = 2.5V

POSITIVE SUPPLY

NEGATIVE SUPPLY


VOLTAGEGAIN(dB)

120

0

10

20

30

40

50

60

70

110

100

90

80

6241 G19

TA = 25CVS= 2.5V

AV = 1

INPUTCAPACITANCE(pF)

16

14

12

10

8

6

4

2

01k 100k 1M 100M10k 10M

FREQUENCY (Hz)

6241 G21

VS = 1.5V

CCM

TOTAL SUPPLY VOLTAGE (V)0 2 61 4 83 75 9 10

CHA

NGEINOFFSETVOLTAGE(V)

100

20

40

60

80

100

80

40

60

20

0

6241 G22

VCM = VS/2

TA = 125C

TA = 55C

TA = 25C

POWER SUPPLY VOLTAGE (V)1.5 2.5 4.52.0 3.53.0 4.0 5.0

OUTPUTSHORT-CIRCUITCURRENT(mA)

50

10

20

30

40

50

40

20

30

10

0

6241 G23

SOURCING

SINKINGTA = 125C

TA = 125C

TA = 55C

TA = 55C

TA = 25C

OUTPUT VOLTAGE (V)0 0.5 2.51.51.0 2.0 3.0

INPUTVOLTAGE(V)

120

100

20

40

60

80

0

6241 G24

TA = 25CVS = 3V, 0V

RL = 100k

RL = 10k

OUTPUT VOLTAGE (V)0 1 2 53 4

INPUTVOLTAGE(V)

120

100

20

40

60

80

20

0

6241 G25

TA = 25CVS = 5V, 0V

RL = 1k

RL = 10k

OUTPUT VOLTAGE (V)5 4 023 1 51 2 3 4

INPUTVOLTAGE(V)

100

20

40

60

80

60

40

20

0

6241 G26

TA = 25CVS = 5V

RL = 1k

RL = 10k

OUTPUT CURRENT (mA)50 40 30 20 10 10 30200 40 50

OFFSETVOLTAG

E(V)

500

400

100

200

300

500

400

300

100

200

0

6241 G27

TA = 125C

TA = 55C

TA = 25C

VS = 5V

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Warm-Up Drift vs Time Noise Voltage vs Frequency

Series Output Resistance andOvershoot vs Capacitive Load

Series Output Resistance andOvershoot vs Capacitive Load

0.1Hz to 10Hz Voltage Noise

Noise Current vs FrequencyMinimum Output SeriesResistance vs Capacitive Load

Settling Time vs Output Step(Inverting)

Settling Time vs Output Step(Non-Inverting)


TIME AFTER POWER UP (s)0 10 30205 40 605015 3525 45 55

CHANGEINOFFSETVOLTAGE(V)

25

15

20

5

0

10

5

6241 G28

TA = 25C

VS = 1.5V

VS = 2.5V

VS = 5V

FREQUENCY (Hz)

20

10NOISEVOLTAGE(nV/Hz)

30

40

50

60

1 100 1k 100k

6241 G29

010 10k

TA = 25CVS = 2.5VVCM = 0V

TIME (1s/DIV)

VOLTAGENOISE(200nV/DIV)

6241 G30

VS = 5V, 0V

FREQUENCY (Hz)

1NOISECURRENT(fA/Hz)

10

100 10k 100k

6241 G31

0.11k

1000

100

TA = 25C

VS = 2.5V

VCM = 0V

CAPACITIVE LOAD (pF)10

OVERSHOOT(%)

60

50

40

30

20

10

0100 1000

6241 G32

RS = 50

RS = 10

VS = 2.5VAV = 1

RS1k 1k

CL

75pF

+

0.01F 1F0.1F1000pF100pF

CAPACITIVE LOAD

1

OUT

PUTSERIESRESISTANCE()

10

10pF 10F

6241 G33

0.1

1000

100

VS= 2.5V

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Distortion vs Frequency Distortion vs FrequencyMaximum Undistorted OutputSignal vs Frequency

Distortion vs Frequency

Large Signal Response Large Signal Response Output Overdrive Recovery

Small Signal ResponseDistortion vs Frequency


FREQUENCY (Hz)10k 100k 1M 10M

OUTPUTVOLTAGESWINGING(VP-P

)

10

7

4

1

8

5

2

9

6

3

6241 G37

TA = 25CVS = 5VHD2, HD3 < 40dBc

AV = +2

AV = 1


DISTORTION(dBc)

30

60

90

100

50

80

40

70

6241 G38

VS = 2.5VAV = 1VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD


DISTORTION(dBc)

30

60

90

100

50

80

40

70

6241 G39

VS = 5VAV = 1VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD


DISTORTION(dBc)

30

60

90

100

50

80

40

70

6241 G40

VS = 2.5VAV = 2VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD


DISTORTION(dBc)

30

60

90

100

50

80

40

70

6241 G41

VS = 5VAV = 2VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD

VS = 2.5VAV = 1RL =

6241 G42

0V

VS = 5VAV = 1RL =

6241 G43

0V

VS = 2.5VAV = 1RL = 1k

6241 G44

0V

VS = 2.5VAV = 3RL =

500ns/DIV 6241 G45

0V

0V

VIN(1V/DIV)

VOUT(2V/DIV)

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Amplifier Characteristics

Figure 1 is a simplified schematic of the amplifier, which

has a pair of low noise input transistors M1 and M2. Asimple folded cascode Q1, Q2 and R1, R2 allow the inputstage to swing to the negative rail, while performing levelshift to the differential drive generator. Low offset voltageis accomplished by laser trimming the input stage.

Capacitor C1 reduces the unity cross frequency and im-proves the frequency stability without degrading the gainbandwidth of the amplifier. Capacitor CM sets the overallamplifier gain bandwidth. The differential drive generatorsupplies signals to transistors M3 and M4 that swing theoutput from rail-to-rail.

The photo of Figure 2 shows the output response to aninput overdrive with the amplifier connected as a voltagefollower. If the negative going input signal is less thana diode drop below V, no phase inversion occurs. Forinput signals greater than a diode drop below V, limit thecurrent to 3mA with a series resistor RS to avoid phaseinversion.

ESD

The LTC6240/LTC6241/LTC6242 have reverse-biased ESD

protection diodes on all input and outputs as shown inFigure 1. If these pins are forced beyond either supply,unlimited current will flow through these diodes. If thecurrent is transient and limited to one hundred milliampsor less, no damage to the device will occur.

The amplifier input bias current is the leakage current ofthese ESD diodes. This leakage is a function of the tempera-ture and common mode voltage of the amplifier, as shown

in the Typical Performance Characteristics curves.

Noise

The LTC6240/LTC6241/LTC6242 exhibit exceptionallylow 1/f noise in the 0.1Hz to 10Hz region. This 550nVP-Pnoise allows these op amps to be used in a wide varietyof high impedance low frequency applications, wherezero-drift amplifiers might be inappropriate due to theircharge injection.

In the frequency region above 1kHz the LTC6240/LTC6241/

LTC6242 also show good noise voltage performance. Inthis frequency region, noise can easily be dominated bythe total source resistance of the particular application.Specifically, these amplifiers exhibit the noise of a 3.1kresistor, meaning it is desirable to keep the source andfeedback resistance at or below this value, i.e. RS + RG||RFB 3.1k. Above this total source impedance, the noisevoltage is not dominated by the amplifier.

Noise current can be estimated from the expression in =2qIB, where q = 1.6 1019 coulombs. Equating 4kTRf

and R2qI

Bf

shows that for source resistors below 50Gthe amplifier noise is dominated by the source resistance.See the Typical Performance Characteristics curve NoiseCurrent vs Frequency.

Figure 1. Simplified Schematic Figure 2. Unity Gain Follower Test Circuit

APPLICATIONS INFORMATION

R2

Q2

6241 F01

VIN+

ITAIL

VIN

VO

V+

V+

VV

V

CM

DESD5

DIFFERENTIALDRIVE

GENERATOR

BIAS

DESD6

V+

DESD2

V+

DESD4

V

DESD1

V

DESD3

R1

Q1

M2M1

M3

M4

C1CLAMP

+2.5V

2.5V

6241 F02

+

LTC6240

RS

VIN VOUT

VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE

VDD =+2.5V

VSS =2.5V

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Proprietary design techniques are used to obtain simulta-neous low 1/f noise and low input capacitance. Low inputcapacitance is important when the amplifier is used with

high value source and feedback resistors. High frequencynoise from the amplifier tail current source, ITAIL in Fig-ure 1, couples through the input capacitance and appearsacross these large source and feedback resistors. As anexample, the photodiode amplifier of Figure 15 on the lastpage of this data sheet shows the noise results from theLTC6241 and the results of a competitive CMOS amplifier.The LTC6241 output is the ideal noise of a 1M resistorat room temperature, 130nVHz.

Half the Noise

The circuit shown in Figure 3 can be used to achieve even

lower noise voltage. By paralleling 4 amplifiers the noisevoltage can be lowered by 4, or half as much noise. The comes about from an RMS summing of uncorrelatednoise sources. This circuit maintains extremely high inputresistance, and has a 250 output resistance. For loweroutput resistance, a buffer amplifier can be added withoutinfluencing the noise.

Stability

The good noise performance of these op amps can be at-tributed to large input devices in the differential pair. Above

several hundred kilohertz, the input capacitance rises andcan cause amplifier stability problems if left unchecked.When the feedback around the op amp is resistive (RF), apole will be created with RF, the source resistance, sourcecapacitance (RS, CS), and the amplifier input capacitance.In low gain configurations and with RF and RS in eventhe kilohm range (Figure 4), this pole can create excessphase shift and possibly oscillation. A small capacitor CFin parallel with RF eliminates this problem.

Low Noise Single-Ended Input to Differential Output

AmplifierThe circuit on the first page of the data sheet is a low noisesingle-ended input to differential output amplifier, with a200k input impedance. The very low input bias currentof the LTC6241 allows for these large input and feedbackresistors. The 200k resistors, R1 and R2, along with C1 andC2 set the 3dB bandwidth to 80kHz. Capacitor C3 is usedto cancel effects of input capacitance, while C4 adds phaselead to compensate the phase lag of the second amplifier.

Figure 3. Parallel Amplifier Lowers Noise by 2x Figure 4. Compensating Input Capacitance


10

6241 F03

+1/4

LTC6242

1k

1k

10

+1/4

LTC6242

1k

1k

10

+1/4

LTC6242

1k

1k

10

+ 1/4LTC6242

1k

1k

+2.5

2.5

VIN VO

+

CINCS

6241 F04

RF

RSOUTPUT

CF

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The op amps good input offset voltage match and lowinput bias current means that the typical differential outputoffset voltage is less than 40V. A noise spectrum plot of

the differential output is shown in Figure 5.

The guard ring should extend as far as necessary to shieldthe high impedance signal from any and all leakage paths.Figure 6 shows the use of a guard ring on the LTC6241 in

a unity gain configuration. In this case the guard ring isconnected to the output and is shielding the high impedancenoninverting input from V. Figure 7 shows the invertinggain configuration.

A Digitally Programmable AC Difference Amplifier

The LTC6241 configured as a difference amplifier, can becombined with a programmable gain amplifier (PGA) toobtain a low noise high speed programmable differenceamplifier. Figure 8 shows the LTC6241 based as a single-

supply AC amplifier. One LTC6241 op amp is used at thecircuits input as a standard four resistor difference amplifier.

Figure 5. Differential Output Noise

Achieving Low Input Bias Current

The DD package is leadless and makes contact to the PCBbeneath the package. Solder flux used during the attach-ment of the part to the PCB can create leakage current

paths and can degrade the input bias current performanceof the part. All inputs are susceptible because the backsidepaddle is connected to V internally. As the input voltagechanges or if V changes, a leakage path can be formedand alter the observed input bias current. For lowest biascurrent, use the LTC6240/LTC6241 in the SO-8 and providea guard ring around the inputs that are tied to a potentialnear the input voltage.

Layout Considerations and a PCB Guard Ring

In high source impedance applications such as pH probes,

photodiodes, strain gauges, et cetera, the low input biascurrent of these parts requires a clean board layout tominimize additional leakage current into a high impedancesignal node. A mere 100G of PC board resistancebetween a 5V supply trace and an input trace adds 50pAof leakage current, far greater then the input bias currentof the operational amplifier. A guard ring around the highimpedance input traces driven by a low impedance sourceequal to the input voltage prevents such leakage problems.

Figure 6. Sample Layout. Unity Gain Configuration, Using GuardRing to Shield High Impedance Input from Board Leakage

Figure 7. Sample Layout. Inverting Gain Configuration, UsingGuard Ring to Shield High Impedance Input from Board Leakage


FREQUENCY (kHz)0 20 6010 40 8030 7050 90 100D

IFFERENTIALOUTPUTVOLTAGEDENSITY(nV/Hz)

140

60

80

100

120

0

20

40

6241 F05

VS = 2.5VTA = 25C3dB BW = 80kHz

LTC6241 S8

R

OUT+

IN

IN+

V

LEAKAGECURRENT

NO LEAKAGECURRENT

GUARD

RING

NO SOLDER MASKOVER THE GUARD RING

LTC6241 F06

LTC6241 S8

LTC6241 F07

R

R

OUT+

IN

IN+

V

VIN

GND

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LTC6240/LTC6241/LTC6242

22

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Figure 8. Wideband Difference Amplifier with HighInput Impedance and Digitally Programmable Gain

The low bias current and current noise of the LTC6241allow the use of high valued input resistors, 100k orgreater. Resistors R1, R2, R3 and R4 are equal and thegain of the difference amplifier is one. An LTC6910-2 PGAamplifies the difference amplifier output with invertinggains of 1, 2, 4, 8, 16, 32 and 64. The second

LTC6241 op amp is used as an integrator to set the DCoutput voltage equal to the LT6650 reference voltage VREF.The integrator drives the PGA analog ground to providea feedback loop, in addition to blocking any DC voltagethrough the PGA. The reference voltage of the LT6650can be set to a voltage from 400mV to V+ 350mV withresistors R5 and R6. If R6 is 20k or less, the error dueto the LT6650 op amp bias current is negligible. The lowvoltage offset and drift of the LTC6241 integrator will not

contribute any significant error to the LT6650 referencevoltage. The LT6650 VREF voltage has a maximum errorof 2% with 1% resistors. The upper 3dB frequency of

the amplifier is set by resistor R3 and capacitor C1 andis limited by the bandwidth of the PGA when operated ata gain of 64. Capacitor C2 is equal to C1 and is added tomaintain good common mode rejection at high frequency.The lower 3dB frequency is set by the integrator resistorR7, capacitor C3, and the gain setting of the LTC6910-2PGA. This lower 3dB zero frequency is multiplied by thePGA gain. The rail-to-rail output of the LTC6910-2 PGAallows for a maximum output peak-to-peak voltage equalto twice the VREF voltage. At the maximum gain setting of64, the maximum peak-to-peak difference between inputsV1 and V2 is equal to twice VREF divided by 64.

Example Design: Design a programmable gain AC differ-ence amplifier, with a bandwidth of at least 10Hz to 100kHz,an input impedance equal to or greater than 100k, andan output DC reference equal to 1V.

a. Select input resistors R1, R2, R3 and R4 equal to100k.

b. If the upper 3dB frequency is 100kHz then C1 = 1/(2 R2 f3dB) = 1/(6.28 100k 100kHz) = 15pF (to

the nearest 5% value) and C2 = C1 = 15pF.c. Select R7 equal to one 1M and set the lower 3dB

frequency to 10Hz at the highest PGA gain of 64, thenC3 = Gain/(2 R7 f3dB) = 64/(6.28 100k 10Hz)= 1F. Lower gains settings will give a lower f3dB.

d. Calculate the value of R5 to set the LT6650 referenceequal to 1V;

VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF 1). ForR6 = 20k, R5 = 30k

With VREF

= 1V the maximum input difference voltageis equal to 2V/64 = 31.2mV.

40nVpp Noise, 0.05V/C Drift, Chopped FETAmplifier

Figure 9s circuit combines the 5V rail-to-rail performanceof the LTC6241HV with a pair of extremely low noise JFETsconfigured in a chopper based carrier modulation scheme


6241 F08

R4

R3

R2

+1/2

LTC6241

C1

C2

1F

0.1F8 7 6 5

G2 G1 G0

1

12

2 3 4

AGNDOUT IN V

V+

0.1F

V+

V+

R1

R1 = R2 = R3 = R4

V2

V1

R5

1k

1000pF

3 4

5

R620k

LTC6910-2

LT6650

VOUT

VREF

+

1/2LTC6241

C3 R7100

1F

DIGITAL INPUTS

G1G2 GO

GAIN

0011001

1

0000111

1

0101010

1

01248

1632

64

VOUT = (V1 V2) GAIN + VREF

VR

R

R k V

REF

REF

= +

= =

0 45

61

5 10 5 2 R6 20

.

k

d BANDWIDTH f f

fR C

HIGH LOW

HIGH

3

1

2 3

=

=P 1 2 7 3

fGAIN

R CLOW=

P

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Figure 9. Ultralow Noise Chopper Amplifier

to achieve an extraordinarily low noise and low DC drift.The performance of this circuit is suited for the demand-ing transducer signal conditioning situations such as high

resolution scales and magnetic search coils.The LTC1799s output is divided down to form a 2-phase925Hz square wave clock. This frequency, harmonicallyunrelated to 60Hz, provides excellent immunity to harmonicbeating or mixing effects which could cause instabilities.S1 and S2 receive complementary drive, causing A1 tosee a chopped version of the input voltage. A1s squarewave output is synchronously demodulated by S3 andS4. Because these switches are synchronously driven

with the input chopper, proper amplitude and polarityinformation is presented to A2, the DC output amplifier.This stage integrates the square wave into a DC voltage,

providing the output. The output is divided down (R2 andR1) and fed back to the input chopper where it serves asa zero signal reference. Gain, in this case 1000, is set bythe R1-R2 ratio. Because A1 is AC coupled, its DC offsetand drift do not affect the overall circuit offset, resultingin the extremely low offset and drift noted. The JFETshave an input RC damper that minimizes offset voltagecontribution due to parasitic switch behavior, resulting inthe 1V offset specification.


+

+

BIAS

10M

1F

141516

32

1

S4

S3 240k

1F

OUTPUTA2

LTC6241HV

A1LTC6241HV

1F

INPUT

10k

8

7

11

S1S2

9

6

10

R210k

R110

NOISEOFFSET

DRIFT

OPEN-LOOP GAINI

= 40nVP-P 0.1Hz TO 10Hz= 1V= 0.05V/C

R210

= 10= 500pA

+1GAIN =

9

0.01F

1

1

2

2

6241 F09

= 0.1% METAL FILM RESISTOR= 1% METAL FILM RESISTOR

***

= LTC201 QUAD

= LSK389= LINEAR INTEGRATED SYSTEMS

FREMONT, CA

1F

DIVRSET

LTC1799

V+

74C90 10

18.5kHz

OUT 74C74 2

TO1

POINTS

TO2

POINTS

Q Q

54.2k*

TO LTC201 V+ PIN

5V

5V 5V

5V 5V

925Hz

TO LTC201 V PIN

1F

898**

5V

5V

898**

LSK389

30.1

499**

++

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LTC6240/LTC6241/LTC6242

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by the sensor is forced across the feedback capacitorby the op amp action. Because the feedback capacitoris 100 times smaller than the sensor, it will be forced to

100 times what would have been the sensors open circuitvoltage. So the circuit gain is 100. The benefit of this ap-proach is that the signal gain of the circuit is independentof any cable capacitance introduced between the sensorand the amplifier. Hence this circuit is favored for remoteaccelerometers where the cable length may vary. Difficultieswith the circuit are inaccuracy of the gain setting with thesmall capacitor, and low frequency cutoff due to the biasresistor working into the small feedback capacitor.

Figure 12 shows a noninverting amplifier approach. This

approach has many advantages. First of all, the gain is setaccurately with resistors rather than with a small capaci-tor. Second, the low frequency cutoff is dictated by thebias resistor working into the large 770pF sensor, ratherthan into a small feedback capacitor, for lower frequencyresponse. Third, the noninverting topology can be paral-leled and summed (as shown) for scalable reductions involtage noise. The only drawback to this circuit is that theparasitic capacitance at the input reduces the gain slightly.This circuit is favored in cases where parasitic inputcapacitances such as traces and cables will be relatively

small and invariant.

The noise measured over a 50 second interval, in Figure 10,is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-tributed to the input JFETs die size and current density.

Figure 11. Classical Inverting Charge Amplifier Figure 12. Low Noise Noninverting Shock Sensor Amplifier

Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth

Low Noise Shock Sensor Amplifiers

Figures 11 and 12 show the amplifiers realizing two dif-ferent approaches to amplifying signals from a capacitivesensor. The sensor in both cases is a 770pF piezoelectricshock sensor accelerometer, which generates charge underphysical acceleration.

Figure 11 shows the classical charge amplifier approach.The LTC6240 is in the inverting configuration so the sensor

looks into a virtual ground. All of the charge generated


5s/DIV6241 F10

20nV/DIV

BIAS RESISTORVISHAY-TECHNO

CRHV2512AF1007G(OR EQUIVALENT)

MAINGAIN-SETTINGELEMENT IS ACAPACITOR

SHOCK SENSORMURATA-ERIEPKGS-00LD

770pF

CABLE HAS

UNKNOWN C

Rf1G

6241 F11

VOUT = 110mV/g

+LTC6240

Cf7.7pF

BIAS RESISTORVISHAY-TECHNO

CRHV2512AF1007G

(OR EQUIVALENT)

1G

VS+

6241 F12

10k

1k

1k

100

VOUT

= 110mV/gVS = 1.4V to 5.5VBW = 0.2Hz to 10kHz

VOUT

+1/2

LTC6241HV

VS

10k100

+1/2

LTC6241HV

SHOCK SENSORMURATA-ERIEPKGS-00LD

770pF

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1M Transimpedance Amplifier with 43nV/HzOutput Noise

In a normal 1M transimpedance amplifier, like that shownon the back page of this data sheet, the output noise densitymust be at least 130nV/Hz at room temperature. This istrue even should the op amp be perfectly noiseless, becausethe 1M resistor provides 130nV/Hz of voltage noise atroom temperature independently of the op amp.

The circuit of Figure 13 provides an overall transimpedancegain of 1M, but it has an output noise density of only43nV/Hz, about 1/3 of the normal transimpedance ampli-fier. It does this by taking a higher initial transimpedancegain of 10M and then attenuating by a factor of 10. The

transistor section provides voltage gain and works on a54V supply voltage to guarantee adequate output swing.

By achieving an output swing of 50V before attenuation,the circuit provides an output swing to 5V after attenu-ation. The 10M resistor sets the gain of the TIA stage

and has a noise density of 400nV/Hz. After attenuation,the effective TIA gain drops to 1M while the noise floordrops to 40nV/Hz, which clearly dominates the observed43nV/Hz. Note the additional benefit that the offset voltageof the op amp is divided by 10. Worst-case output offsetfor this circuit is 150V over temperature.

Reference Buffer

Figure 14 shows the LTC6240 being utilized as a bufferin conjunction with the LT1019 reference. The passive

R-C filter attenuates the reference noise and the LTC6240provides a low noise buffer, resulting in an output noiseof 8nV/Hz.

Figure 13. 1M Transimpedance Amplifier with 43nV/Hz Output Noise

Figure 14. Low Noise Reference Buffer


5V

54V

5V

1.5V

3pF

PHOTODIODE

6241 F135V

10k

+LTC6240HV

100pF

10M1%

0.3pF

1k

10k 2.4k

33k

MPSA06

43k

9.09k1%1/4W

1k1%

VOUT1M GAIN(1V/A)

10M GAIN(10V/A)

MPSA06

5V

5V6241 F14

0.2

+

LTC6240HV

1M

10FCERAMICOR FILM

8nV/Hz VOUT1F

LT1019-2.5180nV/Hz

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DD Package8-Lead Plastic DFN (3mm 3mm)

(Reference LTC DWG # 05-08-1698)

PACKAGE DESCRIPTION

3.00 p0.10(4 SIDES)

NOTE:1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEWEXPOSED PAD

1.65 p 0.10(2 SIDES)

0.75 p0.05

R = 0.125TYP

2.38 p0.10

14

85

PIN 1TOP MARK

(NOTE 6)

0.200 REF

0.00 0.05

(DD8) DFN 0509 REV C

0.25 p 0.05

2.38 p0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.65 p0.05(2 SIDES)2.10 p0.05

0.50BSC

0.70 p0.05

3.5 p0.05

PACKAGEOUTLINE

0.25 p 0.050.50 BSC

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27

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DHC Package16-Lead Plastic DFN (5mm 3mm)


PACKAGE DESCRIPTION

3.00 0.10(2 SIDES)

5.00 0.10(2 SIDES)

NOTE:1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC

PACKAGE OUTLINE MO-2292. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 0.10

BOTTOM VIEWEXPOSED PAD

1.65 0.10(2 SIDES)

0.75 0.05

R = 0.115TYP

R = 0.20TYP

4.40 0.10(2 SIDES)

18

169

PIN 1TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 0.05

(DHC16) DFN 1103

0.25 0.05

PIN 1NOTCH

0.50 BSC

4.40 0.05(2 SIDES)

RECOMMENDEDSOLDER PAD PITCH AND DIMENSIONS

1.65 0.05(2 SIDES)2.20 0.05

0.50 BSC

0.65 0.05

3.50 0.05

PACKAGEOUTLINE

0.25 0.05

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LTC6240/LTC6241/LTC6242

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PACKAGE DESCRIPTION

GN Package16-Lead Plastic SSOP (Narrow .150 Inch)


GN16 (SSOP) 0204

1 2 3 4 5 6 7 8

.229 .244

(5.817 6.198)

.150 .157**

(3.810 3.988)

16 15 14 13

.189 .196*

(4.801 4.978)

12 11 10 9

.016 .050

(0.406 1.270)

.015 .004

(0.38 0.10) 45

0 8 TYP.007 .0098

(0.178 0.249)

.0532 .0688

(1.35 1.75)

.008 .012

(0.203 0.305)TYP

.004 .0098

(0.102 0.249)

.0250

(0.635)BSC

.009

(0.229)REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 BSC.0165 .0015

.045 .005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASHSHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES(MILLIMETERS)

NOTE:1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

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LTC6240/LTC6241/LTC6242

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S5 Package5-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1635 Rev B)

1.50 1.75(NOTE 4)

2.80 BSC

0.30 0.45 TYP5 PLCS (NOTE 3)

DATUM A

0.09 0.20(NOTE 3) S5 TSOT-23 0302 REV B

PIN ONE

2.90 BSC(NOTE 4)

0.95 BSC

1.90 BSC

0.80 0.90

1.00 MAX0.01 0.10

0.20 BSC

0.30 0.50 REF

NOTE:1. DIMENSIONS ARE IN MILLIMETERS2. DRAWING NOT TO SCALE3. DIMENSIONS ARE INCLUSIVE OF PLATING4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR5. MOLD FLASH SHALL NOT EXCEED 0.254mm6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.62MAX

0.95REF

RECOMMENDED SOLDER PAD LAYOUTPER IPC CALCULATOR

1.4 MIN2.62 REF

1.22 REF

PACKAGE DESCRIPTION

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LTC6240/LTC6241/LTC6242

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S8 Package8-Lead Plastic Small Outline (Narrow .150 Inch)


PACKAGE DESCRIPTION

.016 .050

(0.406 1.270)

.010 .020

(0.254 0.508) 45

0 8 TYP.008 .010

(0.203 0.254)

SO8 0303

.053 .069

(1.346 1.752)

.014 .019

(0.355 0.483)TYP

.004 .010

(0.101 0.254)

.050

(1.270)BSC

1 2 3 4

.150 .157

(3.810 3.988)

NOTE 3

8 7 6 5

.189 .197

(4.801 5.004)NOTE 3

.228 .244

(5.791 6.197)

.245MIN .160 .005

RECOMMENDED SOLDER PAD LAYOUT

.045 .005.050 BSC

.030 .005TYP

INCHES

(MILLIMETERS)

NOTE:1. DIMENSIONS IN

2. DRAWING NOT TO SCALE3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

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LTC6240/LTC6241/LTC6242

31

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

E 07/10 Update to Simplified Schematic (Figure 1) 19

(Revision history begins at Rev E)

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LTC6240/LTC6241/LTC6242

PART NUMBER DESCRIPTION COMMENTS

LTC1151 15V Zero-Drift Op Amp Dual High Voltage Operation 18V

LT1792 Low Noise Precision JFET Op Amp 6nV/Hz Noise, 15V Operation

LTC2050 Zero-Drift Op Amp 2.7 Volt Operation, SOT-23

LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amp Dual/Quad Version of LTC2050 in MS8/GN16 PackagesLTC2054/LTC2055 Single/Dual Zero-Drift Op Amp Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages

LTC6244 Dual 50MHz Rail-to-Rail Op Amp 100V VOS(MAX), 1pA IBIAS, 40V/V, Slew Rate

Figure 15. Ultralow Noise 1M 150kHz Photodiode Amplifier

LTC6241 Output Noise Spectrum. 1M Resistor Noise

Dominates; Ideal Performance

Competition Output Noise Spectrum. Op Amp Noise Dominates;

Performance Compromised

RELATED PARTS

TYPICAL APPLICATION

R2

1.69k

C3180pF

C11500pF

+1.5V

1.5V

1.5V

SFH213FAOR EQUIVALENT

(4pF) 6241 TA02a

RF1M

R1

866

+1/2LTC6241

+1/2

LTC6241

C2

1500pF

CF1pF

1M TIA 150kHz 3RD ORDER BUTTERWORTH FILTER

R3

2k

1kHz 101kHz10kHz/DIV

6241 TA02b

0V

30nV/HzPERDIV

1kHz 101kHz

6241 TA02c

10kHz/DIV

0V

30nV/HzPERDIV

624012 fe

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