60-ghz cmos transceivers: why and how? - ieee · 60-ghz cmos transceivers: why and how? behzad...
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60-GHz CMOS Transceivers: Why and How?
Behzad Razavi
Electrical Engineering Department
University of California, Los Angeles
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Outline
IntroductionReceiver Front EndTransmitter Front EndFrequency DividerReflectionsConclusion
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Why 60 GHz?
7 GHz of Unlicensed BandPossibility of Realizing (Multiple) On-Chip Antennas:- Low-Cost Packaging- Differential Operation Higher Output Power- No Need for T/R Switch- No Need for AC Coupling- No Need for High-Frequency ESD DevicesPossible Applications:- Gb/s Networks, e.g., Video Streaming- Highly-Interconnected Networks
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Highly-Interconnected Networks
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Why CMOS?
Need Complex Modulation Techniques:- OFDM- QAM- Frequency Hopping?Need Sophisticated Analog Calibration:- I/Q Matching at 60 GHz?!- Wideband Analog Baseband Filters- Multitude of High-Speed ADCsLarge Fractional Bandwidth (>10%):- Several Staggered High-Q Signal Paths- Multiple VCOs and Tuned Dividers
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Challenges
Limited transistor speed Need for inductors and transmission lines.Inductor footprints Long interconnectsInductor Q's tend to saturate around 25.Varactor Q's likely to be lower than inductor Q's.Lossy on-chip antennas BeamformingPassive and active device modelingGain and phase mismatches, etc.
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Transceiver Building Blocks
ReceiverFront End
Designed in 0.13-μm CMOS; migrating to 90-nm process.
JSSC, Jan.06 RFIC Symp, June 06
RFIC Symp, June 06
TransmitterFront End
FrequencyDivider
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Receiver Architecture
Balun
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Raw Speed of MOS Devices
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Coplanar Line Microstrip Line
Spiral Inductors vs. Transmission Lines
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Folded Microstrip
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Choice of Linewidth
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S
A
A'
Choice of Line Spacing
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Choice of Line Spacing
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Cascode vs. Common-Gate LNA
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Simplified LNA
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Complete LNA
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Mixer Design
Conventional Mixer Proposed Mixer
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On-Chip Balun
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Receiver Floor Plan
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Input
LO
BB
Out
put
Active Area = 300 um x 400 um
Die Photograph
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Measured Performance
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3-dB improvement in SNR for twice the power consumption and area.
Other Thoughts
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Transmitter Front End
Slot Antenna- Large Area- High LossDipole- Narrow Footprint- Moderate Loss(~6 dB)
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Transmitter Design
Pout = -10 dBm
Psupp = 44 mW
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Nested Inductors
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Effect of Mutual Coupling
168170172174176178180182184186188
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Mutual Coupling (k)
Out
put V
olta
ge (m
V)
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Die Photograph
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Measurement Setup
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Antenna Radiation Pattern
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Flipflop-Based Dividers Miller DividerInjection-Locked Divider
Conventional Divider Topologies
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Injection-Locked Divider
Narrow frequency range; inversely proportional to tank Q:
4π
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Phase noise degrades if, due to mismatches, input frequency is not equal to 2ω0.
Phase Noise Degradation
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Increasing the Range
[Rategh et al, JSSC, May 00]
Ganged tuning does not overcome frequency
mismatch.
Difficult to guarantee natural frequency of divider
tracks that of VCO.
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Tracking Issues
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Phase-Locked Divider
Constant phase noise across range if gain of PD remains constant.No trade-off with tank Q. PD circuit must be very simple and experience complete switching.
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Phase-Locked Divider
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Die Photograph
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Measured Output
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Phase Noise across Range
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Divider
Challenges Revisited
LO (I/Q) GenerationLO DivisionLO Distribution
LNA I/Q Mixers
QuadratureVCO
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Conclusion
60-GHz transceivers can form highly-intercon-nected networks carrying high data rates. Nested inductors allow compact layout andshorter interconnects.Phase-locked dividers can provide a widefrequency range.Direct-conversion transceivers face difficultissues with respect to LO generation, division, and distribution.