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PART 1.1 : Load capacitances for each node in the circuit

Interpolation

X1 be the value of propagation delay nearest to the simulated value but greater than it and Y1 be the corresponding

capacitance.

X be the value of propagation delay simulated value Y be the corresponding capacitance to be found.

X2 be the value of propagation delay nearest to the simulated value but less than it and Y2 be the corresponding

capacitance.

Then by interpolation

( 1)

1 =

(1 2)

1 2

1. NAND followed by NOR:

Input slew Rising Propagation

delay

Falling Propagation

delay

Load capacitance estimated using

NLDM tables

Average capacitance

Rise delay Fall delay

10ps 50.33ps 50.13ps 4.48fF 2.20fF3.51fF20ps 53.14ps 51.42ps 4.437fF 2.80fF

30ps 56.30ps 52.52ps 4.443fF 2.70fF

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2. INVERTER followed by NOR:

Input slew Rising Propagation

delay

Falling Propagation

delay

Load capacitance estimated using

NLDM tables

Average capacitance

Rise delay Fall delay

10ps 37.63ps 40.55ps 5.92fF 4.108fF4.969fF20ps 40.54ps 42.13ps 5.85fF 4.037fF

30ps 43.75ps 44.65ps 5.86fF 4.039fF

3. NOR followed by NAND:

Input slew Rising Propagation

delay

Falling Propagation

delay

Load capacitance estimated using

NLDM tables

Average capacitance

Rise delay Fall delay

10ps 52.36ps 83.35ps 3.14fF 2.84fF

2.98fF20ps 55.84ps 84.7ps 3.18fF 2.824fF

30ps 59.09ps 86.1ps 3.103fF 2.79fF

4. NOR followed by INVERTER:

Input slew Rising Propagationdelay

Falling Propagationdelay

Load capacitance estimated usingNLDM tables

Average capacitance

Rise delay Fall delay

10ps 50.12ps 80.34ps 2.679fF 2.393fF

2.50fF20ps 53.61ps 81.21ps 2.714fF 2.319fF

30ps 56.71ps 82.56ps 2.614fF 2.295fF

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PART 1.2: Circuit path delay estimation :

To get the worst case delay for the above circuit we apply VDD from bit0 to bit4 and apply controlling inputs to bit5 an

bit6.

By doing so we make all the gates in the circuit act as inverters, and also get the worst case delay for the circuit.

By simulating the above circuit for the input combination 111111 -> 001111 and for i/p slew of 10ps

we get the Falling delay = 354.3ps and the Rising delay = 336.4ps

Theoretically calculating we get:

Falling delay = rise + fall + rise + fall + rise + fall = 50.33 x 3 + 83.35 X 2 + 80.34 = 398.03ps

Rise delay = fall + rise + fall + rise + fall + rise = 50.13 x 3 + 52.36 x 2 + 50.12 = 305.23ps

Percentage error :

For Fall case:

[(398 - 354.3) / 354.3 ] x 100 = 12.34%

For rise case:

[(336.4 - 305.23) / 336.4 ] x 100 = 9.265%

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Part 1.3: Delay Estimation for circuit with interconnect capacitances:

Assuming that each interconnect has an additional 10fF capacitance added to it:

NAND followed by NOR interface has capacitance: 10f + 3.51f = 13.51fF ;

INVERTER followed by NOR interface has capacitance : 10f + 4.969f = 14.969fF ;

NOR followed by NAND interface has capacitance : 10f + 2.98f = 12.98fF ;

NOR followed by INVERTER interface has capacitance : 10f + 2.50f = 12.50fF ;

Simulation results for this modified circuit gives the following values:

Fall delay = 638ps; Rise delay = 610.3ps;

Estimation of node capacitors sing NLDM tables:

NODE INPUT SLEW Delay estimated using NLDM

Rise delay Fall delay

NAND - NOR 10ps 79.62ps 94.324ps

INVERTER - NOR 10ps 66.99pf 85.77ps

NOR - NAND 10ps 84.34ps 129ps

NOR - INVERTER 10ps 82.92ps 128ps

Theoretically calculating we get:

Falling delay = rise + fall + rise + fall + rise + fall = 79.62 x 3 + 129 x 2 + 128 = 624.86ps

Rise delay = fall + rise + fall + rise + fall + rise = 94.324 x 3 + 84.34 x 2 + 82.92 = 534.58ps

Percentage error :

For Fall case:

[(638 - 624.86) / 638 ] x 100 = 2.10%

For Rise case:

[(610.3 - 534.8) / 610.3 ] x 100 = 12.37%

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Part 2: Power measurement and clock gating

2.1 : Power measurement for a 8bit Multiplier:

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Power Graph:

Total power consumption = 12.5mW

Average power consumption = 361.2uW

Static power graph: Static power consumption = 67.5nW [THIS IS FOR ALL INPUTS = 0] ;

= 150nW [THIS IS FOR ALL INPUTS = 1]

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8 bit multiplier with input and output register files:

Power consumption for all the blocks:

A] Power gating is applied:1. Input register file:

total power consumption = 4mw average power consumption = 92.48uW

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2. Output register file:

total power consumption = 3.5mw average power consumption = 40.42uW

3. Multiplier stage:

total power consumption = 7.4mw average power consumption = 473.3uW

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4. Load inverters:

total power consumption = 4.8mw average power consumption = 9.716uW

5. Total power consumption of the circuit:

total power consumption = 9.8mw average power consumption = 615.9uW

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6. Static power consumption:= 20mW [THIS IS FOR ALL INPUTS = 1] ;

= 55uW [THIS IS FOR ALL INPUTS = 0]

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B]. Power gating is not applied:

1. Input register file:

total power consumption = 3.8mw average power consumption = 149.6uW

2. Output register file:

total power consumption = 3.7mw average power consumption = 112.4uW

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3. Multiplier stage:

total power consumption = 7.6mw average power consumption = 749uW

4. Load inverters:

total power consumption = 4.8mw average power consumption = 30.58uW

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5. Total power consumption of the circuit:

total power consumption = 9.8mw average power consumption = 1.042mW

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Extra credit part:

clock gating logic:

it is a frequency divider logic to get clock for 3 cycles and deactivate it for 3 cycles.