555-timer pdf
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555 TimerIntroduction:
The 555 Timer is one of the most popular and versatileintegrated circuits ever produced!
SigneticsCorporation first introduced this device as the
SE/NE 555 in early 1970.
It is a combination of digital and analog circuits.
It is known as the time machineas it performs a wide
variety of timing tasks.
Applications for the 555 Timer include: Ramp and Square wave generator
Frequency dividers
Voltage-controlled oscillators
Pulse generators and LED flashers 2
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555 timer- Pin Diagram
The 555 timer is an 8-Pin D.I.L. Integrated Circuit or chip
Notch
Pin 1
3
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555 timer- Pin Description
Pin Name Purpose
1 GND Ground, low level (0 V)
2 TRIG OUT rises, and interval starts, when this input falls below 1/3 VCC.
3 OUT This output is driven to approximately 1.7V below +VCCor GND.
4 RESET
A timing interval may be reset by driving this input to GND, but the
timing does not begin again until RESET rises above approximately
0.7 volts. Overrides TRIG which overrides THR.
5 CTRL "Control" access to the internal voltage divider (by default, 2/3 VCC).
6 THR The interval ends when the voltage at THR is greater than at CTRL.
7 DISOpen collectoroutput; may discharge a capacitor between intervals.
In phase with output.
8 V+, VCC Positive supply voltage is usually between 3 and 15 V. 4
http://en.wikipedia.org/wiki/Vcchttp://en.wikipedia.org/wiki/Vcchttp://en.wikipedia.org/wiki/Vcchttp://en.wikipedia.org/wiki/Open_collectorhttp://en.wikipedia.org/wiki/Open_collectorhttp://en.wikipedia.org/wiki/Vcchttp://en.wikipedia.org/wiki/Vcchttp://en.wikipedia.org/wiki/Vcc -
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555 Timer
Description:Contains 25 transistors, 2 diodes and 16 resistors
Maximum operating voltage 16V
Maximum output current 200mA
If you input certain signals they will be processed / controlled in a
certain manner and will produce a known output.
INPUT PROCESS OUTPUT
Best treated as a single component with required
input and output
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Inside the 555 Timer
S R Q Q
0 0 No Change
0 1 0 1
1 0 1 0
1 1 X X
Threshold
Control Voltage
Trigger
Discharge
Vref
+
R
S Q
Q
Truth Table
Fig: Functional Diagram of 555 Timer
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Inside the 555 Timer
Operation: The voltage divider has three equal 5K resistors. It
divides the input voltage (Vcc) into three equal
parts.
The two comparators are op-amps that compare
the voltages at their inputs and saturate depending
upon which is greater.
The Threshold Comparator saturates when the voltageat the Threshold pin (pin 6) is greater than (2/3)Vcc.
The Trigger Comparator saturates when the voltage at
the Trigger pin (pin 2) is less than (1/3)Vcc
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I nside the 555 Timer The flip-flop is a bi-stable device. It generates two
values, a high value equal to Vccand a low valueequal to 0V.
When the Threshold comparator saturates, the flip flop isReset (R) and it outputs a low signal at pin 3.
When the Trigger comparator saturates, the flip flop is Set(S) and it outputs a high signal at pin 3.
The transistor is being used as a switch, it connectspin 7 (discharge) to ground when it is closed.
When Q is low, Q bar is high. This closes the transistorswitch and attaches pin 7 to ground.
When Q is high, Q bar is low. This open the switch andpin 7 is no longer grounded
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Uses of 555 timer
What the 555 timer is used for:
To switch on or off an output after a certain time delay i.e.
Games timer, Childs mobile, Exercise timer.
To continually switch on and off an output i.e.
warning lights, Bicycle indicators.
As a pulse generator i.e.
To provide a series of clock pulses for a counter.
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Schematic Diagram of 555 Timer
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555 Timer operating modes
The 555 has three operating modes:1. Monostable Multivibrator
2.Astable Multivibrator
3. Bistable Multivibratior
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555 Timer as Monostable Multivibrator
Description:
In the standby state, FF holds
transistor Q1ON, thus
clamping the external timing
capacitor C to ground. The
output remains at ground
potential. i.e. Low.
As the trigger passes through VCC/3, the FF is set, i.e. Q bar=0, then
the transistor Q1OFF and the short circuit across the timing
capacitor C is released. As Q bar is low , output goes HIGH. 12
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555 Timer as Monostable Multivibrator
Fig (a): Timer in Monostable Operation with Functional Diagram
Fig (b): Output wave Form of Monostable 13
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Monostable Multivibrator- Description Voltage across it rises exponentially through R towards
Vccwith a time constant RC.
After Time Period T, the capacitor voltage is just greater
than 2Vcc/3 and the upper comparator resets the FF, i.e.
R=1, S=0. This makes Q bar =1, C rapidly to groundpotential.
The voltage across the capacitor as given by,
sec1.1)3
1ln(
)1(3
2
3
2,
)1(
RCTRCT
e RCT
VccVcc
VccvcTt
e RCt
Vccvc
at
Ifve going reset pulse terminal (pin
4) is applied, then transistor Q2-> OFF,
Q1-> ON & the external timing
capacitor C is immediately discharged.
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Behavior of the Monostable
Multivibrator
The monostable multivibrator is constructed by
adding an external capacitor and resistor to a 555
timer.
The circuit generates a single pulse of desiredduration when it receives a trigger signal, hence it
is also called a one-shot.
The time constant of the resistor-capacitorcombination determines the length of the pulse.
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Uses of the Monostable Multivibrator
Used to generate a clean pulse of the correct
height and duration for a digital system
Used to turn circuits or external components on or
off for a specific length of time.
Used to generate delays.
Can be cascaded to create a variety of sequential
timing pulses. These pulses can allow you to timeand sequence a number of related operations.
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Monostable Multivibrator
17
Fxx
x
R
T
C 9.01001.1
100
1.1 10
103
3
Problem:
In the monostable multivibrator of fig, R=100k
and the time delay T=100ms. Calculate the value of C ?
Solution:
T=1.1RC
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Applications in Monostable Mode
1. Missing Pulse Detector.
2. Linear Ramp Generator.
3. Frequency Divider.
4. Pulse Width Modulation.
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1.Missing Pulse Detector
Fig (a) : A missing Pulse Detector Monostable Circuit
Fig (b) : Output of Missing Pulse Detector19
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Missing Pulse Detector- Description
When input trigger is Low, emitter-base diode of Q is
forwarded biased capacitor is clamped to 0.7v(ofdiode), output of timer is HIGH width of T o/p of
timer > trigger pulse width.
T=1.1RC select R & C such that T > trigger pulse. Output will be high during successive coming of
input trigger pulse. If one of the input trigger pulse
missing trigger i/p is HIGH, Q is cut off, timer acts as
normal monostable state.
It can be used for speed control and measurement.
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2.Linear Ramp Generator
at pin 2 > Vcc/3
Capacitor voltage
at pin 6
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Linear Ramp Generator- Description
iQ3
Applying KVL around base-emitter loop of Q3
)(
)1()()(21
1
i
i
I
RRIRIRIRIIRIIRIVVRR
R
C
EECEBEBEBBEBCEEBECC
))()(
21
211
21
211
( RRRRRVVR
RRRRVVRR
E
BECCBECC
E ii
t
C
dt
C
idt
C RRR
RRVVR
RRR
RRVVRv
E
BECC
t
E
BECC
t
c }
)
)({
1}
)
)({
11
21
211
0 21
211
0 ((
TRRCR
RRVVRV
E
BECC
CC
)
)(
3
2
21
211
(
)(
)3
2
211
21(
RRVVR
RRCRV
BECC
ECC
T
When becomes at T,vc VCC3
2
Voltage Capacitor,
Ic
Analysis:
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3.Frequency Divider
Fig: Diagram of Frequency Divider
Description:
A continuously triggered
monostable circuit when triggered by a
square wave generator can be used as a
frequency divider, if the timing interval is
adjusted to be longer than the period of the
triggering square wave input signal.
The monostable multivibrator will
be triggered by the first negative going edge
of the square wave input but the output will
remain HIGH(because of greater timing
interval) for next negative going edge of the
input square wave as shown fig.
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4.Pulse Width Modulation
Fig a: Pulse Width Modulation Fig b: PWM Wave Forms
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Pulse Width Modulation- Description
The charging time of capacitor is entirely depend upon 2Vcc/3.
When capacitor voltage just reaches about 2Vcc/3 output of the timer
is coming from HIGH to Low level.
We can control this charging time of the capacitor by adding
continuously varying signal at the pin-5 of the 555 timer which is
denoted as control voltage point. Now each time the capacitor voltage
is compared control voltage according to the o/p pulse width change.So o/p pulse width is changing according to the signal applied to
control voltage point. So the output is pulse width modulated form.
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Pulse Width Modulation
Practical Representation
Fig: PWM & Wave forms
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Astable Multivibrator
27
1Ground 5FM Input (Tie to gnd via bypass cap)
2Trigger 6Threshold
3Output 7Discharge
4Reset (Set HIGH for normal operation) 8Voltage Supply (+5 to +15 V)
Fig (a): Diagram of Astable Multvibrator
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Astable Multivibrator
28
Fig (b): Functional Diagram of Astable Multivibrator using 555 Timer
A1
A2
V1
V2
VTVC
Vo
VA
R2
R1
R3
A1
A2
Q1
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Astable Multivibrator- Description
29
Connect external timing capacitor between trigger point
(pin 2) and Ground.
Split external timing resistor R into RA& RB, and connect
their junction to discharge terminal (pin 7). Remove trigger input, monostable is converted to Astable
multivibrator.
This circuit has no stable state. The circuits changes its
state alternately. Hence the operation is also called free
running oscillator.
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30
Resistive voltage divider (equal resistors) sets threshold
voltages for comparators
V1= VTH = 2/3 VCC V2= VTL = 1/3 VCC
Two Voltage Comparators
- For A1, if V+> VTH then R =HIGH
- For A2, if V-< VTL then S = HIGH
RS FF
- If S = HIGH, then FF is SET, = LOW, Q1OFF, VOUT= HIGH
- If R = HIGH, then FF is RESET, = HIGH, Q1ON, VOUT = LOW
Transistor Q1is used as a Switch
Astable 555 Timer Block Diagram Contents
Q
Q
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31
Operation of a 555 Astable
VCC
VC(t)
RA RB
1) Assume initially that the capacitor is discharged.a) For A1, V+= VC = 0V and for A2, V-= VC= 0V, so R=LOW,
S=HIGH, = LOW , Q1 OFF, VOUT = VCC
b) Now as the capacitor charges through RA& RB,eventually VC> VTLso R=LOW & S=LOW.
FF does not change state.
Q
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32
Operation of a 555 AstableContinued
VC(t)
RB
Q1
2) Once VCVTHa) R=HIGH, S=LOW, = HIGH ,Q1 ON, VOUT = 0
b) Capacitor is now discharging through RBand Q1toground.
c) Meanwhile at FF, R=LOW & S=LOW since
VC< VTH.
Q
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33
Operation of a 555 AstableContinued..
3) Once VC< VTL
a) R=LOW, S=HIGH, = LOW , Q1 OFF, VOUT = VCC
b) Capacitor is now charging through RA& RBagain.
VCC
VC(t)
RA RB
Q
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Timing Diagram of a 555 Astable
34
VC(t)VTH
VTL
VOUT(t) TL
TH
t = 0 t = 0't
t
1 2 3
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Astable Multivibrator- Analysis
35Contd.
The capacitor voltage for a low pass RC circuit subjected to a step input of Vccvolts is
given by,
The time t1taken by the circuit to change from 0 to 2Vcc/3 is,
)1( eVv RCt
CCc
RCteVV RC
CC
CCt
09.1)1(3
21
1
VV CCC3
2
The time t2to charge from 0 to vcc/3 is VV CCC 3
1
RCteVV RC
CC
CCt
405.0)1(3
2
2
So the time to change from Vcc/3 to 2Vcc/3 is, RCRCRCtttHIGH 69.0405.009.121
So, for the given circuit, C
RRt BAHIGH )(69.0
The output is low while the capacitor discharges from 2Vcc/3 to Vcc/3 and the
voltage across the capacitor is given by,
eVV RCt
CC
CC
3
2
3
Charging time
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Astable Multivibrator- Analysis
36
CRt BLOW 69.0
After solving, we get, t=0.69RC
For the given circuit,
Both RAand RBare in the charge path, but only RBis in the discharge path.
The total time period,
CCT RRRtt BBLOWHIGH A 69.0)69.0 (
CCCCT RRRRRRRR AAA BBBBB )69.0)69.0])69.0 2(([(
CCTf
RRRR AA BB )
45.1
)69.0
11
2(2( Frequency,
Duty Cycle,100
)
)100
)69.0
)69.0100%
2(
(
2(
(XX
C
CX
TD
RR
RRRR
RRt
A
A
A
A
B
B
B
BHIGH
100)
100)69.0
69.0100%
2(2(XX
C
CX
TD
RR
RRR
Rt
AA B
B
B
BLOW
Discharging time
.1.45 is Error Constant
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Behavior of the Astable Multivibrator
The astable multivibrator is simply an oscillator. The
astable multivibrator generates a continuous stream of
rectangular off-on pulses that switch between two
voltage levels.
The frequency of the pulses and their duty cycle are
dependent upon the RC network values.
The capacitor C charges through the series resistors RA
and RB with a time constant (RA+ RB)C.
The capacitor discharges through RBwith a time
constant of RBC
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Uses of the Astable Multivibrator
Flashing LEDs
Pulse Width Modulation
Pulse Position Modulation
Periodic Timers Uses include LEDs, pulse generation, logic
clocks, security alarms and so on.
38
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Applications in Astable Mode
39
1.Square Generator
2.FSK Generator
3.Pulse Position Modulator
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1.Square Generator
40
0
%50100)
)
1
2
2
2((
1
1
R
RR
RR
Here
XDutyCycle
To avoid excessive discharge current through Q1when R1=0
connect a diode across R2, place a variable R in place of R1.
Charging path R1& D; Discharging path R2& pin 7.
10F
C1
3
Fig: Square Wave Generator
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2. FSK Generator
41
Description:
In digital data communication,
binary code is transmitted by
shifting a carrier frequency
between two preset
frequencies. This type of
transmission is called Frequency
Shift Keying (FSK) technique.
Fig: FSK Generator
Contd..
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FSK Generator
42
The frequency of the output wave form given by,
CRRf
O )
45.1
2( 1 2
When input digital is LOW, Q1is ON then R3parallel R1
CRRRf
O )
45.1
2||( 3 1 2
A 555 timer is astable mode can be used to generate FSK signal.
When input digital data is HIGH, T1is OFF & 555 timer works as
normal astable multivibrator.
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2. Pulse Position Modulator
43
Fig (a): Pulse position Modulator
Fig (b): Output Wave Form of PPM
Description:
The pulse position modulator can be
constructed by applying a modulating
signal to pin 5 of a 555 timer connected
for astable operation.
The output pulse position varies with
the modulating signal, since the
threshold voltage and hence the time
delay is varied.
The output waveform that the
frequency is varying leading to pulse
position modulation.
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Astable Multivibrator
44
Problem:
In the astable multivibrator of fig, RA=2.2K, RB=3.9K and C=0.1F. Determine
the positive pulse width tH, negative pulse width tLow, and free-running frequency fo.
Solution:
msXKCRt BLOW 269.0)1.0)(9.3(69.069.0 10 6
?)
45.11
2(
CT RRf
A Bo
msXKKC
RRt BAHIGH
421.0)1.0)(9.32.2(69.0)(69.0
10
6
?1009.322.2
9.32.2100
)
)100%
2(
(
XKXK
KXX
TD
RR
RRt
A
A
B
BHIGH
Duty Cycle,
?1009.322.2
9.3100
)100%
2(
X
KXKXX
TD
RR
Rt
A B
BLOW
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45
One PossibleSolution:
One Possible
Solution:
Example: A 555 oscillator can be combined with a J-K FF to
produce a 50% duty-cycle signal. Modify the above
circuit to achieve a 50% duty-cycle, 40 KHz signal.
Example: Design a 555 Oscillator to produce an approximate
square-wave at 40 KHz. Let C > 470 pF.
F=40KHz; T=25s; t1=t2=12.5sFor a square-wave R
A
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Comparison of Multivibrator Circuits
46
Monostable Multivibrator Astable Multivibrator
1. It has only one stable state 1. There is no stable state.2. Trigger is required for the operation
to change the state.
2. Trigger is not required to change the
state hence called free running.
3. Two comparators R and C are
necessary with IC 555 to obtain the
circuit.
3. Three components RA, RBand C are
necessary with IC 555 to obtain the
circuit.
4. The pulse width is given by T=1.1RC
Seconds
4. The frequency is given by,
5. The frequency of operation is
controlled by frequency of triggerpulses applied.
5. The frequency of operation is
controlled by RA, RB& C.
6. The applications are timer, frequency
divider, pulse width modulation etc
6. The applications are square wave
generator, flasher, voltage controlled
oscillator, FSK Generator etc..
CT RRf
A Bo )
45.11
2(
S h itt T i
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Schmitt Trigger
47
The use of 555 timer as a Schmitt trigger is shown in fig.
Here the two internal comparators are tied together and externally
biased at Vcc/2 through R1 and R2. Since the upper comparator will
trip at 2Vcc/3 and lower comparator at Vcc/3, the bias provided by R1
and R2is centered within these two thresholds.
Fig (b): Output Wave FormFig (a): Circuit Diagram of Schmitt Trigger
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Features of IC 555 TimerThe Features of IC 555 Timer are:
1. The 555 is a monolithic timer device which can be used
to produce accurate and highly stable time delays or oscillation. It
can be used to produce time delays ranging from few
microseconds to several hours.
2. It has two basic operating modes: monostable and
astable.
3. It is available in three packages: 8-pin metal can, 8-pin
mini DIP or a 14-pin. A 14-pin package is IC 556 which consists of
two 555 times.
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Features of IC 555 Timer
4. The NE 555( signetics ) can operate with a supplyvoltage in the range of 4.5v to 18v and output currents of
200mA.
5. It has a very high temperature stability, as it is
designed to operate in the temperature range of -55c to
125oc.
6. Its output is compatible with TTL, CMOS and Op-
Amp circuits.
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PHASE-LOCKED LOOPS
50
PLL
PHASE LOCKED LOOPS Introduction
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PHASE-LOCKED LOOPS- Introduction
51
The phase-locked loop is a negative feedback system in
which the frequency of an internal oscillator (vco) is
matched to the frequency of an external waveform with
some Pre-defined phase difference.
Vd(t)
PHASE
COMPARATOR
(PC)
LOW PASS
FILTER
(LPF)
VCO
AMPLIFIER
(A)
Vi(t)
Vo(t)
Vp(t)
(EXTERNAL R & C DETERMINES
VCO FREQUENCY)
v
fKo
Contd..
PHASE LOCKED LOOPS
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PHASE-LOCKED LOOPS
52Contd..
The phase comparator (phase detector) can be as simple asan exclusive-or gate (digital signals) or is a mixer (non-linear
device - frequency multiplier) for analog signals.
The phase comparator generates an output voltage Vp(t)(relates
to the phase difference between external signal Vi(t)and vcooutput Vo(t)).
If the two frequencies are the same (with a pre-defined phase
difference) then Vp(t) = 0.
If the two frequencies are not equal (with various phase
differences), then Vp(t) = 0and with frequency components
about twice the input frequency.
Phase Comparator:
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PHASE-LOCKED LOOPS
53Contd..
The low pass filterremoves these high frequency components and
Vd(t)is a variable dc voltage which is a function of the phase
difference.
Voltage Controlled Oscillator: The vcohas a free-running frequency, fo, approximately equal to
the input frequency. the vco frequency varies as a function of Vd(t)
The feedback loop tries to adjust the vco frequency so that:
Vi(t) FREQUENCY = Vo(t) FREQUENCY
THE VCO IS SYNCHRONIZED, OR LOCKED TO V i(t)
Low pass filter:
PLL LOCK RANGE
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PLL LOCK RANGE
54
Lock range is defined as the range of frequencies in the vicinity of
the vcosNatural frequency (free-running frequency) for which the
pll can maintain lockwith the input signal. The lock range is also
called the tracking Range.
The lock range is a function of the transfer functions of the pc,
amplifier, and vco.
Hold-in range:
The hold-in range is equal to half the lock range
The lowest frequency that the pll will track is called the lower lock
limit. The highest frequency that the pll will track is called the upper
lock limit Contd..
Lock range:
PLL LOCK RANGE
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PLL LOCK RANGE
55
PLL CAPTURE RANGE
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PLL CAPTURE RANGE
56Contd.
Capture range is defined as the band of frequencies in the vicinity
of fowhere the pll can establish or acquire lock with an input range(also called the acquisition range).
Capture range is a function of the BW of the lpf ( lpf BW capture
range).
Capture range is between 1.1 and 1.7 times the natural frequency
of the vco.
The pull-in range:
The pull-in range is equal to half the capture range
The lowest frequency that the pll can lock onto is called the lower
capture limit
CAPTURE RANGE:
PLL CAPTURE RANGE
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PLL CAPTURE RANGE
The highest frequency that the pll can lock onto is called
the upper capture limit
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58
PLL LOCK/CAPTURE RANGE
LOCK RANGE > CAPTURE RANGE
PLL Basic Components
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PLL-Basic Components
59
Phase detector:
Transfer function: K[V/radians].
Implemented as: four quad
multiplier, XOR gate, state
machine.
Voltage controlled oscillator (VCO):
Frequency is the first derivative ofphase.
Transfer function: KVCO/s
[radians/(Vs)]
Low pass filter:
Removes high frequency components coming from the phase detector.
Determines loop order and loop dynamics.
PLL OPERATION Putting All Together
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PLL OPERATION-Putting All Together
60
e
dd
VK
edd KV dafout VKKV
af
outd
KK
VV
d
de
K
V
v
fKo
o
out
K
fV
out
o
V
fK
ooutKVf
nin fff
oafdL KKKKK
OPEN-LOOP GAIN:
PLL OPERATION
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PLL OPERATION
61
KdKf Ka
Ko
dded KKV2
maxmax
Loafd KKKKKf22
max
HOLD-IN RANGE
LKfRangeLock
max2
PLL 565 Pin Configuration
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PLL 565 Pin Configuration
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PLL Example
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PLL- Example
63
Problem:
fn= 200 kHz, fi= 210 kHz, Kd= 0.2 V/rad, Kf= 1, Ka= 5, Ko= 20 kHz/V
radkHzKL /20)20)(5)(1)(2(.
PLL OPEN-LOOP GAIN:
VCO FREQUENCY CHANGE for LOCK:
kHzfff nin 10200210
PLL OUTPUT VOLTAGE:
VVkHz
kHz
K
fV
o
out 5./20
10
Solution:
Contd..
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PLL-Example
64
STATIC PHASE ERROR:
65.285./2.
1.
radradV
V
K
V
e d
d
HOLD-IN RANGE:
LOCK RANGE:
kHzKf L 4.312
max
kHzfRangeLock 8.622 max
PHASE DETECTOR OUTPUT VOLTAGE:
VKK
VV
af
outd 1.
)5(1
5.
Salient Features of 565 PLL
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Salient Features of 565 PLL1. Operating frequency range =0.01Hz to 500KHz
2. Operating voltage range = 6v to 12v
3. Input level required for tracking:
10mv rms min to 3v peak to peak max
4. Input impedance = 10ktypically.
5. Output sink current : 1mA typically.6. Output source current: 10mA typically
7. Drift in VCO Centre frequency: 300 PPM/ c
8. Drift in VCO Centre frequency with supply voltage: 1.5
percent/Vmax
9. Triangle wave amplitude: 2.4 Vppat 6v supply voltage.
10. Square wave amplitude: 5.4 Vppat 6v supply voltage.
11. Bandwidth adjustment range: < 1 to 60%65
PLL APPLICATIONS
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PLL APPLICATIONS
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Analog and digital modulation
Frequency shift keying (fsk) decoders
Am modulation / demodulation
Fm modulation / demodulation
Frequency synthesis
Frequency generation
PLL APPLICATIONS
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PLL APPLICATIONS
67
1.FM Demodulator:
2.FM Modulator:
Voltage Controlled Oscillator (VCO)
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Voltage Controlled Oscillator (VCO)
68
A voltage controlled oscillator is an oscillator circuit
in which the frequency of oscillations can be
controlled by an externally applied voltage
i
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VCO Operation
69
VCO A l i
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VCO Analysis
70Contd..
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VCO Analysis
71
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Features of VCO
72
li i f
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Applications of VCO
73
The various applications of VCO are:
1. Frequency Modulation.
2. Signal Generation (Triangular or Square Wave)
3. Function Generation.
4. Frequency Shift Keying i.e. FSK demodulator.
5. In frequency multipliers.
6. Tone Generation.
VCO
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VCO
74Contd.
VCO
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VCO
75
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Thank You