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Small Signal Modeling of a Novel Single-Phase

Photovoltaic Inverter

Pan Geng, Weimin Wu, Yinzhong Ye, and Yijian Liu

Department of Electrical Engineering, Shanghai Maritime University, Shanghai, 200135, China

Abstract-The dual mode time-sharing photovoltaic (PV)

inverter is generally of higher efficiency compared to other types

because only one power stage operates in the high switching

frequency state at any time. In this paper, small-signal-model

comparison was made between the conventional dual mode

time-sharing inverter and the proposed dual mode time-sharing

cascaded inverter. It has been revealed with modeling that the

control-to-output voltage transfer function of the conventional

inverter has right half plane zero, and the system is difficult to be

controlled well, additionally, a simple compensator could hardlymeet the requirement on systems phase margin and amplitude

margin when the input voltage is lower than a half peak value of

the output voltage. However, it becomes much easier to design a

desired compensator for the proposed buck-type inverter. The

experiments in a 1kW prototype of proposed inverter verified the

theoretical analysis.

Index Terms: small-signal-model, dual mode, time-sharing,

photovoltaic inverter

I. INTRODUCTION

Photovoltaic (PV) generation system is one of attractive

renewable energy sources. The electrical characteristics of PV

panels vary with their types, manufacturing processes, and

temperature levels[1]

. Many topologies and control methods

have been presented to reach a high performance[1-9]

. Fig.1

shows a good solution of conventional dual mode time-sharing

inverter with a chemical DC-link capacitor forhigh efficiency[6]

. However, the system is difficult to be controlled well. Few

papers investigated how to design a suitable control system for

this type inverter in detail[6~9]

. In this paper, models of the

conventional dual mode time-sharing inverter and the proposed

one (as shown Fig.2)[3]

will be derived. And the experiments in

a 1kW prototype of proposed inverter verified the theoretical

analysis.

Fig.1 Conventional dual mode t ime-sharing inverter

Fig.2 Proposed dual mode time-sharing cascaded inverter

II. MODELING OF THE DUAL MODE TIME-SHARING

INVERTER

A. Systems basic Operating Principle

Fig.3 shows the basic operating principle for the dual mode

time-sharing inverter. When the absolute instantaneous value of

the output AC voltage is lower than that of the input DC voltage

(named as Buck operating stage), the output power stage of

this type inverter (Full-bridge inverter) works in high frequency

state only.

Fig.3. Operating principle for dual mode time-sharing inverterWhen the absolute instantaneous value of the output AC

voltage is higher than that of the input DC voltage (named as

Boost operating stage), the output power stage is in an

economical operating mode because the boost stage of the

conventional inverter operates in sine wave modulation, while

the current-fed circuit of the proposed one chops to shape the

head part of the sine wave.

B.

Modeling for Buck operating stage

During Buck operating stage, the conventional inverter and

the proposed one can be simplified as Fig.4. Both could be

treated as buck converters.

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(a). Of conventional inverter

(b). Of proposed inverter

Fig.4 Equivalent circuits during Buck operating stageThe small signal models of these two inverters could be

derived as follows.

For the proposed topology, during a switching period Ts, the

voltage of inductor L2could be described as:

=

=

)()(

)()()(

22

121

tVtV

tVtVtV

oL

oCL (1)

where VL21 is the voltage of L2when the switch Vt2 is on, and

VL22is the voltage ofL2when the switch Vt2is off.

Using the state-space averaging method, Eq.1 could be

simplified as:

TsoTsCTsL

TsLtVtVtd

dt

tidLtV )()()(

)()( 11

2

22 == (2)

where d1(t) is the duty-cycle of buck chopper converter, and

Ts is the average value in the switching period Ts.

The currents of capacitors C1, C2 and the voltage balance

equation could be described as:

TsLTsinTsC

TsCtitdti

dt

tVdCti )()()(

)()( 21

1

11 == (3)

R

tVti

dt

tVdCti Ts

o

TsLTsC

TsC

)()(

)()( 2

2

22 == (4)

TsCTsintVtV )()( 1= (5)

Unlike DC/DC converters, this circuit does not have a steady

state during the line frequency period, but it could be treated as a

quasi-steady-state in a switching period while analyzing a

steady state working point. The quasi-steady-state equation

could be expressed as:

=

=

=

=

1

1

2

2

Cin

oC

oL

Lin

VV

VDVR

VI

DII

(6)

where these variables are the quasi-steady-state values of the

circuit.Using perturbation approach to the average model of Eq.2~5

with being ignored the high-order terms and being the variables

substituted by Eq.6 will lead to:

=

=

=

+=

)()(

)()(

)(

)()()()(

)()()()(

1

22

1221

1

111

2

2

tVtV

R

tVti

dt

tVdC

tdItiDtidt

tVdC

tVtdVtVDdt

tidL

Cin

o

L

C

LLinC

oCCL

(7)

where R, L1, L2, C1, C2 are load resister, filter inductors and

capacitors of the proposed one respectively, and a variable with

a cap of ^ is the small-signal disturbance variable.

A similar process for the small signal model of conventional

topology will result in:

=

=

=

+=

=

))()(

)()(

)(

)()()()(

)()()()(

)()()(

1

22

2

'

12211

1

1

'

112

2

11

1

titi

R

tVti

dt

tVdC

tdItiDtidt

tVdC

tVtVDtdV

dt

tidL

tVtVdt

tidL

Lin

oL

C

LLLC

oCCL

CinL

(8)

whereR,L1,L2, C1, C2are load resister, filter inductors and

capacitors of the conventional inverter respectively.

Fig.5 shows the small-signal equivalent circuit models during

Buck operating stage.

)(tVin

)(` tVo

)(2` tdIL

)(` 1 tdV C


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)(tVin

)(tVo

)(2 tdIL

)(tdVin


Fig.5 Small-signal equivalent circuit models during the Buck operating stage

The control-to-output voltage transfer functions of these two

inverters can be deduced as Eq.9 and Eq.10 respectively:

( ) RsLDLsRDCLCLCLsCLLsCCLLRVRsLVDsCLVR

sG

inoin

vd

+++++++

+

=

)(

)(

2

2

1

22

212211

3

121

4

2121

1

2

11

1'

(9)

RsLsCRL

RVsG invd

++=

2

2

22

)(1

(10)

It can be seen that the transfer function of conventionalinverter is a fourth-order system with two right half plane zeros,

while the transfer function of the proposed one is much simple.

C.

Modeling for Boost operating stage

During Boost operating stage, the conventional dual mode

time-sharing inverter and the proposed one can be simplified as

that shown in Fig.6. The conventional inverter now works as a

boost chopper, while the proposed one is still a buck chopper.



Fig.6 Equivalent circuit during Boost operating stageBased on the similar processed, the small signal models and

the small signal equivalent circuit models are shown in Equ.11,

Equ.12 and Fig.7, respectively. And the control-to-output

voltage transfer functions are deduced as Equ.13 and Equ.14

respectively.

=

=

=

=

+=

)()(

)()(

)(

)()()()(

)()()(

)()()()(

1

'

'

'

2

22

'

2211

11'

'

1

22

'

211

'11'

'

'

'

'''

'

'

'

''

'

titi

R

tVti

dt

tVdC

titdItiDdt

tVdC

tVtVdt

tidL

tdVtVDtVdt

tidL

Lin

o

L

C

LLL

C

oC

L

CCin

L

(11)

+=

=

=

+=

+=

121

22

2

211

1

1

2

2

121

1

)()()(

)()(

)(

)()()(

)()()()(

)()()()(

LLin

oL

C

LLC

oinC

L

CininL

ItdtDiti

R

tVti

dt

tVdC

tiN

ti

dt

tVdC

tVtVtVdt

tidL

tVNtVDVtddt

tidL

(12)

)(` tV in

)(` tV o

)(1 tdIL

)(` 1 tdV C

1:D


)(tVin

)(1 tdIL

)(tdVin

)(tVo

)(tVin


Fig.7 Small-signal equivalent circuit models during the Boost operating stage

( ) ( ) RDsDLLsRDCLCLCLsCLLsCCLLR

sRD

LDRV

sGO

vd+++++++

=22

21

22

221121

3

121

4

2121

1 )(

)(2'

(13)

( ) ( ) RNsNLLRsNCLCLCLsCLLsCCLRLNRV

G invd 2221

22

221121

3

121

4

21212

+++++++=

(14)

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III.

DESIGN OF THE CONTROL COMPENSATOR FOR THE PROPOSED

INVERTER

Below are the main parameters of the conventional inverter

and the proposed one,

For the conventional inverter: Vin=80V, Vo=110Vrms, the

switching frequency of boost and full-bridge inverter are 45kHz

and 30kHz respectively, L1=400uH, C1=30uF, L2=500uH,

C2=10uF,R=15ohm.For the proposed one: Vin=80V, Vo=110Vrms, the switching

frequency of Vm1, Vth1~4, and Vt1~4 are 108kHz, 54kHz and

30kHz respectively,L1=160uH, C1=30uF,L2=500uH, C2=10uF,

R=15ohm.

Fig.8 Frame of control system

The frame of control system is shown in Fig.8, where Gc(s) is

the transfer function of compensation network, Gm(s) is the

transfer function of PWM modulator and H(s) is transfer

function of feedback network. Therefore, the original open-loop

transfer function is Gm(s)Gvd(s)H(s).

Unlike DC/DC converters, the duty-cycle of steady state for

DC/AC converters is not a fixed value. But it is known that the

output voltage waveform of an inverter distorts easiest when it

reaches its peak value. And the circuit could be regarded as

working at the worst condition under this duty-cycle. If the

circuit could be controlled well under this duty-cycle, the circuit

could work well in the whole line frequency period. So in thispaper, only the worst condition is analyzed either during the

Buck operating stage or the Boost operating stage. The

original open-loop bode plots of both stages are described in

Fig.9 and Fig.10 respectively.



Fig.9 Bode plots of the original open-loop control-to-output voltage transferfunctions during Buck operating stage



Fig.10 Bode plots of the original open-loop control-to-output voltage transfer

functions during Boost operating stage

Owing to the right half plane zeros, the conventional inverter

has a poor characteristic. It is difficult to design a simple

compensator to make the system work well. However, the

proposed topology is a buck type inverter in essence. Without

any right half plane zeros, it is much easier to design a desired

compensator.

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For example, during the Boost operating stage, the

cross-over frequency is designed at 20kHz, and the

compensators zeros are set to compensate the poles of the

original transfer function respectively, and the compensators

poles are designed at 108kHz to eliminate the ripple at the

switching frequency. It is easy to get a desired compensator as

following,

25

23244

)1078.6()105()10(1046.3)(

+++=

sssssGc (15)

The root locus and bode plot of the compensated system is

shown in Fig.11. It can be seen that it is a stable system and has

a phase margin of about 54.2 degrees and an amplitude margin

of about 20.5 dB with enough low frequency gain.

Fig.11 Root locus and bode plot of the Compensated control-to-output voltage

transfer functions during Boost operating stage

IV. EXPERIMENTAL RESULTS

A 1kW 80/110V dc/ac inverter prototype shown in Fig.12 is

accomplished to demonstrate the proposed control strategy.The experimental waveform is shown in Fig.13, where channel

1 is the output voltage and channel 2 is the load current. It can

be seen that the waveforms of output voltage and load current

are very sinusoidal, and these two waveforms have the same

phase.

Fig.12 Experimental prototype

Fig.13 Experimental waveform

V. CONCLUSIONS

This paper shows how to design a desirable compensator

based on the small-signal-model, and shows that the proposed

buck type converter without right half plane zero in its

control-to-output voltage transfer function is easier to be

compensated and has a better stability. The experimentalresults on a 1kW prototype show the feasibility of this inverter.

ACKNOWLEDGMENT

The authors thank the supports from the National Natural

Science Foundation of China (NSFC) (No: 50707017), the

Leading Academic Discipline Project of Shanghai Municipal

Education Commission (No: J50602) and Innovative Project of

Shanghai Municipal Education Commission (No: 09YZ249)

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