40g/100gbps next generation high speed optical/ … · 台灣是德科技股份有限公司...

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40G/100Gbps Next Generation High

speed Optical/ Electrical & GPON

Communication Test Overview

Brian Chi 祁子年

Senior Project Manager

Agilent/ Keysight Technologies

[email protected]

Jan.13 & 14, 2015

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Agenda

2

40G/ 100G/ 400G Market Trends overview

AOC test solution introduction

Real time or Sampling Scope?

400G Solution PAM-4

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Digital/Optical Technology Deployment Eco System

3

CPRI

OBSAI

CPRI

OBSAI

MAN

WAN

CPU o

NB

SB

DVI

DP

HDMI

PCIe

DDR, BoB

PCIe

HD

Audio

USB SATA

PCI

HT

PCIe

SONET

XFP

Module

Desktop Chipset

DMI

QPI

Public Wireline Infrastructure

PON

OLT PON

PON PON

HT

CEI

GbE

CEI

GbE

SATA II

Infiniband

FibreChannel

GbEthernet

HDD

SAN

LAN Server

Storage

GbE

FC

FC

GbE

SFP Module

Enterprise Infrastructure

Ethernet Ethernet

SFI

Infrastructure

Interfaces

XFI

Telco

Switch

Public Wireless

Infrastructure

OBSAI

RF IC

DigRF

MIPI

D-PHY

M-PHY

UniPro

Mobile Device

BB IC

AP

LTE

WiMAX

BSC/

RNC BTS USB

DSI

CSI

DDR

UFS

RH

RH

MHL

SSIC

M-PCIe

DDR

A/V

Decoder/

Processor

BB IC

Tx/Rx

RF IC

DP

HDMI USB

WiHD

Consumer

Longhaul

OTN

DWDM

SATCOM

Radar

AMP

RF

Mix

Mod

Radar

SATCOM

IQ

High-Speed Computing Datacom World

Telecom World

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Market Trends Smartphones, Online video content and Could continue to drive the need for faster

network connections.

Industry is responding with new technology that provides:

• Increased data rates: 10Gb/s25Gb/s/28Gb/s

• Increased port density(Lane):1x4x8x12x24x32x

• Increasing spectral efficiency: Complex Modulation

• Increasing pulse amplitude modulation level: PAM-4

-200G -100G 0G 100G 200G

4

//www.google.com/

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Network Types (highest performance versus lowest cost) Application Units/Year Price/DUT Signal

SAN/LAN Data Center – Rack 100K - 1M $10 - $100 Elec. or 850 nm NRZ

SAN/LAN Data center – Floor 1M - 10M $10 - $100 850 nm MM NRZ

LAN Campus 100K - 1M $100 - $1K 1310 MM or SM NRZ

PON Access – Consumers 100K - 10M $10 1550 SM NRZ WDM

PON Access – Business 10K - 100K $100 - $1K 1550 SM NRZ WDM

MAN Metro 10K - 100K $1K - $10K 1550 SM NRZ/CM

WDM

WAN Long-haul 1K - 100K $10K - $100K 1550 SM NRZ/CM

WDM EDFA

WAN Submarine 100 - 10K $100K - $1M 1550 SM NRZ/CM

WDM EDFA

SAN: Storage Area Network NRZ: Non-Return to Zero modulation

LAN: Local Area Network CM: Complex modulation

PON: Passive Optical Network MM: Multimode fiber

MAN: Metropolitan Area Network SM: Single-mode fiber

WAN: Wide Area Network WDM: Wavelength-division multiplexing

EDFA: Erbium-doped fiber amplifier

5

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Market Info.

6

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Market Information

7

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Market information

8

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Three 100Gb/s Evolution Paths

4 Fibers, 1 wavelength

with 25Gbit/s,

on-off modulation

50 GHz 50 GHz

1 Fiber, 192 wavelength with

100Gbit/s in each ITU-T channel,

advanced modulation

1 Fiber 4 wavelength

with 25Gbit/s,

on-off modulation

4x25Gb/s

Multi-fiber

4x25Gb/s

Multi-λ

4x25Gb/s

Dual-Pol & DQPSK

2013/11/13 Turk Telekom

and Huawei Completed a

2T WDM Field Trial.

The field trial achieved

groundbreaking 40Tb/s C-

band transmission over a

single fiber(10M channels

of HD videos):

307km between Ankara

and Cankiri / 32QAM

modulation/400Gps

9

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So many flavors of 100 Gb Ethernet

10

Real Time Scopes Ethernet Solutions

Agilent Restricted

April, 2012

Test: What is 100GBaseLR4? 10Gbase KR4?

10

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Key architectures for 100 Gb/s Data communications (1 meter to 10 km)

100 Gb/s usually means 25 Gb/s

4 x 25 = 100

Even in expensive telecommunications, higher order modulation is used rather than

switching at a 100 GHz rate

11

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802.3 ae, 802.3 ap, 802.3 aq, 802.3 ba, 802.3 802.3 bg, 802.3 bj, 802.3 bm, 8023 bs…..???

– These are names for a task force that will work to create a new

standard

– When the standard is completed it will be a standalone document

but eventually will become part of the overall 802.3 Ethernet

document (clauses added to 802.3)

• The big document is free:

http://standards.ieee.org/about/get/802/802.3.html

• All clauses through 89 (40/100 GbEn)

• 3694 pages! (Divided into 6 sections)

• About every four years newer standards are rolled into the

main document (it just keeps getting bigger and bigger!)

• Draft documents (prior to official release are available for a fee)

12

http://standards.ieee.org/about/get/802/802.3.html

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Common form factors for the hardware

13

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Common devices that customers will want to test (From component to system level)

14

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M8020A 32 Gbit/s High-Performance BERT

86100D High speed sampling Scope

Dual Q-REX N4391A OMA

Review of OFC 2014

15

http://ofc.hargroveinc.com/Home.aspx

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Agenda

16




400G Solution PAM-4

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Active Optical Cables Used to extend the transmission of signals for MANY applications!

• Ethernet

• Fibre Channel

• InfiniBand

• SAS

• USB3.0

• PCIe

• HDMI

• DVI

• etc.

Electrical I/O <-> Optical for low loss transmission <-> Electrical I/O

Electrical I/O

Optical

17

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Active Optical Cables - InfiniBand

1. Return Loss, S11 (TDR or VNA)

2. Active Time Domain (ATD) testing (waveform/jitter) using 28G BERT

(with aggressors) and 28G Scope.

Next Steps: At Oct 2014 IBTA plugfest at UNH-IOL facilities, Agilent plans to:

Develop MOI using N1055A TDR for S11 on 28G AOC

Finalize MOI using Anritsu+86100D DCA-X for 28G AOC ATD

S11 BERT with aggressors

Scope S11

Active Time

Domain (ATD)

S-parameters (S11) /

Impedance (TDR)

18

http://2.bp.blogspot.com/-u638VFxngRs/UUsapIuMcfI/AAAAAAAAAAs/VkiY9NP5vbI/s1600/AOCs.jpg

http://2.bp.blogspot.com/-u638VFxngRs/UUsapIuMcfI/AAAAAAAAAAs/VkiY9NP5vbI/s1600/AOCs.jpg

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Time Domain Reflectometry (TDR)

Incident wave

Reflected wave

DUT - PCB

- Connector

- Cable

- Interconnect

Step

Generator

Sampler

TDR (impedance Profile)

S11 (Return Loss) TDR Module

Time Domain Reflectometry (TDR)

Incident wave

Reflected wave

DUT - PCB

- Connector

- Cable

- Interconnect

Step

Generator

Sampler

TDR (impedance Profile) TDR Module

Time Domain Transmission (TDT)

Incident wave

Reflected wave

DUT - PCB

- Connector

- Cable

- Interconnect

Step

Generato

r

Sampler

TDR

S11 TDR Module

Transmitted

wave

Step

Generator

Sampler

TDR or RX only

Module TDT (Step Response)

TDR (Impedance Profile)

1

2

3 4

5 6

1. Reference Plane 2. Connector Launch 3. Uncoupled TX Line 4. Coupled Diff TX Line 5. Connector 6. Open Circuit

Quick Review: TDR/ TDT and S-parameters

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Configuring the 86100D TDR/TDT Solution

– 4 Port Devices (most common) (TDR, TDT, S-parameter measurements)

Multi-Port Devices (TDR, TDT, S-parameter measurements)

Qty 1 86100D DCA-X Mainframe

Qty 1 86100D-202 S-Parameter SW

Qty 1 *N1055A-54F 50 GHz, 4-port, Fem

Qty 1 N4694A-HMM ECal DC-67 GHz

Qty 1 86100D-ETR Enhanced Trigger *Determine channel count, bandwidth, m or f

connectors

Qty 1 86100D DCA-X Mainframe

Qty 1 86100D-ETR Enhanced Trigger

Qty 1 86100D-202 S-Parameter SW

Qty 4 N1055A-54F 50 GHz, 4-port, Fem

Qty 1 N4694A-HMM ECal DC-67 GHz

Keysight 86100D + N1055A 50GHz TDR module

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Typical AOC R&D and PL testing solution

Tx1

Tx2

Tx3 Tx4

Rx1’

Rx2’

Rx3’ Rx4’

Tx1’

Tx2’

Tx3’ Tx4’

Rx1

Rx2

Rx3 Rx4

MCB MCB

N4960A CJ1 (Jitter Injection)

N4951B D32 (De-emphasis.) *2

D32

H32

86100D+ 86107A

N1045A-04F Qty=2

25Gbps

4-Lanes

E32

E32

E32

E32

2.4 to 2.92mm 30cm Cables

Qty=20

2.92mm 30cm Cables Qty=14

2.4 to 2.4mm 30cm Cables

Qty=4

11667C 50GHz Splitter Qty=4 N4960A CJ1 (Jitter Injection)

N4952A E32 (32G Error Detector)

D32

D32

N4960A CJ1

N4952A E32

(Error Detector)

H32 1:4 Power Divider I.L. 15dB

(Typical) + 3dB( Connector) ~ 18dB in

Power

9dB in Voltage, 6V 0.75V (>0.7V

Diff).

21

http://cp.home.agilent.com/agilent7/s7viewers/flash/genericzoom.swf?logo2=false&serverUrl=/agilent7/is/image/&contentRoot=/agilent7/skins/&locale=en&config=Agilent/AGILENT-IMGSET&image=Agilent/PROD-1000000345.epsg.pro-IS



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N4960A 17Gb/s and 32Gb/s BERT Platform The N4960A controller can support two remote heads:

• Remote heads allow placing high-speed signal connectors close to the DUT

• This allows using short interconnect cables – minimizing signal degradation

• Modular is flexible: build a 17G BERT now and upgrade to 32G later; use two

pattern generators and no error detector; add de-emphasis or high-voltage heads

as needed

• Controller has key clocking advantage: clock heads synchronously or

asynchronously; use the N4877A 32Gb/s CDR to clock the error detector

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- Pattern generator with integrated 4-tap de-emphasis (pre, post1, post2)

- Control software imports S-parameter data for automatic cursor determination

- Ideal for lossy high-speed environments: backplane testing, embedded IC testing (chip in board, CoB, etc)

N4951B-D17 and N4951B-D32 De-Emphasis “DE” Remote PG Head

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De-Emphasis – Cursor Definition Cursors are names for neighbouring bits relative to the current transmitted bit

• Pre-cursor is the bit before the current bit, post-cursor1 is the bit after the

current bit, post-cursor2 is the bit after the post-cursor1 bit

• All same-value bits following the last post-cursor have the same amplitude

• The amplitude of certain cursors is determined by the settings, relative to the

cursor value which is determined by the output amplitude setting

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De-Emphasis – Tap Weight Calculator

The SW takes an

S-parameter

measurement file

and matches the

DE transfer

function to the

inverted frequency-

dependent loss

This is how we find

the best cursor

values for any

backplane, without

over-attenuating

the signal

25

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De-Emphasis – Demo Setup shown was

demonstrated at

DesignCon 2013:

8” lossy FR4 ISI board

with SMA connectors

Top image is 1.6Vpp-d

PRBS7 eye at 28Gb/s

with no de-emphasis

(all pre- and post-

cursors set to 0dB)

Bottom image is same

output with cursors:

• Pre1: 5dB

• Post1: -7dB

• Post2: -2dB

26

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N4980A Multi-instrument BERT Software – Bathtub and JTol

Built in measurements:

Single-channel and multi-channel BER

Bathtub visualization

Jitter Tolerance, includes user-defined

template

27

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40G/ 100G RX Stress Eye testing (BERT Application)

Stress Eye VECP

0.01

0.1

1

10

0.01 0.1 1 10 100

Norm UI

2X Jitter UI

ISI BOX

Pattern (Stress Eye)

DCA (Calibration)

Receiver (BER Count)

DUT as example

28

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Agenda

29




400G Solution PAM-4

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Two Tx Characterization Solutions:

30

Sampling and Real-time Oscilloscopes - which to choose?

Real Time

Oscilloscope

Equivalent-time

Sampling Oscilloscope

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Equivalent-Time Sampling Extremely wide bandwidths at low sample rates

A sample is taken, the data pattern

repeats and the next sample is taken

at a slight delay compared to the

previous sample

In practice, samples are very close together

(can be less than 100 fs apart). Through

multiple passes of the signal, the waveform

can be precisely reconstructed

31

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Sampling Scope Bandwidth is Independent of Sample Rate

Measurement bandwidth is

affected by how narrow the

sampler control pulse is (can

be just a few picoseconds)

Since only one sample is

taken, the A-D process can

be very high resolution (up to

16 bits) with very low noise

S Sampler input

Sampler control pulse

Sampler pulse: Low bandwidth High bandwidth

32

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Eye diagrams: Highly synchronous sampling at arbitrary bit locations

PRBS

Reconstructed

Waveform

Trigger Point Sampling

Point

Clock

Trigger

Re-Arm Time

One Bit

33

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Real-time Sampling

Trigger

EventT=1/F

S

T

T

34

Sample entire waveform in one acquisition

Nyquist criterion obeyed: Fs > 2*BW of signal

Interpolation is used to precisely fill in points in between

actual sampled points to yield better resolution

S(t)

Could

Trigger Here….

Or Here

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Effects of 4th Order Bessel-Thomson low pass filter - Combined Gaussian and Flat Response

35

ΔBW

Frequency

Att

en

uati

on

3dB

33 GHz 63 GHz

Gaussian Response

Maximally-Flat Response

Scope swept response measurement

There is a compromise between the flat response with higher bandwidth and the

Gaussian response that has less bandwidth but a smoother roll off.

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Different Responses – affect on rise time and voltage

36

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Compliant Frequency Response (Reference Receiver)

Receiver Frequency Response:

37

4th Order Bessel-Thomson Response

Step Response (red)

Typical RT

Response

Typical SS

Response Scopes have different frequency responses

Will result in different eye/waveform

shapes and amplitudes

–> different measurement results!

Examples:

• IEEE P802.3bj™/D3.2, 11th April 2014

Section 92.8 100GBASE-CR4 Electrical Characteristics: “A test system with a fourth-order Bessel-Thomson low-pass response

with 33 GHz 3 dB bandwidth is to be used for all transmitter signal

measurements, unless otherwise specified.”

To provide more consistency, several standards now specify BW and shape.

• Implementation Agreement OIF-CEI-03.1

13.3.10 Transition Time “The waveform is observed through a fourth-order Bessel-Thomson

response with a bandwidth of 40 GHz.”

Flat Group Delay

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Which is the right scope for your application?

38

Compare Real-Time (RT) vs Equivalent-Time (Sampling) Oscilloscopes

Real-Time Scopes

• Best for troubleshooting scenarios

Captures one-time events

No explicit trigger needed,

advanced trigger features

• Fastest sample rate (160 G Sa/s),

large record length (deep single-shot

memory)

• Does not require repetitive signals

to generate pattern waveforms

• Highest Compliance App coverage

Sampling Scopes

• Highest Overall Signal Fidelity

Wider bandwidth (> 90 GHz)

Lowest timebase jitter (RJ < 45 fs rms)

Lower noise floor (< 0.25 mV)

Higher A/D resolution (16 bits)

• Lower sample rate (kSa/s), but deep sub-

sampled memory (up to 2^23 bits long, 4096 samples/bit)

• Modular platform (Electrical, Optical, TDR)

• Roughly half the price for same BW

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Which is the right scope for your application?

40

Compare Real-Time (RT) vs Equivalent-Time (Sampling) Oscilloscopes

Total Data

Rate, Gb/s

Lane Data

Rate, Gb/s

Lanes IEEE, SFF or OIF CEI Standards 86100D DCA-X

Applications

Real-Time Scope

Applications

Various 6, 11, 25

and 28

1 OIF CEI 3.1 with VSR & MR N1012A Contact

Keysight

100 25.78 4 100GBASE-KR4

100GBASE-CR4

N1084A N8829A

N8830A

10

40

10.3125 1

4

SFP+

QSFP+

N1014A N6468A

10

40

10.3125 1 10GBASE-KR

40GBASE-KR4

N1081A N8814A

40 10.3125 4 QSFP+ N1014A N6468A

40 10.3125 4 XLAUI / CAUI

XLPPI / CPPI

N1083A N6468A

(XLPPI)

40

100

10.3125 4

10

40GBASE-CR4

100GBASE-CR10

N1082A N8828A

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86100D DCA-X ：100G - Electrical

• 86100D DCA-X Mainframe

• 86108B Dual 50 GHz plug-in module

• Channels: 2

• Bandwidth: > 50 GHz

• Timebase Random Jitter: <50 fs rms typ

• Integrated Clock Recovery: 50 Mbps – 32 Gbps

• Built-in Jitter Spectrum Analysis (Option JSA)

Highest Accuracy

• Channels: 2 to 16 per mainframe

• Bandwidth: > 60 GHz

• Timebase Random Jitter: < 150 fs typ with 86107A

• Clock Recovery: External (N4877A 32G CDR)

Highest Density • 86100D DCA-X Mainframe

• N1045A 60 GHz 2/4 Channel Remote Head

Highest accuracy

Easiest setup (no extra cabling/splitters required)

Highest margin for your designs

Most economical scope for 25/28 Gbps designs

Highest electrical channel count solution

Best throughput (simultaneous acquisition)

Remote heads minimize signal degradation

due to cables/fixtures

www.agilent.com/find/86108B www.agilent.com/find/N1045A

50 Mbps – 32 Gbps

(continuous coverage)

Application: IC Chip(Gearbox/Serdes), Backplane, Electrical Interface of EQ

41

http://www.agilent.com/find/86108B



http://www.agilent.com/find/N1045A



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Reduced timebase jitter (86107A/ 86100D-PTB)

42

42

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Internal Precision Time Base (86100D-PTB) 86100D-PTB: Internal PTB supporting 2.4 to 44 GHz clocks

(continuous)

Trigger Input

(to 32 GHz) Internal PTB

(to 44 GHz)

• Reduces intrinsic timebase jitter to < 100 fs on all 16 channels.

• Does NOT occupy a module slot.

< 100 fs rms jitter

Ultra-Low Jitter WITH:

• 16 electrical channels

Or

• 8 elec + 2 optical

Or

• 4 optical

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The DCA is the industry standard for optical test and we continue to lead as 4x25 Systems are developed: 100 Gb is an ideal scenario for the 86100D DCA Only the 86100D can observe 4 optical channels

simultaneously

Configurations for 25/28 Gb/s optical

applications • 86100D DCA-X Mainframe

• 86116C-025 25/28 Gb/s Single-mode (1 Channel)

• 86105D-281 25/28 Gb/s Multimode (1 Channel)

• 86115D-284 25/28 Gb/s Multimode (4 Channels)

• 86107A Precision Timebase (for ultra-low jitter

performance upgrade from exist 86100D)

Highest optical channel count

Eye/Mask, Waveform, Jitter analysis

“Ideal” frequency response capability

Industry standard for optical transceiver

design and MFG test

44

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Lower Cost Optical Transceiver Manufacturing

Run

measurements

on fixture A

Swap

transceivers on

fixture B ALTERNATE

Agilent’s DCA – the

industry standard for

over 15 years

Best Flexibility Lowest Cost of Test

• 86100C/D with 86105C

• 1 optical & 1 electrical port

• 155 Mb/s to 11.3 Gb/s

• 86100C/D with 86115D

• 2 to 8 optical ports

• 8.5 Gb/s to 14 GB/s

High Volume Manufacturing:

8 optical ports/mainframe

45

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Save Time When Using Multiple Channels

Eyes

Aligned

46

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Measurements on multi-lane systems are easy Only the 86100D can perform eye-mask tests on up to

16 channels in parallel (plus 64 eye measurements)

47

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Compliance Applications for the 86100D DCA-X

Test Selection

Report Generation

Results

Method-of-Implementation (MOI)

- available from IBTA website

48

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Agenda

49




400G Solution PAM-4

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Enabling the next step in link data rate

– 56 Gb/s lane data rate will be the principle enabler for 400GbE

– Two contenders for implementing 56Gb/s lane data rate:

• 56G NRZ

- + No new science – linear evolution from 25/28G lanes

- - Difficult to manage channel loss & channel reflections

• 28 Gbaud PAM-4

- + Channel loss problems worked out with 28 Gb/s NRZ

- - 30% chip real estate, 35+% more power

- - Lose 9.6 dB usable SNR

- - Lots of new challenges – little experience to draw from

• Both signaling technologies will be utilized to enable 400GbE

50

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NRZ (Non-Return-to-Zero) vs. PAM (Pulse Amplitude Modulation)

NRZ (PAM-2) PAM-4

51

• 2 amplitude levels

• 1 bit of information in every symbol

• 4 amplitude levels

• 2 bits of information in every symbol

(2x throughput for the same Baud rate)

• Lower SNR, more susceptible to noise

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Status of the Standards using PAM-4 – Very early in Standards development

• 802.3bj clause 94 (25.78 Gb/s as 13.6 Gbaud PAM-4 in 1m

backplane)

- Low adoption rate – no advantage over clause 93 – 25.78 G

NRZ

• OIF CEI-56G-VSR draft v2

- Very complete early draft

- Basis for other standards – Ethernet, Fiber Channel,

Infiniband, ...

– Under consideration:

• 64GFC

• Other OIF standards: CEI-56G-MR, CEI-56G-LR

• 400Gb Ethernet

52

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PAM Test Patterns

PAM-4 transmitters must be capable of generating:

• JP03A Test Pattern - Repeating {0,3} sequence

• JP03B Test Pattern - {0,3} repeated 15 times, {3,0} repeated 16 times

03030303030303030303030303030330303030303030303030303030303030

• Transmitter Linearity Test Pattern

- The transmitter linearity test pattern is a

repeating 160-symbol pattern with a sequence of

10 symbol values each 16 UI in duration.

{–1,–1/3,+1/3,+1,–1,+1,–1,+1,+1/3,–1/3}

- 10 consecutive symbols mitigates the impact

of ISI on “Level” measurements (VA, VB, VC, VD)

53

Reference: IEEE Std 802.3bj-2014, Amendment to IEEE Std 802.3™-2012 as amended by

IEEE Std 802.3bk™-2013

Will these be leveraged into future IEEE/OIF

PAM4 Standards?

• Quaternary PRBS13 Test Pattern (QPRBS13)

- The QPRBS13 test pattern is a repeating 15548-symbol (338 training frame words) sequence

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JP03B Test Pattern

– JP03B is a 62 bit clock pattern with phase reversal

- {0,3} repeated 15 times, {3,0} repeated 16 times

03030303030303030303030303030330303030303030303030303030303030

– JP03B is an ideal pattern to measure:

• Random Jitter (RJ)

• Periodic Jitter (PJ)

• Even-Odd (F/2) Jitter

54

What can get measured?

Page


Implementing PAM-4 links = “New Science”

55

– Inherent ISI requires receivers to be less susceptible to pattern dependent jitter

decision threshold

Amount of switching jitter

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Other impairments that challenge PAM-4 receivers

• Non-linearity - Amplitude compression in lower eyes

- Non uniform effective SNR across individual eyes

– Receivers sensitive to additional artifacts beyond “traditional” jitter types in NRZ

• Still learning what impairments cause problems

- New measurements WILL be defined for Tx Outputs

- New stress types WILL be defined for Rx Input testing

56

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Page

40G/ 100G/ 400G Solution

86100D DCA-X with 86108B Precision

Waveform Analyzer Module

M8020A J-BERT II with

M8061A Multiplexer/De-emphasis 63GHz DSOZ634A Infiniium

High-Performance

Oscilloscope

M8195A 65 GSa/s Arbitrary Waveform

Generator

57

Page


Keysight M8000 BER Series of BER Test Solution

58

Fast, accurate receiver characterization

16 Gb/s J-BERT M8020A, 4 channel

M8195A > 32 Gbaud multi-level generator,

4 channel*

16 Gb/s J-BERT M8020A, 1 – 2 channel

32 Gb/s J-BERT M8020A, 1 channel

M8070A Software

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J-BERT M8020A High Performance BERT

Accurate PAM-4 receiver

characterization:

– Adjustable amplitude/offset

– Calibrated jitter built-in

– De-emphasis 8 taps ± built-in

– Interference with built-in

superposition

– Up to 32 Gbaud and 16 Gbaud

– Memory and PRBS (up to 231-1)

– Add-on to 32G and 16G J-BERT

M8020A

PAM-4 signal at 25.78 Gbaud, PRBS 27-1

measured with DCA-X (N1055A-54F)

59

Page


Highest

bandwidth

requirements

better fit for

M8195A

AWG Applications

AWG

… you name it …

A/D (Radar,

EW)

Wideband RF &

Satellite

DPD; amplifier

test

5G, new modulation

formats

HDMI / CPHY

Physics, THz

research

Coherent Optical

High-speed

digital (incl. PAM4)

Highest

dynamic range

requirements

better fit for

M8190A

60

M8195A

8 bit 65 GSa/s

20 GHz analog bandwidth

M8190A

14 bit 8 GSa/s / 12 bit 12 Gsa/s

5 GHz analog bandwidth

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M8195A in Digital Applications

– Flexible stimulus for any modulation format:

• NRZ, PAMx, DMT, …

– Adding impairments without external hardware

• Transition times, ISI, Jitter, DCD, noise, …

– Clean & distorted signals up to 32 Gbaud

– S-Parameter embedding / de-embedding

M8195A 65 GSa/s

AWG 61

Cost-effective multi-level, multi-channel

capabilities Variable transition times

Variable jitter

Variable ISI

Combination of impairments In

dustr

y leadin

g s

ourc

e f

or

PA

M-4

Page


Fast new stress creation

Step 1: Study the current

pattern eye for anomalies

62

Using DCA-X, Flex DCA, M8195A – 4 Easy Steps!

Step 2: Using FlexDCA – create a new stress

to amplify the anomaly

– or create an entirely different one

(DC wander in signal)

Page


Fast new stress creation

Step 3: Download the

simulated stressed pattern into

the M8195A

63

Using DCA-X, Flex DCA, M8195A – 4 Easy Steps!

Step 4: New stressed pattern is available for

testing your new design!

N1010A

FlexDCA

Page


Jitter testing/ PAM4 Setup Keysight N4960A

Keysight 86100D

64

Page


Summary

66

1. 100G Solution is booming by high speed communication

business requirement

2. Agilent/ Keysight provides total solutions: BERT/ TDR/

DCA (Electrical/ Optical)

3. BERT: Combined with N4960A provides production line

test solution for AOC testing.

4. TDR: New 50GHz TDR up to 16 channels in one 86100D

mainframe with Time/ S-para measure capability.

5. SS and RT Scope: Keysight provides 40G/100G UDA tools

running under both platforms.

6. PAM-4: Keysight is ready for next generation 400G

solutions with AWG/ JBERT/ DCA/ Q-Rex.

PCI Express Physical Layer Test Challenges at 16GBit/s

Rick Eads

Jan.13 & 14, 2015

Portions Copyright PCI-SIG

Page PCI Express and the PCI-SIG

Understanding

Oscilloscopes 2

Page

Protocol Spec

3

PCI-SIG PCI Express Standards Organization

PCI Express Board of Directors Keysight, Intel, AMD, IBM, Synopsys, Qualcomm, Dell, HP, nVidia

PCI-SIG Executive Director: Reen Presnel, VTM

Electrical Work

Group:

Intel, AMD

Protocol Work

Group:

Intel

Card

Electromechanical

Work Group

Cable work

group

Legal: Tim Haslach

PCI Express 4.0

Serial Enabling

Work Group

Electrical Spec

C.E.M Spec

Cable Spec

Test Specification

Page

PCI Express® – Keysight Total Solution Physical layer –

interconnect design

ADS design software

86100D DCA-J/TDR

E5071C ENA option TDR

Physical layer-

transmitter test

90000 X-Series oscilloscope

N5393D PCI Express

electrical compliance

software

86100CU-400 PLL and Jitter

Spectrum Measurement SW

Physical layer-

receiver test

M8020A J-BERT High

Perfformance BERT

N5990A automated

compliance and device

characterization test software

Data link/transaction

layer

Digital Test Console

• U4301A Protocol Analyzer

• U4305A Exerciser

•Protocol Test Card

• Multiple probes with ESP

technology

Industry’s lowest scope noise

floor/sensitivity and trigger jitter

X1 through x16 Analysis and Exerciser

support, with industry’s only ESP probing

technology

DSA-X Series & V Series

Real-Time Oscilloscopes

Automated compliance software

– accurate, efficient and consistent

4

PCI Express Technology Extensions

mPCIe (PCI

Express over

MIPI M-Phy)

M.2 (NGFF)

SFF-8639

PCI Express

SATA Express

Extensions

PCI Express 4.0 Timeline (estimated)

Q1 Q2 Q3 Q4

2015

Q1 Q2 Q3 Q4

2016

Q1 Q2 Q3 Q4

2013

Q1 Q2 Q3 Q4

2014

Rev 0.3 Rev 0.5 Rev 0.7 Rev 0.9

Test Chip Data

PCI Express Data Rates

2.5Gbps

5Gbps

8Gbps

16 Gbps

PCIe Electrical Features Gen1, Gen2, Gen3, Gen4

– Data rates 2.5GT/s, 5GT/s, 8GT/s, 16GT/s

– 10-12 bit error ratio

– AC coupled

– Link widths 1, 2, 4, 8, 16, 32 lanes

– Hot swap capable

– 2.5 and 5GT/s scrambled + 8b10b

– 128/130 scrambled encoding (8GT/s and 16GT/s)

– Power management

GT/s Enablers – Receiver equalization required

– Introduce statistical channel analysis

• Channel compliance & simulation with behavioral Tx/Rx

– Mitigate baseline wander & crosstalk

• Polynomial choice of 128/130 code on individual lanes

• Baseline wander:

• LFSR offsets between adjacent lanes reduces simultaneous switching

time

lan

e

Red: vict+2aggr; pink: vict+1aggr; black: vict only

9

PCI Express 4.0

Root Complex End Point

DifferentialFrequency:100MHz

SSC: (30-33kHz, +0 / -0.5%)

REFCLK

Tx + Tx -

Tx + Tx -

Rx + Rx -

Rx + Rx -

CEM

Spec

Base

Spec Base

Spec x N

x N

12” FR-4

1 Connector (w/o retimer)

Common Clocked Architecture

Supported Data Rates 2.5Gbps, 5Gbps, 8Gbps, 16Gbps

PCI Express 4.0 Overview

Key attributes of PCIe 4.0

16 GT/s, uses 128/130 bit scrambling, same as the PCIe 3.0 standard

Maintains backward compatibility with installed base of PCIe devices

Limited channel reach: approx. 12” one connector

Longer channels require retimers or lower loss channels

New features

Uniform spec methodology applied across all data rates (as much as possible)

Support for independent Refclk clocking mode with SSC (SRIS)

Integration of Retimer ECN into 4.0 BASE

This web seminar will include information based upon 0.3 spec changes vs. the 3.0 spec and on items under discussion for potential changes in the 0.5 specification

Reference Clock

Transmitter

Retimer

Receiver

Page

Separate Reference Clocks with Independent SSC (SRIS)

12

Page

Inexpensive Cabling = Independent Clock + Spread Spectrum

Challenge: PCIe spec did not support independent clock with spread spectrum

SATA cable does not include clock and is ~ $0.50

PCIe cables include reference clock, would increase cost > $1 for equivalent cable

PCIe Base Spec 3.0 ECN approved

1) Requires use of larger elasticity buffer

2) Requires more frequent insertion of SKIP ordered set

3) Requires receiver changes (CDR). Does not change transmitter or reference clock requirements.

4) Second ECN updates Model CDRs

Change will create a number of new form factor opportunities for PCIe

SATA Express: Connector for PCIe SSD compatible with SATA

Lower cost external cabled PCIe

Example of

Possible

PCIe x2 Cable

13

Page

Model CDR Must Reject SSC

20 dB/dec

Insufficient SSC Rejection

14

Page

First pass on a CDR model

Kept 40 dB/Dec,

model CDRs for

2.5/5 GT/s

consistency

Impact on

Existing CDRs?

ωn = ω3dB = 2π * 2.09 MHz for 8 GT/sωn = ω3dB = 2π * 2.43 MHz for 16 GT/sζ = 0.707

8 GT/s

16 GT/s

15

GT/s Jitter Tolerance vs CDR Model

Frequency (Hz)

Gain

Allows greater number

of current CDRs to be

Gen4 Compliant

16

Page

Transmitter Design at 16GT/s

17

Page

Transmitter Specification Preset definition

Retain P0-P10 with same definition as PCIe 3.0 at 8GT/s

Package loss (ps21TX)

Informative for root complex devices, normative for AIC devices

Architecture Specific Post Processing

Embedded vs. non-embedded, Common vs. Independent Refclk architectures

Jitter parameters

Applied uniformly for all 4 data rates

Number of normative parameters reduced

Informative params added

Return Loss extended up to 8GHz

Same limits as at 4.0 GHz

T-coils likely required to meet limits

18

Page

Tx/Rx Return Loss Parameters

Freq (GHz)

50

MH

z

1.2

5 G

Hz

2.5

GH

z

4.0

GH

z

8.0

GH

z

A B C D

A: 2.5, 5.0, 8.0 and 16 GT/s

B: 5.0, 8.0 and 16 GT/s

C: 8.0 and 16.0 GT/s

D: 16 GT/s only

Differential Return Loss Mask

Freq (GHz)

50

MH

z

1.2

5 G

Hz

2.5

GH

z

4.0

GH

z

8.0

GH

z

A B C D

A: 2.5, 5.0, 8.0 and 16 GT/s

B: 5.0, 8.0 and 16 GT/s

C: 8.0 and 16.0 GT/s

D: 16 GT/s only

Common Mode Return Loss Mask

Retu

rn L

oss (

dB

)

Retu

rn L

oss (

dB

)

Effective die pad capacitance is ~400 pf (both TX and RX pads)

19

Page

Transmitter Test at 16 GT/s

Understanding

Oscilloscopes

Implications for testing

PCIe @ 2.5GT/s

-3.5dB

PCIe @ 5GT/s

-3.5dB

-6 dB

PCIe @ 8GT/s

De-emphasis Presets P0-P10 (11)

De-emphasis, preshoot, boost for each preset

Signal Quality for at least 1 preset must pass

PCIe @ 16 GT/s

De-emphasis Presets P0-P10 (11)

De-emphasis, preshoot, boost for each preset

Signal Quality for at least 1 preset must pass

X16 lanes (592 test cases possible)

20

Page

The Receiver

21

Page

Tx/Rx Link Equalization Testing for PCIe 3.0

PCIe 3/4 Test

Challenges 22

According to PCI Express Electrical PHY Test Specification

Test Number Test Name

2.3 Add-in Card Transmitter Initial Tx EQ Test for

8.0GT/s

2.4 Add-in Card Transmitter Link Equalization Response

Test for 8GT/s

2.7 System Board Transmitter Link Equalization

Response Test for 8GT/s

2.10 Add-in Card Receiver Link Equalization Test for

8GT/s

2.11 System Board Receiver Link Equalization Test for

8GT/s

Page


PCIe 3/4 Test

Challenges 23

Tests 2.3, 2.4, and 2.7 focus on the transmitter

3-Tap

De-Emphasis Equalization CDR

Receiver Transmitter

Means for

measuring

signal quality

Algorithm for

determining

equalization

and de-

emphasis

De-

Emphasis

Controller

Request de-emphasis setting

Con

trol

Con

trol

Page


PCIe 3/4 Test

Challenges 24

Tests 2.3, 2.4, and 2.7 focus on the transmitter

3-Tap



Means for

measuring

signal quality

Algorithm for

determining

equalization

and de-

emphasis

De-

Emphasis

Controller


Con

trol

Con

trol

The PCIe 3.0 Receiver Link Equalization

Tests specified in 2.3 and 2.4 and 2.7

provide insight to TxEQ issues and corner

case situations

• Requires the DUT to negotiate using

both Presets and Cursors values

• Determines if DUT responds to

Preset/Cursor requests in the

specified amount of time

• Troubleshoot the issues between

protocol communication vs PHY layer

performance

Page


PCIe 3/4 Test

Challenges 25

Tests 2.10 and 2.11 focus on the receiver

3-Tap



Means for

measuring

signal quality

Algorithm for

determining

equalization

and de-

emphasis

De-

Emphasis

Controller


Con

trol

Con

trol

Page


PCIe 3/4 Test

Challenges 26

Tests 2.10 and 2.11 focus on the receiver

3-Tap



Means for

measuring

signal quality

Algorithm for

determining

equalization

and de-

emphasis

De-

Emphasis

Controller


Con

trol

Con

trol

The PCIe 3.0 Receiver Link Equalization Tests

specified in 2.10 and 2.11 are the most

important test of a DUT, they:

• Determine the DUT’s ability to request

appropriate amounts of transmitter

equalization

• Determine the DUT’s ability to

internally apply the appropriate amount

of receiver equalization

• Determine the quality of the DUT’s

algorithm for optimizing the link quality

• Determine the DUT’s ability to optimize

TxEQ and RxEQ in a short period of

time

Page

Introducing the Protocol Aware M8020A J-BERT

– 16 / 32Gb/s BERT, 1-4 channels

– Highly integrated functionality

• 8-tap de-emphasis

• CDR with adjustable LBW & peaking

• PLL clock multiplication with adjustable LBW

• CTLE analyzer equalization

• Common- and Differential-Mode Sinusoidal Interference (CMSI/DMSI)

– Protocol awareness

• On-the-fly encoding and decoding (8b/10b, 128b/130b, 128b/132b)

• Scrambler reset, seed, and start sequencing

• Symbol Error Ratio (SER) and Frame Error Ratio (FER) measurements

• Skip Order Set (SKPOS) addition/subtraction for asynchronous clocks

• Dynamic Link Equalization negotiation

• Analysis of Link Training Status State Machine (LTSSM) state transitions

PCIe 3/4 Test

Challenges 27

Take the express lane to design verification

Page

Retimers and PCI Express

28

Page

Definitions

Retimer:

A Physical Layer protocol aware, software transparent, Extension Device that forms two separate electrical Sub-Links.

Re-driver:

A non-protocol aware, software transparent, analog only, Extension Device. Generally a device that does not contain a clock and data recovery (CDR), uses only a Continuous Time Linear Equalizer (CTLE) in the Receiver, and uses a fixed De-emphasis in the Transmitter.

Repeater :

Retimer or Re-driver

29

Page

Retimer State Machine Diagram

30

Page

Retimer Use Models

31

Page

Retimer Use Model Block Diagram

32

Page

Root Complex (Motherboard

33

Page

Slave Loopback

Retimers are required to support slave loopback

The pseudo port that receives the TS1s with the loopback set executes as a loopback Slave

Supports entry from Recovery or Configuration

The other pseudo port places its Transmitter in Electrical Idle

34

Page

Slave Loopback

35

Page

Conclusions 1. 16 GT/s is achievable; however, no silver bullets.

2. Channel length is limited by insertion loss. 12 inches seem to be near the limit without

retimer technologies.

3. Much of what enabled PCIe 3.0 at 8GT/s will be used for 16 GT/s operation (TX EQ, RX

EQ)

4. Channels will need to improve (minimize discontinuities from connectors, consistent

impedance profile of transmission lines, minimizing stubs, via transitions, crosstalk)

5. For channels longer than about 12”, channel extension technologies will be required

(retimer)

6. Tools for full PCIe 4.0 TX and RX BASE testing are available today.

36

Page

PCI Express® 4.0 – Keysight Total Solution Physical layer –

interconnect design

ADS design software

86100D DCA-J/TDR



floor/sensitivity and trigger jitter

37

Page


interconnect design

ADS design software

86100D DCA-J/TDR


Physical layer-

transmitter test

90000 X, Z-Series

oscilloscope

N5393D PCI Express


software




floor/sensitivity and trigger jitter DSA-X Series & Q Series


38

Page


interconnect design

ADS design software

86100D DCA-J/TDR


Physical layer-

transmitter test

90000 X, Z-Series

oscilloscope

N5393D PCI Express


software



Physical layer-

receiver test

M8020A J-BERT High

Perfformance BERT

N5990A automated

compliance and device

characterization test software


floor/sensitivity and trigger jitter DSA-X Series & Q Series


Automated compliance software

– accurate, efficient and

consistent

39

Page

For further information

You will find more information on PCI Express and Keysight test solutions at:

www.pci-sig.com

www.keysight.com/find/pciexpress

www.keysight.com/find/si

www.keysight.com/find/PCIe_receiver_test

PCI-SIG Website, Specification, S/W Tools,

Keysight Test Procedure

Keysight tools to help you succeed with your

PCI Express design such as the N5393D

Compliance application.

Keysight tools to help you master signal

integrity challenges.

PCIe 3.0 Rx Test Detailed Information

40

http://www.pci-sig.com/



http://www.agilent.com/find/pciexpress

http://www.agilent.com/find/si

http://www.agilent.com/find/PCIe_receiver_test

http://www.agilent.com/find/PCIe_receiver_test

Page

Invitation to Join PCI-SIG on Linked-In*

Must be employed by a member company of the PCI-SIG to join.

41

40g/100gbps next generation high speed optical/ … · 台灣是德科技股份有限公司...

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