4. design abstraction and validation vlsi medc 104

MEDC- 104 VLSI Design – Design Abstraction and Circuit Validation

Ayoush JohariAssistant Professor

Department Of Electronics and Communication EngineeringLNCTS. Bhopal

LAKSHMI NARAYAN COLLEGE OF TECHNOLOGY & SCIENCE

The VLSI design process

May be part of larger product design.Major levels of abstraction:

• specification;• architecture;• logic design;• circuit design;• layout.

The Design Problem

A growing gap between design complexity and design productivity

Design Methodology

• Design process traverses iteratively between three abstractions: behavior, structure, and geometry• More and more automation for each of these steps

Dealing with complexity

• Divide-and-conquer: limit the number of components you deal with at any one time.

• Group several components into larger components:– transistors form gates;– gates form functional units;– functional units form processing elements;– etc.

Hierarchical name

• Interior view of a component:– components and wires that make it up.

• Exterior view of a component = type:– body;– pins.

Fulladder

a

bcin

sum

cout

Instantiating component types

• Each instance has its own name:– add1 (type full adder)– add2 (type full adder).

• Each instance is a separate copy of the type:

Add1(Fulladder)

a

bcin

sum

cout

Add2(Fulladder)

a

bcin

sumAdd1.a Add2.a

A hierarchical logic design

z

box1 box2 x

Component hierarchy

top

i1 xxx i2

Hierarchical names

• Typical hierarchical name:– top/i1.foo

component pin

Layout and its abstractions• Layout for dynamic latch:

Stick diagram

Transistor schematic

Mixed schematic

inverter

Levels of abstraction

• Specification: function, cost, etc.• Architecture: large blocks.• Logic: gates + registers.• Circuits: transistor sizes for speed, power.• Layout: determines parasitics.

Circuit abstraction• Continuous voltages and time:

Digital abstraction• Discrete levels, discrete time:

Register-transfer abstraction• Abstract components, abstract data types:

+

+

0010

0001

0100

0011

Top-down vs. bottom-up design

• Top-down design adds functional detail.– Create lower levels of abstraction from upper

levels.• Bottom-up design creates abstractions from

low-level behavior.• Good design needs both top-down and

bottom-up efforts.

Design abstractions

specification

behavior

register-transfer

logic

circuit

layout

English

Executableprogram

Sequentialmachines

Logic gates

transistors

rectangles

Throughput,design time

Function units,clock cycles

Literals, logic depth

nanoseconds

microns

function cost

Design validation

• Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it.

• Forward checking: compare results of less- and more-abstract stages.

• Back annotation: copy performance numbers to earlier stages.

Manufacturing test

• Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right.

• Must quickly check whether manufacturing defects destroy function of chip.

• Must also speed-grade.

VLSI Design MethodologiesFull Custom Design

Semi Custom Design

Gate Array Design

Standard Cell Design

FPGA Based Design

PLA Based Control

Hardwired Control

CPLD Based Design

RT-Level Synthesis

HDL Based Design Methodology

IP Cores, SOCs, DSPs, MEMs

VLSI Design Cycle (1/9)

System Specification

Architectural Design

Logic Design

Circuit Design

Physical Design

Functional Design Fabrication

Packaging


System Specification – Specification of the size, speed, power and functionality of the VLSI system.

Architectural Design – Decisions on the architecture, e.g., RISC/CISC, # of ALU’s, pipeline structure, cache size, etc. Such decisions can provide an accurate estimation of the system performance, die size, power consumption, etc.


Functional Design – Identify main functional units and their interconnections.

No details of implementation.


Logic Design – Design the logic, e.g., boolean expressions, control flow, word width, register allocation, etc. The outcome is called an RTL (Register Transfer Level) description. RTL is expressed in a HDL (Hardware Description Language), e.g., VHDL and Verilog.

X = (AB+CD)(E+F)Y= (A(B+C) + Z + D)


Circuit Design – Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist.


• Net list:net1: top.in1 in1.innet2: i1.out xxx.Btopin1: top.n1 xxx.xin1topin2: top.n2 xxx.xin2botin1: top.n3 xxx.xin3net3: xxx.out i2.inoutnet: i2.out top.out

• Component list:top: in1=net1 n1=topin1

n2=topin2 n3=topine out=outnet

i1: in=net1 out=net2xxx: xin1=topin1 xin2=topin2

xin3=botin1 B=net2 out=net3

i2: in=net3 out=outnet


top

i1 xxx i2

Component hierarchy

VLSI Design Cycle (8/9) Physical Design – Convert the Netlist into a geometric

representation. The outcome is called a layout.


Fabrication – Process includes lithography, polishing, deposition, diffusion, etc., to produce a chip.

Packaging – Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module)

VLSI Design CycleSystem Specification

ArchitecturalSpecification

RTL in HDL

Netlist

Layout

Timing & relationshipbetween functional units

Chips

Packaged andtested chips

ArchitecturalDesign

FunctionalDesign

LogicDesign

PhysicalDesign

Fabrication

Packaging

Circuit Designor

Logic Synthesis

Physical Design Cycle (1/6)

Circuit Partitioning

Floorplanning & Placement

Routing

Layout Compaction

Extraction and Verification

Physical Design Cycle (2/6) Circuit Partitioning – Partition a large circuit into sub-circuits

(called blocks). Factors like #blocks, block sizes, interconnection between blocks, etc., are considered.


Floorplanning – Set up a plan for a good layout. Place the modules (modules can be blocks, functional units, etc.) at an early stage when details like shape, area, I/O pin positions of the modules, …, are not yet fixed.

Deadspace


Placement – Exact placement of the modules (modules can be gates, standard cells, etc.) when details of the module design are known. The goal is to minimize the delay, total area and interconnect cost.

v

Feedthrough

Standard cell type 1

Standard cell type 2

Physical Design Cycle (5/6) Routing – Complete the interconnections between modules.

Factors like critical path, clock skew, wire spacing, etc., are considered. Include global routing and detailed routing.

v

Feedthrough

Type 1 standard cel1

Type 2 standard cell

Physical Design Cycle (6/6) Compaction – Compress the layout from all directions to

minimize the total chip area.

Verification – Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification (extract geometric information to compute resistance, capacitance, delay, etc.)

Design Styles (1/2)

• Full-Custom ASICs– Some (possibly all) logic cells are customized and

all mask layers are customized • Semicustom ASICs

– All logic cells are predesigned (defined in cell library) and some (possibly all) of the mask layers are customized

– Types: Standard-cell based and Gate-array-based ASICs

Design Styles (2/2)

• Programmable ASICs– All logic cells are predesigned and

none of the mask layers are customized– Types: PLD (Programmable Logic Device) and

FPGA (Field Programmable Gate Array)

Full-custom ASICs (1/3)

• Engineers design some or all of the logic cells, circuits, or layout specifically for one ASIC– Full-custom ICs are the most expensive

to manufacture and to design– Manufacturing lead time (the time it takes just to make an

IC – not including design time) is typically 8 weeks

Full-custom ASICs (2/3)

• When does it make sense?– there are no suitable existing cell libraries available– existing logic cells are not fast enough– logic cells are not small enough– logic cells consume too much power– ASIC is so specialized that

some circuits must be custom designed

• Trends: fewer and fewer full-custom ICs are being designed (excluding mixed analog/digital ASICs)

Full Custom Design (3/3)

Standard-Cell-Based ASICs (1/5)• Cell-Based ASIC (CBIC) uses predesigned cells

(AND, OR gates, multiplexers, flip-flops, ...)• Standard-cell areas are built of rows of standard cells• Standard-cell areas can be used in combination with larger

predesigned cells (microcontrollers, or even microprocessors), known as megacells

A cell-based ASIC (CBIC) die with a single standard-cell area combined with 4 fixed blocks

Standard-Cell-Based ASICs(2/5)

• Characteristics– custom blocks can be embedded;

ASIC designer defines only the placement of the standard cells and the interconnect in a CBIC

– standard cells can be placed anywhere on a silicon =>all mask layers of a CBIC are customized

– manufacturing lead time is 8 weeks

Standard-Cell-Based ASICs (3/5)• Advantages

– designers save time, money, and reduce risks using a predesigned, pretested, and precharacterized standard-cell library

– standard cells in the library are constructed using full-custom;each standard cell can be optimized individually(for example, to maximize speed, minimize area, etc);

• Disadvantages– time or expense of designing or buying the standard-cell library– time needed to fabricate all layers of the ASIC for each new

design

Standard-Cell-Based ASICs(4/5)• Standard-cells are designed

to fit horizontally together to form rows• Internal construction of a cell

- 25 microns wide (lambda is 0.25)- AB: abutment box - BB: bounding box- Power supplies: VDD, GND- Each different shaded and labeled pattern represents a different layer- Connections: A1, B1, Z

Standard-Cell-Based ASICs (5/5)

• Routing the CBIC- Interconnections between cells use spaces (called channels) between rows - 2 separate layers of metal interconnect (metal1 and metal2) running at right angles to each other- Feedthrough: refers either to the piece of metal that is used to pass a signal through a cell or to a space in a cell waiting to be used as a feedthrough

Gate-Array-Based ASICs

• In gate-array-based ASIC transistors are predefined on the silicon wafer– Base cell – the smallest element that is replicated– Base array – the predefined pattern of transistors

• Masked Gate Array (MGA): only layers which define the interconnect between transistors are defined by the designer using custom masks

• Designer chooses from a gate-array library predesigned and precharacterized logic cells (often called macros)

Gate-Array-Based ASICs (1/4)

• Since only metal interconnections are unique for MGA, we can use prefabricated wafers (with completed transistor layers) – the turnaround time is reduced to a few days or at most a

couple of weeks– the costs for all the initial prefabrication steps for MGA are

shared for each consumer => the cost of an MGA is reduced compared to FC and CBIC

• Types: Channeled, Channelless, and Structured Gate Array


• Channeled gate array– we leave space between the rows of transistors for wiring

• Characteristics– only interconnect is customized– the interconnect uses predefined spaces between rows– manufacturing lead time is between 2 days and 2 weeks


• Channel less gate array (sea-of-gates or SOG)– there are no predefined areas set aside

for routing between cells – we customize the contact layer that

defines the connections between metal1 and transistors– when use area of transistor for routing,

do not make any contacts to the device underneath

• Characteristics– only some (the top few) mask layers

are customized – the interconnect – manufacturing lead time is

between 2 days and 2 weeks

Gate-Array-Based ASICs (4/4) Structured gate array or embedded gate array

combines features of CBIC and MGA motivation: MGA has only fixed gate-array base cell;

difficult and inefficient implementation of memory we set aside some IC area and dedicate it to a specific function

(contain different cells, more suitable for building memory cells, for example, or complete block, such as a microcontroller)

Characteristics only some (the top few) mask layers

are customized – the interconnect custom blocks can be embedded manufacturing lead time is

between 2 days and 2 weeks problem: embedded function is fixed

Programmable Logic Devices(1/2)

• PLDs– standard ICs, available in standard configurations– sold in high volume to many different customers– PLDs may be configured or programmed to create

a part customized to specific application• Characteristics

– no customized mask layers or logic cells– fast design turnaround– a single large block of programmable interconnect– a matrix of logic macrocells that usually consists of

programmable array logic followed by a flip-flop or latch

Programmable Logic Devices(2/2) Types of PLDs

PROM: uses metal fuse that can be blown permanently) EPROM: used programmable MOS transistors whose characteristics

are altering by applying a high voltage PAL – Programmable Array Logic

programmable AND logic array or AND plane, and fixed OR plane

PLA – Programmable Logic Array programmable AND plane

followed by programmable OR plane Depending on how

the PLD is programmed erasable PLD (EPLD) mask-programmed PLD

Field-Programmable Gate Arrays (FPGA)• FPGA

– a step above the PLD in complexity;it is usually larger and more complex than a PLD

– rapidly growing in importance• Characteristics

– none of mask layers are customized– a method for programming basic cells

and the interconnect– the core is regular array

of programmable basic logic cells (combinational + sequential)

– a matrix of programmable interconnectthat surrounds the basic cells

– programmable I/O cells around the core– design turnaround is a few hours

Economics of ASICs

• Goal– discuss the economics of using ASICs in a product and compare

the most popular types of ASICs: an FPGA, an MGA, and a CBIC

• Warning! – costs change rapidly and IC industry is notorious for keeping its

costs, prices, and pricing strategy closely guarded secrets, so the numbers we will use to illustrate the different components of cost are approximate

• Part cost– vary enormously: from a few dollars to several hundreds– FPGAs are more expensive per gate than MGAs– MGAs are more expensive per gate than CBICs

Levels of VLSI Design in a Traditional Flow• Specification

– what the system (or component) is supposed to do

• Architecture– high-level design of component

• state defined• logic partitioned into major blocks

• Logic– gates, flip-flops, and the connections

between them

• Circuit– transistor circuits to realize logic elements

• Device– behavior of individual circuit elements

• Layout– geometry used to define and connect

circuit elements

• Process– steps used to define circuit elements

High Level Synthesis

GDSII

Synthesis

Placement

Routing

Extraction and Timing Verification

Manufacturing

Architecture Design

Verification

RTL

Design Principles (Traditional)

• Partition the problem (hierarchical design)– Different abstraction levels: RTL, gate-level, switch-level, transistor-

level

• Orthogonize concerns– Abstraction vs. implementation

– Logic vs. timing

• Constrain the design space to simplify the design process– Balance between design complexity and performance– E.g., standard-cell methodology

VLSI Design Flow Evolution

• Expanding in two directions– System-on-Chip (SoC) Design

– Design for Manufacturability (DFM)

• More design metrics– Area

– Timing

– Power

– Signal Integrity

– Reliability

• Tighter Integration– Design closure

– RTL/GDSII sign-off re-defined


GDSII

Synthesis

Placement

Routing


Manufacturing

Architecture Design

Verification

RTL

Design Procedure and Tools

• Behavior modeling– Matlab/C/VHDL

• Logic synthesis– DesignCompiler, BuildGates, …– Verification of synthesis

• Formal Verification (Verplex)• Static timing analysis (PrimeTime)

• Place and route– Astro, SOCE, …– Verification of layout

• DRC, ERC, LVS (Calibre)• Extraction (SignalStorm)• Delay Calculation (CeltIC)• Simulation (SPICE)

• DFM


GDSII

Synthesis

Placement

Routing


Manufacturing

Architecture Design

Verification

RTL

Design Principles(State of the Art)

• Integrate the problem (design closure)– Back-annotation, predictability

• Balance design metrics– Area/timing/power/signal integrity/reliability

• Explore the design space– Balance between design complexity and performance

– Platform-based SoC design

Design Methodologies (+ business models)• Full-Custom (high effort, leading-edge performance, high-volume)• Semi-Custom (strong infrastructure, economical in lower volumes)

– ASIC (Application-Specific Integrated Circuit)– Standard Cell/Gate Array/Via Programmable/Structured ASIC

• FPGA• Special

– Analog (custom layout, I/Os and sense amps)– Mixed-Signal / RF (unique to each process, no scaling)

• System-on-Chip ( System-in-Package)– Various components: IP blocks, ASIC, FPGA, memory, uP, RF, etc.– Define implementation platform, hardware-software co-design– Performance vs. complexity

Test Generation

Design Verification

Timing Verification

Simulation

Floorplanning

Logic PartitioningDie Planning

LogicSynthesi

s

Logic Design and

Simulation

Behavioral Level Design

Global Placement

Detail Placement

Clock Tree Synthesis

and Routing

Global Routing

Detail Routing

Power/Ground Stripes, Rings

Routing

Extraction and Delay Calc. Timing Verification

LVSDRCERC

IO Pad Placement

Traditional Taxonomy

Front End

Back End

Generic Flow Steps• Library preparation

– Library data preparation

– Design data preparation

• Logic design– Specification to RTL

– RTL simulation

– Hierarchical floorplanning

– Synthesis

– Formal verification

– Gate level simulation

– Static timing analysis

Physical design• Physical floorplanning

• Place and route

• RC extraction

• Formal verification

• Physical verification

• Release to manufacturing

Design for test Engineering change order

Library and Design Data• Models and technology data required to execute the design

flow• Power, timing: ALF, DCL, OLA, .lib, STAMP• Layout: LEF, DEF, GDSII• Delays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF,

SPEF, SPICE• Layout rules: Dracula, Calibre “deck”

Architecture Design• Platform-based SoC Design

– Platform is a library of design resources– Helps design space exploration– Meet in the middle

• Embedded system– Hardware-software co-design

Application space

Application instance

System platform

Platform instanceArchitecture space

Platform specification

Platform design-spaceexploration

High-Level Synthesis (Behavior RTL)• Scheduling

– Assignment of each operation to a time slot corresponding to a clock cycle or time interval

• Resource allocation – Selection of the types of hardware components and the number for each

type to be included in the final implementation• Module binding

– Assignment of operation to the allocated hardware components• Controller synthesis

– Design of control style and clocking scheme• Compilation

– of the input specification language to the internal representation• Parallelism extraction

– usually via data flow analysis techniques

Architecture Level Floorplanning

• Defines the basic chip layout architecture– Define the standard cell rows and I/O placement locations– Place RAMs and other macros– Separate gate array, memory, analog, RF blocks– Define power distribution structures such as rings and stripes– Allow space for clock, major buses, etc.

• Rules of thumb for cell density are used to initially calculate design size

Logic Synthesis• Conversion of RTL to gate-level Netlist

– Targeted to a foundry-specific library

– Can be performed hierarchically (block by block)

• Timing-driven– Clock information– Primary input arrival times, primary output required times– Input driving cells, output loading– False paths, multi-cycle paths

• Interconnect delay may be calculated based on a “wireload model” which uses fanout to estimate delay

• Clock parameters (insertion delay, skew, jitter, etc.) are assumed to be attainable later in place and route

Formal Verification• RTL description and gate level netlist are compared to verify

functional equivalence, thereby verifying the synthesis results– Formal methods– Graph isomorphism– Binary Decision Diagram (BDD)

• Emerging technology that supplements the more traditional gate-level simulation approach

• FV also performed after place-and-route (if gate Netlist changes)

RTL Simulation• RTL code, written in Verilog, VHDL or a combination of both,

is simulated to verify functional correctness• Test benches apply input stimulus to the design• Several methods are used to verify the outputs

– Self-checking test benches automatically verify output correctness and report mismatches

– Results can be stored in a file and compared to previous results– Waveform displays can be used to interactively verify the outputs

Gate-Level Simulation• Covers both functionality and timing• Correctness is only as good as the test vectors used• Especially critical for non-synchronous designs, verification of false

path and multi-cycle path constraints• Cell timing is included in the simulation models and interconnect

delay is passed from the synthesis run• Worst case PVT conditions are used to analyze for setup violations,

and best case PVT conditions are used to analyze for hold violations– PVT = Process, Voltage, Temperature

Static Timing Analysis• Verifies that design operates at desired frequency

– Implicitly assumes correct timing constraints (!), e.g., boundary conditions• Timing constraints are similar to those used by logic synthesis• Verifies setup and hold times at FF inputs; can also check timing from and

to PI’s and PO’s; can also check point-to-point delay values (with blocking of pins, etc.)

• As with gate-level simulation, both best- and worst-case analysis is performed

• Typically performed on full-chip (not block) basis– May require modified constraints for inter-block issues: multiple clock domains,

multi-cycle paths, etc.• For compatibility with timing-driven layout flow, helps to have simple /

single set of constraints – Other issues: incremental analysis, …

Block-Level Physical Floorplanning• Reconcile logical and physical hierarchies• Cells that are interconnected want to be close together

– Take advantage of RTL hierarchy– Generate a physical hierarchy– RTL hierarchy = best physical hierarchy?

• Often bundled within the same cockpit as the place and route tool

• Give placement some initial clues to reduce complexity

Place and Route• Automatically place the standard cells• Generate clock trees• Add any remaining power bus connections• Route clock lines• Route signal interconnects• Design rule checks on the routes and cell placements• Timing driven tools

– Require timing constraints and analysis algorithms similar to those used during the static timing analysis step

RC(L) Extraction• Calculate resistance and capacitance (and inductance) of

interconnects – Based on placement of cells– Routing segments

• Calculate capacitive (inductive) effects of adjacent segments – Extract capacitance between metal segments

• RC(L) data transferred back to – Static timing analysis (back annotation)– Gate level simulation– Replaces wire load model used in synthesis

• Drive delay calculation, signal integrity analysis (crosstalk, other noise), static timing.

Physical Verification• DRC – Design Rule Check

– Spacing, min dimension rules.

• LVS – Layout Versus Schematic– Verifies that layout and Netlist are equivalent at the transistor level.

• Electrical Rule Check– Dangling nets, floating nodes.

• GDSII (Stream Format)– Final merge of layout, routing and placement data for mask

production.

Release to Manufacturing• Final edits to the layout are made

• Metal fill and metal stress relief rules are checked

• Manufacturing information such as scribe lanes, seal rings, mask shop data, part

numbers, logos and pin 1 identification information for assembly are also added

• DRC and LVS are run to verify the correctness of the modified database

• ‘Tapeout’ documentation is prepared prior to release of the GDSII to the foundry

• Pad location information is prepared, typically in a spreadsheet

• Cadence’s Virtuoso is used for custom-manual edits of the mask layers

• Manufacturing steps

– generation of masks

– silicon processing

– wafer testing

– assembly and packaging

– manufacturing test

Fnl. Design

Synthesis

Clock distribution

Design Specs

Lib.+CWLMConstraints

Route, scan re-order

Timing analysis, IPO

ERC, DRC, LVS

Tape-out

Fnl., pwr., SI ECO

Reqmts.

Floor-plan & PGLib.+CWLM

Placement

• Architectural optimization (timing)• Inter-group buses, bandwidth• Clock, SI, test; validation

• Row definitions• Placement of cells• Congestion analysis

• Full RC back-annotation• Hierarchical timing, electrical and SI

analysis and IPO/ECO

• Floorplanning and custom WLM• Power distribution (Internal, I/O)• I/O driver, padring design• Board-level timing, SI

• Placement-based re-synthesis• Noise minimization, isolation • Clock distribution

• Full routing• Scan stitching, re-ordering

Physical re-synth

Detailed Design Flow

More Design Metrics and Techniques• Area

– Cell area– Wirelength

• Timing– Gate– Interconnect

• Power– Dynamic– Static– Leakage

• Signal Integrity– Crosstalk (capacitive, inductive)– Supply voltage drop (IR drop, LdI/dt)

• Reliability– Variation (Vdd, thermal, process variation

(tox, BEOL))– Electromigration– Hot electron effect (SEU)

Cost minimization Synthesis (technology mapping) Placement, routing

Performance optimization Logic transformation, transistor sizing Buffering, re-routing

Power minimization Gating (sleep transistors), variant Vdd Process optimization Dual-Vth

Signal Integrity Sizing, net ordering, shielding P/G design, placement, synthesis

Reliability Statistical design optimization Design margin

Past (250–180nm) Present (130–90nm) Future (65nm –)

Functional

Performance

Testability

Verification

SPEC

Hw/Sw

SW

Logic

Circuit

Place

Wire

other

Perf.

Timing

Power

Noise

Test

Mfg.

otherRepository

Hw/Sw

Data

Model

Optimize Analyze

Comm.

Cockpit

Auto-Pilot

EQ

ch

eck

MASKS

System Design

System

Model

MASKS

SPEC

System Design

System

Model

SWRTL

Functional

Verification

Performance

Testability

Verification

Logic

Place

Wire

other

Timing

Power

Noise

Test

otherRepository

Data

Model

Optimize Analyze

Comm.

Cockpit

Auto-Pilot

EQ

Ch

eck

SW

Opt

HW/SW

Opt

Perf.

Model

System

DesignSystem

Model

File

Synthesis

+ Timing Analysis

+ Placement Opt

File

Place/Wire

+ Timing Analysis

+ Logic Opt

SW

Opt

Performance

Testability

Verification

Functional

Verification

MASKS

RTL

SW

EQ

Ch

eck

HW/SW

Optimization

Multiple design files are converged into one efficient Data Model

Disk accesses are eliminated in critical methodology loops

Verification of function, performance, testability and other design

criteria all move to earlier, higher levels of abstraction followed by

Equivalence checking

Assertion-driven design optimizations

Industry standard interfaces for data access and control

Incremental modular tools for optimization and analysis

Past (250–180nm) Present (130–90nm) Future (65nm –)

Functional

Performance

Testability

Verification

SPEC

Hw/Sw

SW

Logic

Circuit

Place

Wire

other

Perf.

Timing

Power

Noise

Test

Mfg.

otherRepository

Hw/Sw

Data

Model

Optimize Analyze

Comm.

Cockpit

Auto-Pilot

EQ

ch

eck

MASKS

System Design

System

Model

MASKS

SPEC

System Design

System

Model

SWRTL

Functional

Verification

Performance

Testability

Verification

Logic

Place

Wire

other

Timing

Power

Noise

Test

otherRepository

Data

Model

Optimize Analyze

Comm.

Cockpit

Auto-Pilot

EQ

Ch

eck

SW

Opt

HW/SW

Opt

Perf.

Model

System

DesignSystem

Model

File

Synthesis

+ Timing Analysis

+ Placement Opt

File

Place/Wire

+ Timing Analysis

+ Logic Opt

SW

Opt

Performance

Testability

Verification

Functional

Verification

MASKS

RTL

SW

EQ

Ch

eck

HW/SW

Optimization

















Design Flow Evolution (ITRS-2003)

Constructive Interconnect Prediction• Statistical models have their limitations• Critical paths and the law of small numbers

– Statistics properties, e.g., average wire length.– Extreme statistics properties, e.g., critical path length.

• Implementation details– Routing congestion, e.g., horizontal effect.– Timing optimization, e.g., layer assignment.– Via blockage, pin accessibility, wrong way routing, etc.

• Predict by construction (physical synthesis)– try a fast (global) router .

Goal: Design Convergence• What must converge?

– logic, timing, power, SI, reliability in a physical embedding– support front-end signoff with a predictable back-end

• Achieve Convergence through Predictability– correct by construction (“assume, then enforce”)

• constraints and assumptions passed downstream; not much goes upstream

• ignores concerns via guardbanding• separates concerns as able (e.g., FE logic/timing vs. BE spatial

embedding)– construct by correction (“tight loops”)

• logic-layout unification; synthesis-analysis unification, concurrent optimization

– elimination of concerns• reduced degrees of freedom, pre-emptive design techniques• e.g., power distribution, layer assignment / repeater rules

Floorplan / Placement

Routing

“Physical Prototyping Philosophy”

• Prototype delivers accurate physical data.

• Levels of accuracy– Placement-acknowledgeable synthesis

(PKS)– Including global route– Post-detailed-route (In-Place

Optimization, i.e., IPO)

• Hierarchical timing budgeting:– Chip-level CTS, top-level route and IPO,

power analysis and grid design– Block-level synthesis, placement, IPO,

routing

• “Handoff with enough physical information to ensure correct results”

RTL

Gates

Physical Prototype

Functionality known

Timing / routability known

M. Courtoy, Silicon Perspective

Coarse Placement Drives Partitioning, Coarse Routing Drives Pin Assignment / Timing Opt

• Full-chip prototype results in optimal pin placement– Results in narrower

channels and reduced die size

– Reduces the routing congestion

– Improves the chip timing

• Accurate timing budgets result in predictable timing convergence

Physical Prototype Partitioning

Block 1

Block 2

Block 3

Block-Level Timing BudgetsBlock-Level Pin Assignments

Power IR Drop Analysis

Hierarchical Clock Tree Synthesis

Full Chip Power Planning

Block-Level Optimization

Timing Closure

150psskew

120ps skew50psskew

50psskew

100psskew

130ps skew

PlaceDetailed Trial Route

RC ExtractionDelay Calc / STA

IPO

Full ChipPhysical

Prototype

Partition

“Tape Out Every Day”

Nine pieces of Eight…Remember Pirates of Caribbean :

References1. Sedra, Adel S., and Kenneth Carless Smith. Microelectronic circuits. Oxford University

Press, 1987.

2. Neil H.E. Weste, David Harris, Ayan Banerjee; CMOS VLSI Design, A Circuits and Systems Perspective, third edition, Pearson.

3. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits” , A Design perspective Second edition.

4. Course Notes – from Brown, Berkeley University, IITs and others

Thank You...

4. design abstraction and validation vlsi medc 104

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