3d integration of sensors and electronics · • all three 3d chips worked –vip and victr tested...

Ronald Lipton

3D Integration of Sensors and Electronics

9/12/2017 Ronald Lipton | 3D Integration of Sensors and Electronics1

3D Electronics


A three dimensional integrated

circuit is composed of two or more

layers of active electronic

components, integrated vertically by

wafer bonding, thinning, and by

insertion of through silicon vias

(TSV) to connect layers. This is

enabled by a suite of process

technologies developed by industry

RTI Inc DARPA demonstrator ~ 2008

8 micron pitch, 50 micron thick oxide bonded imager (Lincoln Labs ~ 2006)Teledyne 3D stacked Si-CMOS-on-InP by DBI - 2017

TSV

The 3D Promise


Detector

BulkSilicon BulkSilicon

WirebondsOutputinterconnect

Current Pixel detector designs

3D Assembly

detector

• 3D interconnect frees us from the

design tyranny imposed by traditional

edge-based connections

• Very fine pitch bonding (~3 micron)

• Much better power distribution and

connectivity

• Radiation hard, thin sensors and

readout

• Complex electronics without expensive process nodes

• Separation of analog and digital – lower thresholds

• Lower interconnect capacitance – faster, lower power devices

• Tiled, large area devices

• Cost/availability (?)

We are dependent on commercial developments – industry is moving with

increasing speed towards advanced 3D packaging

Fermilab 3D History


FNAL Work on 3D sensors and

interconnects began with studies for the

challenging ILC vertex detectors, which

require small pixels, low mass and power,

and pulse height and time information. We

realized that these technological challenges

could be met by emerging 3D interconnect

and bonding technologies. This led to:

• Work with MIT-LL on their DARPA

funded 3D pilot runs (VIP) -2006

• Work on sensor thinning and backside

contact formation by laser annealing with

Cornell – 2007-10

• Work with Ziptronix on demonstrations

of the DBI bonding process using

BTeV wafers – 2008

• 3D Demonstration project with ILC, x-

ray, CMS designs - 2009-2012

Current work on x-ray, CMS trigger …

9.9mm

BTeV ROICs DBI bonded to sensor thinned to 100 m 2008

MIT-LL 3-layer stack and VIP layout - 2006

50 Micron sensor with laser annealed contact - 2007

3D Demonstration Project


Fermilab led a consortium to demonstrate 3 dimensional electronics – a 4+ year

effort.

• A working 3D process was demonstrated using 2-tier 3D Global Foundries 0.13

mm TSV wafers. FNAL chips for ILC(VIP), CMS(VICTR) and X-ray imaging

(VIPIC) in collaboration with Tezzaron and Ziptronix.

• This took about 18 months longer than anticipated – Tezzaron copper bonding

issues finally solved by using Ziptronix DBI process

LEFT (bottom)chips

Right (top)chips

VICTR VIPVIP

VIPIC VIPIC

I believe this is now the most

widely accepted 3D process.

• Use oxide bonding to bond

planarized wafers with embedded

metal contacts

• Uses standard fab processes

• Low temperature (reworkable) initial

bond and subsequent anneal

• Very fine (~3 micron) pitch

• Wafer-to-wafer or chip-to-wafer

bonding

Direct Bond Interconnect

(DBI) Process


Chip-to-Wafer bond

R. Lipton 7

DBI bonding of ROICs (VICTR, VIPIC, VIP) to BNL sensor wafer

6” sensor wafer

DBI bonded chips

Expose TSVs, pattern Top aluminum

Wafer-wafer3D Bond

Oxide bond Handle wafer

Expose sensor side TSVs, pattern DBI structures

Dice

DBI bond ROIC chips to sensor wafer (RT pick+Place)

Grind and etch to expose top connections

Sensor Integration – Three tier devices


We then chip-to-wafer oxide (DBI) bonded the two-tier 3D chips

to BNL sensors to form three-tier integrated sensor/electronics

assemblies. This included removal of the top handle wafer and

pattering of top contacts

– VIP(ILC), VICTR(CMS), and VIPIC(X-Ray) assemblies

Wafer-wafer bond

1

2

3

.5 mm sensor(BNL)

34 micron high 2-tier VICTR chip

Chip-wafer bond

34 m


• All three 3D Chips worked – VIP and VICTR tested on the bench. VIPIC was extensively tested in particle and x-ray beams.

• Yields were about 50% - 3D bonding and multiple tier assembly

• VIP(ILC) is on hold – no ILC R&D fundsVICTR not relevant to current CMS design

3D Test Results

CD109 radiogram of tungsten mask

400x400 mmmask

VIP – 24m pixels, Time stamp, ADC

0

50

100

150

200

250

300

350

400

450

500

25 30 35 40 45 50 55 60 65

Counts

noise(electrons)

Unbonded

Bumpbonded

FusionBonded

For the VIPIC x-ray imaging chip we were able to compare noise of the oxide-bonded pixels to the same chip with bump bonds. The noise in the oxide bonded pixels is almost a factor of two lower than the conventionally bump bonded parts due to lower capacitance.

Next generation VIPIC-Large


• As a result of our work on VIPIC condensed matter

funded an effort to develop a 3D-based focal plane for

x-ray correlated spectroscopy.

• 3D chip based on VIPIC

– Wafer bonded 130 nm readout chips

– Chip to wafer bonds to sensor wafer

– Bump bonds to ceramic readout board

Submission combined with VIPRAM 3D trigger chip

Progress has again been slow – Novati has had issues

with installing the DBI process in Austin fab and is 9

months late and stalled.

to expose the back-side pads on the digital tier. The resulting sensor/ASIC hybrids are then bump-bonded to a ceramic

readout board as shown in the Figure 1.

The major advantages of this assembly include complete separation of digital activity from low-noise analog parts, large

active area with minimal gaps, uniform distribution of power supplies and I/O pads on the back side. Furthermore the

ASIC’s can be integrated with sensors without bump-bonds. These fusion bonded devices yield a lower equivalent noise

charge compared to their bump-bonded counterparts [2].

Figure 1. Single module 3D integrated edgeless camera

2. ANALOG & DIGITAL PIXELS AND INTER-CONNECTIONS

Each pixel in the analog tier is 65µm x 65µm, and is designed using full custom analog layout. It contains a signal

processing chain which includes a charge sensitive amplifier (CSA) with sensor leakage current compensation, followed

by a two stage shaping filter and a window discriminator. Two, 7-bit trimming Digital to Analog Converters (DAC) are

used to remove systematic offsets in the comparators in every pixel. Each digital pixel consists of a hit processor, 7-bit

counter, 21-bit configuration register and a priority encoder for zero-suppressed readout. Each digital and analog pixel

exchange approximately 40 electrical signals between them. This requires the digital pixel to have the same bonding

interface as the analog pixel (mirror image).

To easily assemble a large ASIC with an area greater than 1 cm2, the 192 x 192 pixel matrix is sub-divided into 36 smaller

sub-chips, each containing an array of 32 x 32 pixels. The choice of the number of pixels in a sub-chip, is determined by

several factors such as number of data I/O’s required per chip, length of pixel address which defines the length of an output

data packet, etc.

Each analog pixel is an indivisible unit. These are arranged in a 32 x 32 array to create a sub-chip. A few flavors of analog

pixels with minimal variations are created to allow different analog biasing transistors to be placed within different analog

pixels. On the other hand, the digital functionality is not physically confined within a pixel but is distributed across a 32 x

32 array to create an indivisible sub-chip shown in Figure 2. This is an essential, unprecedented implementation step, for

the edgeless floorplan of the detector, as apart from the pixel logic, the digital tier also needs a high speed output serializer,

several differential line drivers and receivers and other additional chip-level functional blocks. Additionally, all global

analog signals including power and biases from the readout board have to be conveyed through the digital tier, requiring

the use of all metal layers for connectivity to the analog tier, hence areas within the sub-chip are reserved for distributing

these signals.

The analog and digital tiers are face-to-face connected using a uniform fusion bonding interface. Metal 9 is added to create

metal bonding posts, embedded in oxide. This process results in a highly planar surface topography, required for fusion

bonding. The bonding interface is used for exchanging electrical signals while also providing mechanical support. The

metal bond post is an octagonal PAD 2.5µm in diameter arranged in a 5µm pitch. The pads which are used for electrical

connectivity have vias from metal 9 to metal 8 (last foundry metal layer), which are then routed to the relevant circuitry.

VIPIC digital

VIPIC analog

• Digital 3D chip designed for

associative memory based pattern

recognition

• AM Concept used for ATLAS FTK

and CDF but x 400 speed/density

• Tiers can correspond to barrel layers, ask

for vertical coincidences

Goal: >~200K patterns/chip @ >~200MHz

• 2D 28nm ~ 2D two tier 40nm ~ multi-tier in

65nm

This is currently not the baseline option for

CMS – R&D is continuing as a backup

VIPRAM


!

Design involved

CAM cell design

Majority Logic

Cell design

Control/interface

Initial R&D goal:Proof-of-principle demonstration

CAM tier

Logic tier

Via-Last TSVs


Through Silicon Vias (TSV) are inserted after the

wafer is processed (via-last) enable the use of

wafers from virtually any foundry for 3D. Needed

because Chartered-> Global Foundries dropped

TSV process after initial fabrication

• Fermilab worked with Tezzaron to demonstrate

this technology which will be used in future 3D

submissions

• TSV yield < 1 bad in 104-105 satisfactory for

good IC yield, and continues to improve.

x-section of W-filled TSVs from Fermilab test-TSV wafers run 256 good chains out of 268 chips (110k TSV/chain)

𝐶𝐵−𝑇𝑆𝑉 = 7.8𝑓𝐹

3D integration differs from classical bump bonding in that it is

lowest cost as a wafer-to-wafer process. It is intrinsically an

“edgeless” process - access to I/O and power is vertical rather

than at the edge. Tiling a large array requires good yield for

both the sensor, the bond, and the associated readout chip.

“Active tiles” are a natural high yield solution:

• Utilize active or slim edge sensor wafers

• Avoid classical through-silicon-vias with top-side thinning

and metal redistribution of the ROIC wafer (demonstrated)

• A two-tier test assembly has been fabricated and is being

laser-diced

Prospects - Active Tiles

9/12/2017

Silicon(10m)

oxide

SiliconSensorInterconnect

DBI

contact

Handle wafer

sensor

trenches

Buriedoxide

readoutIC and pads200 micron

Goal – very high dynamic range low noise x-

ray imaging sensor.

• 50mm×50mm pixel, Low noise ~ 10 e- r.m.s.

• Built-in adaptive gain

• Single photon resolution for 0.25-2.0 keV

• Large dynamic range ~104

• Fast frame readout 10 KHz

CMOS sensor lower tier with front end

transistor/charge sluice

• Small charge readout with source follower

• Large charge directed to through sluice to

charge sensitive amplifier

Top ASIC provides signal processing and

readout

Prospects - FLORA


The time resolution due to noise-related jitter for a constant

voltage threshold can be expressed as:

𝜎𝑡~𝜏𝑟𝑖𝑠𝑒𝑁

𝑆+ 𝑠𝑦𝑠𝑡𝑒𝑚 𝑒𝑓𝑓, 𝜎𝑡~

𝜎𝑛𝜕𝑉𝜕𝑡

with front-end noise:

𝜎𝑛2 =

𝐶𝐿2(4𝑘𝑡𝐴)

𝑔𝑚𝑡𝑎, 𝜎𝑡 ≈

𝐶𝐿𝑔𝑚𝑡𝑎

𝑡𝑎2 + 𝑡𝑑

2

and slew rate (dV/dt) related to the inverse amplifier and

detector rise time

• LGADs achieve time resolution by increasing signal

using avalanche gain.

• Similar resolution can be achieved by lowering noise

(capacitance)

Pixel capacitance can be a few ff. – but the interconnect C

can dominate.

The sensor can be thinned (to ~50 microns or so) using

either Si-Si bonding or an epitxial layer, and retain good

signal/noise due to the small load capacitance.

This system would be very radiation hard.

Prospects - Fast Timing – Some speculation


Figure 2 Pixel TCAD model.

y = 2E-18x2 + 1E-16x + 1E-15

0

5E-15

1E-14

1.5E-14

2E-14

2.5E-14

3E-14

0 20 40 60 80 100 120

200 Micron Thick Detector

Farads/m

icron

pitch

We note that a ~ 1mm Si pixel with a fast amp has ~200 ps

resolution. We can scale to get the time resolution of a smaller

pixel.

To compare a 1mm pixel to a 100 x 50 (thick) mm pixel:

𝐶𝑡𝑜𝑡 1𝑚𝑚 ~2.4𝑝𝑓, 𝐶𝑡𝑜𝑡 100𝜇𝑚 ~40𝑓𝑓~ 𝑥 1/60 + 𝑖𝑛𝑡𝑒𝑟𝑐𝑜𝑛𝑛𝑒𝑐𝑡

now assume a x 4 lower gm for the smaller pixels we can

estimate st:

200𝑝𝑠 ×𝑔𝑚𝑐

= 200 ×2

40𝑝𝑠~10𝑝𝑠

This requires the interconnect capacitance to be very small –

achievable in 3D interconnects.

Prospects - Fast timing


Suppose you want to measure HE x-rays

with good timing (thin silicon) with high

efficiency (thick silicon)

• X-rays converting deep generate

bipolar pulses in many channels – due

to weighting field

• These have fast rise time an can

provide multiple samples in neighbor

pixels for deep conversions

• With good s/n the bipolar signals can

trigger discriminators

• A 3D analog/digital stack can analyze

the local hit pattern to extract the best

timing based on conversion depth

This is just a thought now – an example of

possibilities

Tricks with small pixels


25m

185m

12ns

33 micron pitch200 micron thick

• 3D is now an industry mainstream technology,

especially for cell phone cameras

• We are limited to vendors who will work with

smaller customers, and have processes under

control

– In some cases we have found exaggerated

claims based on a few prototypes

– Others (Ziptronix) showed excellent technical

capability and interest

• There is rapid industry change, with continuous

consolidation

• In HEP we need a “sweet spot” of vendors willing to

process small numbers of high value added

devices

• Progress has been slow in HEP, process is

expensive, difficult to apply to large areas

• x-ray imaging requirements for very fast complex

imagers is growing may be more of a “sweet spot”

Is this (still) Snake Oil?


Sony Image sensor with3 micron pitch DBI

• Vertical Interconnect

(TSV)

– Via First, middle, last

• Wafer bonding

– Oxide bonding

– Cu-Cu bond

• Wafer Interconnect

– Microbumps

– DBI

• Topology

– Die-Die, Wafer-Wafer,

Die-Wafer, interposer

3D Landscape


Eric Beyer, IMEC

Devolution


Ziptronix(DBI wafer bonding)

Tezzaron(Memory)

Chartered(IC Fab, Singapore)

SVTC(R&D Foundry)Sematech->Cypress->SVTC

GF(no via first)

Develop via last TSV

Tessera(licensing)

Fab

DBI

Novati(Fab)

Tezzaron(3D memory)

Nhanced(R&D)

(cu bonding) (DBI bonding)

(via first)

AustinFab

DBI Process Availability


Vendor Wafer Diam Wafer-Wafer Die-Wafer TSV Available?

Sony - Not to you

Novati 8” ✓ ~1 mmIn

development

Teledyne Dalsa

6”, 8” ✓ ~5 mmIn

Development Spring 2018

Sandia 6”->8” developing ✓ noIn

Development

IZM 12” ✓ no ~5 mm Yes

Raytheon 8” ✓ - ?

• 3D integration continues to be

a very compelling capability

• Did not talk about

– 2.5 D

– Microbumps

– Interposers

• It has taken a long time to mature …

• There are still no proven vendors for

HEP

• The combination of very low interconnect capacitance and

geometrical and packaging options can be transformative.

• No large-scale HEP applications yet

• This is moving ahead for x-ray imaging where scales are smaller

and there is more risk tolerance.

Summary and Prospects


A three-dimensional integrated circuit,made possible with carbon nanotubes (CNTs). Physics Today 70, 9, 14 (2017)

3D Results –

VICTR – CMS 5

Tier track trigger

chip

R. Lipton23

R.Lipton 3

Longstrip(5mm)sensor

Shortstrip(1mm)sensor

Interposer

ShortstripDBIbonds

Bondpadredistribu on

ROIC

.5mm

8mmBumpbonds

Threshold Noise

Short strip tier

Long strip tier

Noise

Threshold

5 layer stack:

1. Top Sensor

2. Interposer

3. Top ROIC

4. Bot ROIC

5. Bottom sensor

3d integration of sensors and electronics · • all three 3d chips worked –vip and victr tested...

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