3d-integrated circuits: a focus on signal ...terrazon process with dbi & flip chips process...

1

1

3D-INTEGRATED CIRCUITS: A FOCUS ON SIGNAL INTEGRITY AND

ELECTROMAGNETIC COMPATIBILITY

Etienne SICARDINSA/DGEIUniversity of Toulouse31077 Toulouse - [email protected]

www.ic-emc.org

2

Cassoulet (heavy food)

Rugby (heavy efforts)

Airbus A380 (heavy airplane)

TOULOUSE - FRANCE

Founded in -120 B.C (heavy history)

Best place to study in France (2011 ranking)(heavy responsibility)

2

3

I. EMC ISSUES

II. EVOLUTION OF ICS AND CONSEQUENCE ON EMC

III. 3D IC TECHNOLOGY

IV. MEASUREMENT OF 3D-IC EMISSION AND

SUSCEPTIBILITY

V. MODELS FOR 3D-EMC SIMULATION

VI. DESIGN GUIDELINES FOR IMPROVED EMC

SUMMARY

4

I. EMC ISSUES

3

5

5 October 12

http://www.interferencetechnology.com > markets > news

GENERAL EMC ISSUES – ALL DOMAINS

6

Mobile phonePersonal entrainments

Safety systemsComponents

SUSCEPTIBILITY

EquipementsCarbon airplane

Boards

Radar

INDUSTRIAL PRESSURE

Control Systems

EMISSION

4

77 October 12

EMC AT IC LEVEL

WHEN EMC OF ICS STARTED?

• Until mid 90’s, IC designers had no consideration about EMC problems in their design..

• Starting 1996, automotive customers started to select ICs on EMC criteria

• Starting 2005, mobile industry required EMC in System in package

• Starting 2015, massive 3D integration will require careful EMC design

• “Urgent Need to Integrate EMC and Product Safety into Engineering Curriculum of Technical Universities”

8

10k

100k

1M

1996 2000 20021998 2004

GSM 14k

GPRS 64k

Year

2006

Bandwidth (bit/s)

2008

10M

100M

Average bandwidth

HSDPA 1.0 M

HSUPA 4 M

2010

LTE 20 M

UMTS 120 k

We are Here

Boundaries

2G(4.5 Billion users)

3G(1 Billion)

3G+(1 Billion)

4G(0.1 Billion)

3D-IC DRIVING FORCES

THE GIANT SCALE MOBILE PHONE INDUSTRY

2012

LTE-A 40 M

2014

5

9


4G REQUIRES 4 CAMERAS, 10+ PROCESSORS, GB MEMORY• Texas Instruments OMAP 5430 example• 3D Ics are used for memories and camera modules

• 2008 : “Why 3D?”• 2010 “”How 3D? • 2012 : “When 3D?”• …• 20xx : “Why 2D?”

10

EMC IN 3D-ICS

Georgia-Tech vision of SoC

10 October 12

From Georgia Tech 3D system packaging research http://www.prc.gatech.edu.

HOW TO ENSURE EM COMPATIBILITY OF THIS ..?

6

11

Emission and immunity levels (dB)

-40

-30

-20

-10

0

10

20

30

40

50

1 10 100 1000

Frequency (MHz)

Interference risk

Security margin Small margin

Immunity

Immunity

Emission

Emission

EMC MARGIN

MIXING EMISSION AND IMMUNITY LEVELS

FREESCALE « 3G phone in a package » using RCP technology

12

Why a margin

Domain Life time Margin

Aeronautics 30 years 40 dB

Automotive 15 years 20 dB

Mobile phone 1 year 0 dB

Margin depends on application

Acceptable noise level

Process variations

Measurement error

Ageing

Required noise level

Environment

Security

EMC MARGIN

LINK BETWEEN MARGIN AND APPLICATIONS

Ioff/Ion MOS 32-nm

PhD A. C. Ndoye, INSA, 2010

Immunity vs. ageing (LTOL)

7

13

dBµV

0

20

40

60

80

100

10 100 1000

FM GSMRF

EMC IS CRITERION FOR SELECTING IC SUPPLIERS

Supplier A

EMC compliant

Not EMC compliant

Customer's specified limit

LOW EMISSION = DIFFERENTIATOR

B

A

Supplier B

14

Thunderstorm impact

UNINTENTIONAL ELECTROMAGNETIC SOURCES

TV UHF

Radars

2-4G BS

1W

Frequency

1MW

1KW

1GW Weather Radar

3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz

Power

1mW

HF VHF UHF SHF xHF THF

3G

TV VHF

2G4G

• Fields radiated by electronic devices

• Continuous waves & pulsed waves

25m 25mm0.25m 2.5mm2.5m λλλλλλλλ/4 (ideal antenna)0.25mm

SUSCEPTIBILITY ISSUES

8

15

II. EVOLUTION OF IC TECHNOLOGY AND CONSEQUENCE ON EMC

16

Technology

Complexity

Packaging

2004

130nm

100M

Core+ DSP1 Mb Mem

Embedded

blocks

2006

90nm

250M

Core DSPs10 Mb Mem

2008

45nm

500M

Dual coreDual DSP RFGraphic Process.100 Mb MemSensors

2010

32nm

2G

Quad CoreQuad DSP 3D Image ProcCrypto processorReconf FPGA, Multi RF1 Gb Memories Multi-sensors

22nm

2012

7G

10 GIGA-DEVICE ICS

5nm

150 G

2020

?

HIGHER COMPLEXITY

9

17

HIGHER PARASITIC EMISSION

INCREASED SWITCHING DEVICE PERFORMANCES

Current drive

(mA/µm)

2.0

1.0

0.0

130 nm

1.5

0.5

45 nm65 nm 22 nm32 nm 17 nm

Technology node

Intrinsic performances

Strain

Gate material

90 nm

Strain to increase mobility

High K Metal Gate to increase field

effect

Tri-Gate for increasing drive

current and reducing leakage

18

Time

WHY TECHNOLOGY PROGRESSES INCREASE EMISSION

Time

• The current amplitude is a little reduced

• The switching is faster

The noise is increased

The noise is increased

New process

Volt

Old process

CurrentOld process

di/dt

New process

Vss

Vdd

t

iLV

∆∆=∆

t

iLV

∆∆=∆

HIGHER PARASITIC EMISSION

10

1919 October 12

INCREASED SUSCEPTIBILITY

100 mV margin

5.0

3.3

2.5

1.8

0.5µ 0.35µ 0.18µ 90n 65n

Technology

1.0

Supply (V)

1.2

45n

I/O supply

Core supply

32n

DECREASED NOISE MARGIN IN ICS

22n 17n130n

500 mV margin

Adapted from ITRS roadmap for semiconductors, 2011

20

3D-IC EMC CHALLENGES

20 October 12

J. Kim; IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC

BASIC EMC ISSUES IN 3D-ICS

11

21

III. 3D-IC TECHNOLOGY

22



MEMORIES AND IMAGERS

From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev.

12

23

3D-IC BENEFITS

3D TECHNOLOGY

Enables the integration of ics fabricated in different technologies : Cmos, CCD, SOI, sensors, MEMS

23 October 12

C. Bower, et. al., “High Density Vertical Interconnects for 3D Integration of Silicon ICs,” 56th ECTC, San Diego, 2006.

B. Aull, et. al., “Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes” IEEE SSCC 2006.

4µm viasBosch process

0.18µm SOI0.35 µm SOISensor

24

3D-IC TECHNOLOGY

24 October 12

TERRAZON PROCESS WITH DBI & FLIP CHIPS

Process accessible by CMC, CMP and MOSIS for academics, SME and industries

From CMP annual users meeting, “3D-IC Integration”, January 20th 2011, PARIS

Direct bond interconnect

13

25

3D-IC EXAMPLE

25 October 12

Development of 3D Integrated Circuits for HEP, R. Yarema, 2006

3D IC Pixel Electronics, the Next Challenge, R. Yarema, 2008

26

3D-IC EFFICIENCY

IMPROVED ELECTRONIC EFFICIENCY

• 3D reduces interconnect length > inductance effects

• 3D simplifies multiple supply voltage distribution

• 3D reduces package pin count

• More uniform, high density power delivery

26 October 12

J. Lu, “Monolithic 3D Power Delivery Using Dc-Dc Converter”, 3D Architecture Conference, October, 2006, Burlingame, CA.

14

27

3D-IC BENEFITS

DIE BONDING VS THROUGH SILICON VIA

27 October 12

EMC-3D Consortium Overview and CoO Model, Paul Siblerud, www.emc3d.org

Ω≈≈ 500 Cl

ZΩ≈≈ 2000 cL

Z

28

SIGNAL INTEGRITY IN 3D-ICS

28 October 12

A SIGNIFICANT DECREASE OF OVER/UNDERSHOOTS

2D 3D

Buffer 3-stage 1-stage

Pad Load 3-5 pF 1 pF

Interconnectcapa

5-20 pF 0.1-5 pF

Interconnectinductance

5-30 nH 0.1-2 nH

Current drive 10-100 mA 1-10 mA

HDI PCB

Stacked die bonding

3D TSV

15

29

SIGNAL INTEGRITY IN 3D-ICS

A SIGNIFICANT REDUCTION IN I/O COMPLEXITY

• Most Electrostatic Discharge, overstressprotections can be removed

29 October 12

Solder ballESD protection

Voltage translation and level shifers

30

POWER EFFICIENCY 3D-ICS

A BETTER POWER EFFICIENCY

• Shorter wires decrease the average parasitic inductance and resistance and decrease the number of repeaters needed for long wires.

• Capacitance is reduced if the dies are thinned (350 > 10-100 µm)

• The wire efficiency is improved by 10-100 %

• Power dissipation may be reduced by a factor of 2-10

30 October 12

T. Topol « Three-dimensional integrated circuits », Ibm Journal Research, 2006

Lili Zhou, "Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in 3D-Ics « , ICCD 2007

16

31

3D-IC INTERFACING

NO I/O STANDARDIZATION BETWEEN INTERFACES

• Cost-effective high-volume manufacturing will be difficult to achieve unless manufacturing standards are developed

• Identify and create new standards in 3D-ICs.

� Through silicon via size

� Interposer and die thickness

� Microbump dimensions

� Electrical behavior of I/Os

• No I/O standardization at present

• IBIS could play an important role for standard interfacing

31 October 12

From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev.

From ITRS RoadmapFrom http://www.semi.org/node/37306

32

IV. MEASUREMENT OF 3D-IC EMISSION & SUSCEPTIBILITY

17

33

3D-IC MEASUREMENT METHODS

33 October 12

IEC – International Electro-Technical Commission - www.iec.ch

International ElectrotechnicalCommission

169 technical committee

TC 4 : hydraulic turbinesTC 4 : hydraulic turbines

TC 20 : electric cablesTC 20 : electric cables

SC 46A : coaxial cables

SC 47A : integrated circuits


.

.

.

WG 9 : Test procedures and measurement methods for EMC of ICs

Members

USA

Japan

South Korea

Poland

England

Germany

France

Belgium

Italy

Netherlands


Secretary : Japan

Work Group

WG 2 : Digital integrated circuits

WG 4 : Interface integrated circuits

WG 7 : Advanced hybrid integrated circuits

WG 9 : Test procedures and measurement methods for EMC of ICs

WG 2 : Digital integrated circuits

Members

USA

Japan

South Korea

Poland

England

Germany

France

Belgium

Italy

Netherlands

Worldwide expert meetings, defending national industrial approaches

3434 October 12


STANDARD EMC TEST BOARD – 2D/3D DOES NOT MAKE DIFFERENCE

100 mm

MetallizationVia row

DUT

Additional holes

Top layer – DUT layer

Bottom layer – Additional component

Connections of IC by 0.25mm vias

Ground plane under IC Connection

layer 1 to 4 by 0.8mm vias

Decoupling of supply on this part of ground plane

Tinned

Layer 1 – Ground

Layer 2 – Power supply

Layer 3 – Signal

Layer 4 – Ground and/or signal

18

35

STANDARD IC EMISSION MEASUREMENT

METHODS - IEC 61 967

IEC 61967-2(TEM : 1 GHz)

IEC 61967-3/6(Near-field Scan, 5 GHz)

IEC 61967-4(1/150 Ω, 1 GHz)

IEC 61967-8(Mini-stripline)

IEC 61967-7(Mode Stirred Chamber : 18 GHz)

Ext : IEC 61967-2(GTEM 18 GHz)


36

3D-IC Measurement Methods

36 October 12

IEC 61 967 – 2 “TEM/GTEM CELL” -8 “IC-STRIPLINE”

� Upper IC may play the role of shielding

� Upper IC is closer to septum

� 45 mm for TEM, 6.7 mm to Stripline

Low SSN on top High SSN on top

TEM/GTEM cross-section

IC-Stripline cross-section

TEM/GTEM cross-section

45 mm

6,7 mm

19

37


37 October 12

IEC 61 967 – 3/6 “NEAR-FIELD SCAN”

� Combining laser and high-precisionNFS may lead to precise 3D investigations

� But lower die stack shielded by upperdies

� Faster 3D scan: may use « cube-probe » (isotropic measurement of Hx, Hz, Hz) for Hmax measurement

D. Baudry, PhD report, ESIGELEC, Univ Rouen, 2005

38


38 October 12

IEC 61 967 – 4 “1/150 Ω METHOD”

Sub-component

Passive Distribution Network

IB

Immunity behavioral

PDN

Σ,Π

Silicon Die

IA

Internal activity

PDN Embedded passives

PDN package

Other silicon die

Other sub-component

Integrated Circuit

� Each die would have a built-in 1 Ωprobing for IC emissioncharacterization

1 Ω die 11 Ω die 2

1 Ω die 3

20

3939 October 12

IEC 62132-3(Bulk Current Injection : 1 GHz)

IEC 62132-4(Direct Power Inj 1GHz)

IEC 62132-2(TEM/GTEM)

IEC 62132-5(WBFC 1 GHz)

IEC 62132-6(LIHA : 10 GHz)

IEC 62132-8 Mini Stripline

INTERNATIONAL STANDARDS FOR IC SUSCEPTIBILITY MEASUREMENTS


40


40 October 12

3D-RELEVANT IMMUNITY MEASUREMENT

METHODS (RESEARCH)

Skate-probe On-chip sampling

Analog JTAG DPI+NFS

21

41


41 October 12

IEC 62 132 – 3 “BCI METHOD”� BCI is 5 Kg, 20 cm

diameter

� 3D-IC is 3g, 25 mm square

3D-IC connected to a bus (CAN, LIN..) or sensors ?

42


42 October 12

IEC 62 132 – 4 “DPI METHOD”

Sub-component


IB

Immunity behavioral

PDN

Σ,Π

Silicon Die

IA

Internal activity


PDN package

Other silicon die

Other sub-component

Integrated Circuit

� Each die would have built-in injection probes for IC immunity characterization

to die 1to die 2

to die 3

http://ecubes.epfl.ch

22

43


43 October 12

IEC 62 132 – 4 “DPI METHOD”

� Extension of injection to 10 GHz « x-DPI » concept

PCB Board level

1 mm

Interposer level

100 µm

DC

RFITSV to IC

DPI Capa (10-100 pF)

DC Polarization and Isolation resistance(or embedded L)

44


44 October 12

IEC 62 132 – 2 “TEM/GTEM METHOD”, - 8 “MINI-STRIP LINE”

� Mini strip-line efficient for injection (3%)

� Canonical field

F. Klotz, « IC-Stripline, new method for emission and immunity », EMC Compo 2009

EMC test board

Strip line cross-section

6.7 mm

23

45


45 October 12

SKATE PROBE PRINCIPLES� Investigate “what-if

3D” by manual positioning in X,Y,Z

� Avoid the cost of 3D prototypes

� Ensure EMC prior to 3D-IC design

Characterization of the aggressor NF emission

The aggressor SkateProbedesign

SkateProbe validation

Measurement of the coupling between the SkateProbe and the victim

Victim component

An Innovative Methodology for Evaluating Multi-Chip EMC in Advanced 3G Mobile Platforms, S. Akue Boulingui, IEEE EMC Symp Austin, 2009

RF Stage Numerical part

Power management

MemoryProcessor3G Transceiver3G PA

3G LNA

2G PAs

2G Transceiver

46


46 October 12

SKATE PROBE – CASE STUDY� Aggressor : 3G Power amplifier

� Victim : 3G transceiver

24

47


47 October 12

PA_SkateProbeSkateProbe signal Transceiver

Power amplifier

Desired signalUSB conexion

Power meter

-6 dB

Coupler

SKATE PROBE – CASE STUDY� 3D positioning of the

aggressor above the victim� SNR characterization

with/without disturbances

-8,5

-7,5

-6,5

-5,5

-4,5

2110 2120 2130 2140 2150 2160 2170

SN

R (

dB)

SNR targetWith

disturbance

SNR referencecurve

Frequency (MHz)

SN

R (

dB)

50 Ω load

11 mm

14 mm

48


48 October 12

ON-CHIP SAMPLING � Simple Sample/Hold analog cell

to probe voltages & currents

Sampling command

S/H cell

Signal to measure

+

_

Output amplifier

Sampled dataHigh impedance

probe

Attenuator

Sensor

S. Ben Dhia, “On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations”, IEEE Trans. Instr. Meas, 2012

Enrique LAMOUREUX, PhD2006, INSA Toulouse, France

25

49


49 October 12

ON-CHIP SAMPLING

� Setup with DPI

� Clock and Data trig the IC under test

Switching

High frequency Low frequency

Switching Switching

50


50 October 12

-50

-40

-30

-20

-10

0

10

20

30

40

1,E+06 1,E+07 1,E+08 1,E+09

Frequency (Hz)

EM

I tra

nsfe

r fun

ctio

n (d

B V

/W) Simulation

Measurement

ON-CHIP SAMPLING� Extraction of the

transfer function of the IC, strongly dependant on F

� On-chip sensing bandwidth linked to technology

� 2 GHz 0.25µm, 20 GHz 22 nm

S. Ben Dhia, “On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations”, IEEE Trans. Instr. Meas, 2012

26

51

3D IC Measurement Methods

51 October 12

ANALOG JTAG� Usable with digital JTAG

boundary scan� Adds analog testability –

both controllability and observability

� Eliminates large area needed for analog test points

Agrawal, “IEEE 1149.4 JTAGAnalog Test Access Port and Standard”, VLSI Test Lecture 2001

52

3D IC MEASUREMENT METHODS

52 October 12

COMBINED DPI AND NFS� Idea: inject in direct

power injection and measure in Near-field scan

� Tool for observing the 3D-IC from outside

� May help investigating the coupling paths and build accurate models

A. Alaeldine “Analysis of the Propagation of EM Disturbances Inside Integrated Circuits Using DPI and NFS”, IEEE EMC Austin 2009

DPI off

DPI on

27

53

V. MODELS FOR EMC SIMULATION

54

DESIGN

Architectural Design

Design EntryDesign Architect

FABRICATION

EMC compliant

EMC SimulationsCompliance ?

GO

NO

EMC VALIDATED BEFORE FABRICATION

Design Guidelines

Tools

Training

EMC-AWARE DESIGN CYCLE

28

55

IEC STANDARD MODEL APPROACH

1. ICEM-CE - Conducted RF emission

2. ICEM-RE - Radiated RF emission

4. ICIM-CI - Conducted RF immunity

4. ICIM-RI - Radiated RF immunity

www.iec.ch

IEC 62 433 – EMISSION (ICEM) AND IMMUNITY (ICIM) MODELS

Conducted mode models in industrial use

56

GENERIC FLOW

Core – I/O ModelPackage ModelTest board ModelTest bench Model

EMC Model for the circuit

Electrical Simulation

Simulated Emission spectrum

EMC SIMULATION FLOW AT IC LEVEL

The DUT is isolated on a simple EMC board to minimize modeling effort

29

57

Core Model

Probe Model Analog Time-Domain

Simulation

Fourier Transform

Conversion to Win-SPICE

dB vs Freq (log)conversionPackage

Model

Test board Model

INFINEON TRICORE™ - TEM CELL MODEL

EMISSION CASE STUDY

Capacitance coupling to the TEM cell

0A

0.5A

1.0A6.6ns (150MHz))

Core current model

58

Infineon TriCore™ measurement/simulation comparisons

Measure� Correct envelop

� Reasonable match

� Simulation 15 dB above measurement starting 700 MHz

� Manual fit leads to 5 dB max difference

Radiated noise in GTEM cell (dBµV)

INFINEON TRICORE™ - TEM CELL EMISSION

EMISSION CASE STUDY

Predictive model

30

5959

Sub-component


IB

Immunity behavioral

PDN

Σ,Π

Silicon Die/ Intellectual property

IA

Internal activity


PDN package

Other silicon die

Other sub-component

Integrated Circuit (ICEM, ICIM)

Integrated Circuit (ICEM, ICIM)

Sub-component

Silicon die

DOWN-SCALING TO MULTI-DIES

EMISSION MODEL OF MULTI-DIE 2D/3D ICS

One-die to multi-die model

60

3D-IC MODEL

THROUGH SILICON VIA MODEL

60 October 12

J. Kim; IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC

• TSV diameter : 55 µm• TSV SiO2 thickness : 0.5 µm

Low loss upto 30 GHz

31

61

3D-IC MODEL

61 October 12

Resistance and Capacitance values in mΩ and fF

M. B. Healy, “A Study of Stacking Limit and Scaling in 3D ICs: An Interconnect Perspective”, 2009 Electronic Components and Technology Conference


Large capacitance for large & long TSVs

6262


3D-IC MODEL


PAK et al.: Pdn impedance modeling and analysis of 3D TSV IC, IEEE Trans on components, packaging, and manuf. tech, Feb 2011

• Tall 3D Ics lead to significant L. • Crosstalk should also be considered

32

63

3D-IC DELAY MODELING

DELAY VS. INTER-DIE OPTIONS

63 October 12

F2F F2B

J. Roulard, Electrical Characterization and Impact on Signal Integrity of New Basic Interconnection Elements inside 3D Integrated Circuits, 2011 Electronic Components and Technology Conference

• Stacking strategy may reduced delay by 80%

64

3D-IC EMC PERFORMANCES

EMISSION PREDUCTION

64 October 12

• Long bonding act as antennas

• l/4 eq. 5-15 GHz • Important conducted,

radiated noise

µC

mem

Package

• Mem acts as a shielding• Very fast µC/mem

exchanges• Still important antenna• Medium emission

(conducted/radiated)

• Shielding of mem, µC• No antenna effect• TSV may act as a load and

slow down mem/µc exchanges

• Low emission

33

65

3D-IC MODEL

EMISSION PREDICION

E. Sicard, Wu Jianfei www.ic-emc.org “3D-IC Case study”

• 3D-TSV technology may reduce emission by 30 dB vs PCB, and 15 dB vs die stack with wire bonding

-30 dB

Frequency

Radiated emission (dBµV)

66

3D-IC POWER INTEGRITY

POWER INTEGRITY MODELING

66 October 12

Young-Joon Lee, Co-design of Reliable Signal and Power Interconnects in 3D Stacked Ics, 2009

Maximum power noise (mV) with varied settings

Power delivery by specific TSVs

34

67

3D-IC POWER INTEGRITY

67 October 12

Voltage drop as a function of time. The dynamic noise as a function of TSV dimension in µm (40 x 40 TSV)


POWER INTEGRITY MODELINGCore placement strategy has a direct impact on voltage drops

68

Package

IB

PDN

Package PDN

Silicon die

IC PDN Internal BehaviourIB

External pins

ICIM – immunity modelPackage

Monitoring of the failure

PDN = Passive Distribution Network

detection

RF disturbance Coupling path

Close to ICEM-CE

Close to ICEMAdd Diodes (camp, back-to-back, ESD, EOS)

New!

IEC 62433-4 – “ICIM CONDUCED IMMUNITY”

IEC STANDARD MODEL APPROACH

Based on ICEM, add non-linearities

35

69

• 16 bit micro-controller• Direct power injection• Input buffer aggression• Sinusoidal mode• Simulation criterion:

Logical change of input buffer

From A. Boyer’s PhD, INSA, 2007

IMMUNITY SIMULATION

S12X CASE STUDY – DPI ON AN INPUT

70

VI. DESIGN RULES FOR IMPROVED EMC

36

71

Why: because inductance is a major source of resonanceWhere is the inductance: in each conductor, worst is far from ground

L=1 nH/mm

DESIGN RULES

GUIDELINE 1 : REDUCE THE INDUCTANCE

ICIC

VDD

VSS

VSS

VDD

72

Multiple VDD, VSS Tools required to forecast strong di/dt effects

DESIGN RULES

GUIDELINE 2 : PLACE VDD/VSS CLOSE TO STRONG DI/DT

37

73

• to reduce current loops that provoke magnetic field• to increase decoupling capacitance that reduces fluctuations

DieLeadLead

current

Added contributions

Canceled contributions

EM wave

GUIDELINE 3 : PLACE VDD-VSS CLOSE

DESIGN RULES

Added

Canceled (-20 dB)

74

Correct Fail

9 I/O ports

DESIGN RULES

GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS

• To reduce current loops• To reduced LC effects

BGA examples

3D-TSV examples

J. S. Pak “PDN Impedance Modeling and Analysis of 3D TSV IC », IEEE Transactions on components, packaging, and manuf. Tech. vol. 1, no. 2, Feb. 2011

Both correct

38

75

Poor design:x 5 mode switching noise

© Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com

DESIGN RULES

GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS FPGA CASE STUDY

7610/22/2012 Graduate Student Meeting on Electronic

Engineering - Tarragona76

• 1nF added close to the core• More than 15 dB noise reduction• Selected areas:

• Logic Core• Charge pump (FLASH)• Fast I/Os (DDRx)

B.Vrignon CESAME test-chip IEEE Trans EMC 2006

GUIDELINE 5 : PLACE ON-CHIP DECOUPLING CLOSE TO STRONG DI/DT

DESIGN RULES

39

77

Filler-cap at the output buffer area

High speed port

High speed port

Protection circuit

VDD

VSS

Core

Pad

Protection circuit

Filler-cap

GUIDELINE 5 : PLACE ON-CHIP DECOUPLING CLOSE TO STRONG DI/DT

DESIGN RULES

78

GUIDELINE 6 : ADD JIITTER ON THE CLOCK

© B. Vrignon, Freescale SAS

-8 dB

DESIGN RULES

40

79

RC filtering works both for emission and immunity

Ali ALAELDINE , PhD Eseo France

Susceptibility level

Normal Core

Isolated Core

RC Code

GUIDELINE 7 : ADD RC FILTERING TO ISOLATE NOISE

DESIGN RULES

Frequency (MHz)

80

� « Zero » emission designs

� cancel all fields

� negligeable external di/dt

� De-synchronized parts

� « Zero » susceptibility designs

� Clamp, filter

� Protect, shield by design, materials

� Defensive core

supply

Critical sensor

Critical decision

� Reduce frequency� Reduced VDD� Smart capa management� Redundancy

RFI, ESD, EOS, EFT

Detector

… and Why Not?INNOVATIVE EMC …

FUTURE

41

81

CONCLUSION

82

• Higher complexity and frequencies, technology scale down make EMC more and more challenging

• EMC is still investigated late in the design flow

• Mature standard measurement methods dedicated to ICs

• New standards for EMC modeling at IC level

• Good prediction of emission and susceptibility up to 2 GHz for 2D-ICs• 3D-ICs speed up signal propagation, consumes less power• Many 3D-IC technologies co-exist, no standard• New EMC Challenges in 3D due to die-die proximity, protection

simplification• Signal Integrity closely linked to via technologies • PDN & Power Integrity linked to 3D choices• Standard and new measurement methods available• EMC impacted by positioning, designs, filtering and assembly options• 3D-EMC still in infancy stage, a huge room for innovation

CONCLUSION

42

83

Standards www.iec.ch

• IEC 61967, 2001, Integrated Circuits emissions

• IEC 62132, 2003, integrated circuits immunity

• IEC 62433, 2006, Integrated Circuit Model

• IEC 62215, 2009Transcient immunity

Books

www.springeronline.com

REFERENCES

www.emccompo.org

Workshops

EMC Compo in Dec 13Nara

Japan

Tools

www.ic-emc.org

Melbourne, Australia from 20 – 23 May 2013www.apemc13.org

84

Merci beaucoup pour votre attentionThank you very much for listing

• The audience• The IEEE Solid State Circuits Society, Switzerland• The IEEE Electron Device Society, Switzerland• The IEEE Student Branch, EPFL• Wladyslaw Grabinski• Lucian Barbut

3d-integrated circuits: a focus on signal ...terrazon process with dbi & flip chips process...

Documents