3625f-high efficiency 2-cell supercap charger

7/27/2019 3625f-High Efficiency 2-Cell Supercap Charger

1/16

LTC3625/LTC3625-1

3625f

Typical applicaTion

FeaTures DescripTion

1A High Efciency 2-CellSupercapacitor Charger

with Automatic Cell

Balancing

The LTC3625/LTC3625-1 are programmable supercapaci-tor chargers designed to charge two supercapacitors inseries to a xed output voltage (4.8V/5.3V or 4V/4.5Vselectable) rom a 2.7V to 5.5V input supply. Automaticcell balancing prevents overvoltage damage to eithersupercapacitor while maximizing charge rate. No balancingresistors are required.

High eciency, high charging current, low quiescent cur-rent and low minimum external parts count (one inductor,one bypass capacitor at VINand one programming resistor)make the LTC3625/LTC3625-1 ideally suited or small ormactor backup or high peak power systems.

Charging current/maximum input current level is pro-grammed with an external resistor. When the input supply isremoved and/or the EN pin is low, the LTC3625/LTC3625-1automatically enter a low current state, drawing less than1A rom the supercapacitors.

The LTC3625/LTC3625-1 are available in a compact12-lead 3mm 4mm 0.75mm DFN package.

1A SCAP Charger

applicaTions

n High Efciency Step-Up/Step-Down Charging o TwoSeries Supercapacitors

n Automatic Cell Balancing Prevents CapacitorOvervoltage During Charging

n Programmable Charging Current Up to 500mA(Single Inductor), 1A (Dual Inductor)

n VIN = 2.7V to 5.5Vn Selectable 2.4V/2.65V Regulation per Cell (LTC3625)n Selectable 2V/2.25V Regulation per Cell (LTC3625-1)n Low No-Load Quiescent Current: 23An IVOUT, IVIN < 1A in Shutdownn Low Prole 12-lead 3mm 4mm DFN Package

n Servers, RAID Systems, Mass Storage, High CurrentBackup Supplies

n Solid State Hard Drivesn Wireless Power Metersn

High Peak Power Boosted SuppliesL, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks andThinSOT is a trademark o Linear Technology Corporation. All other trademarks are the propertyo their respective owners.

Charging Two 2:1 Mismatched Supercapacitors

TIME (SECONDS)

0

VOLTAGE

(V)

2

4

6

1

3

5

40 80 120 160

3625 TA01b

200200 60 100 140 180

VOUT

VMID

CTOP = 50FCBOT = 100FRPROG = 61.9kCTL = 0

VSEL = 0

VOUT

SW1

SW2

VMID

PGOODPFO

LTC3625

3.3H CTOP 0.1F

CBOT 0.1F

VOUT4.8V

3625 TA01a

10F

VIN2.7V TO 5.5V

VIN

PROG

61.9k

PFIENCTLVSEL

3.3H


2/16

LTC3625/LTC3625-1

3625f

pin conFiguraTionabsoluTe MaxiMuM raTings

VIN, VOUT (Transient) t < 1ms,Duty Cycle < 1% .......................................... 0.3V to 7V

VIN, VOUT, VMID, PGOOD,CTL, PROG, PFI, PFO ................................... 0.3V to 6VEN, VSEL........................................... 0.3V to VIN + 0.3VVOUT Short-Circuit Duration ............................. IndeniteIPGOOD, IPFO............................................................50mAIPROG........................................................................1mAIVIN, ISW1, ISW2, IVOUT (Note 2) ...................................3AOperating Junction Temperature Range(Notes 3, 4) ............................................ 40C to 125CStorage Temperature Range .................. 65C to 125C

(Note 1)

12

11

10

9

8

7

1

2

3

4

5

6

SW2

VOUT

VMID

PGOOD

PFO

PFI

SW1

VIN

CTL

VSEL

EN

PROG

TOP VIEW

13GND

DE PACKAGE12-LEAD (4mm s 3mm) PLASTIC DFN

TJMAX = 125C, JA = 43C/W

EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3625EDE#PBF LTC3625EDE#TRPBF 3625 12-Lead (4mm 3mm) Plastic DFN 40C to 125C

LTC3625EDE-1#PBF LTC3625EDE-1#TRPBF 36251 12-Lead (4mm 3mm) Plastic DFN 40C to 125C

LTC3625IDE#PBF LTC3625IDE#TRPBF 3625 12-Lead (4mm 3mm) Plastic DFN 40C to 125C

LTC3625IDE-1#PBF LTC3625IDE-1#TRPBF 36251 12-Lead (4mm 3mm) Plastic DFN 40C to 125C

Consult LTC Marketing or parts specied with wider operating temperature ranges. *The temperature grade is identied by a label on the shipping container.Consult LTC Marketing or inormation on non-standard lead based nish parts.

For more inormation on lead ree part marking, go to: http://www.linear.com/leadree/For more inormation on tape and reel specications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics The l denotes the specifcations which apply over the ull operatingjunction temperature range, otherwise specifcations are at TA = 25C. VIN = 3.6V, RPROG = 143k, unless otherwise specifed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Input Voltage Range l VIN(UVLO) 5.5 V

VIN(UVLO) Input Undervoltage Lockout(VIN Rising)

VSEL = VIN (LTC3625)VSEL = 0V (LTC3625)VSEL = 0V or VIN (LTC3625-1)

l

l

l

2.82.532.53

2.92.632.63

3.02.732.73

VVV

Input UVLO Hysteresis 100 mV

VOUT(SLEEP) Charger Termination Voltage VSEL = VIN (LTC3625)VSEL = 0V (LTC3625)

VSEL = VIN (LTC3625-1)VSEL = 0V (LTC3625-1)

l

l

l

l

5.24.7

4.43.9

5.34.8

4.54.0

5.44.9

4.64.1

VV

VV

Recharge Hysteresis Below VOUT(SLEEP) 135 mV

VTOP,VBOT Maximum Voltage Across Either othe Supercapacitors Ater Charging

VSEL = VIN, VOUT = 5.3V (LTC3625)VSEL = 0V, VOUT = 4.8V (LTC3625)VSEL = VIN, VOUT = 4.5V (LTC3625-1)VSEL = 0V, VOUT = 4V (LTC3625-1)

l

l

l

l

2.72.452.3

2.05

2.752.52.352.1

VVVV

Maximum Supercapacitor OsetAter Charging

CTL = 0VCTL = VIN

10050

180120

mVmV


3/16

LTC3625/LTC3625-1

3625f

elecTrical characTerisTics The l denotes the specifcations which apply over the ull operatingjunction temperature range, otherwise specifcations are at TA = 25C. VIN = 3.6V, RPROG = 143k, unless otherwise specifed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IVIN Input Operating Current,ISW1 = ISW2 = 0A, No Switching

CTL = VIN, VMID = 1.5V, VOUT = 2.5V (Boost Only)CTL = VIN, VMID = 1.5V, VOUT = 3.5V (Buck Only)

CTL = 0, VMID = 1.5V, VOUT = 2.5V (Buck and Boost)

135275

365

200400

530

AA

A

Input Sleep Current VIN = 5.5V, VOUT = 5.4VVIN = 3.6V, VOUT = 5.4V

238

3515

AA

Input SD Current VOUT = 0V 0 1 A

IVOUT VOUT SD Current VOUT = 5.4V 0 1 A

VOUT Sleep Current VOUT = 5.4V, VIN = 3.6V, EN = VINVOUT = 5.4V, VIN = 5.5V, EN = VIN

171

252.5

AA

VPROG PROG Servo Voltage VOUT = 3.5V, VMID = 1.5V l 1.17 1.2 1.23 V

hPROG Ratio o Measured IPROG Current toIBUCK Programmed Current

118,000

IBUCK Programmed Buck Charge Current RPROG = 143k (Note 5)RPROG = 71.5k (Note 5)

0.881.76

0.991.98

1.102.20

AA

IMAX Maximum Programmed ChargeCurrent

RPROG = 0 (Fault Condition) (Note 5) 1.98 2.65 3.31 A

VMID(GOOD) VMID Voltage Where the BoostRegulator is Enabled

1.35 V

VMID(GOOD) Hysteresis 150 mV

VTRICKLE VOUT Voltage Above Which BoostRegulator Will Exit Trickle ChargeMode and Enter Normal ChargeMode

VOUT Rising VMID V

VTRICKLE Falling Hysteresis 50 mV

IPEAK(BUCK) Buck Charge Current Peak 1.1 IBUCK A

IVALLEY(BUCK) Buck Charge Current Valley 0.9 IBUCK A

IPEAK(BOOST) Boost Charge Current Peak VOUT = 3V, VMID = 2V (Note 5)

VOUT = 1V, VMID = 2V (Note 5)

1.59 2.12

200

2.65 A

mAIVALLEY(BOOST) Boost Charge Current Valley VOUT = 3V, VMID = 2V

VOUT = 1V, VMID = 2V1.41 1.88

02.35 A

mA

Maximum Boost Valley Time VOUT = 1V, VMID = 2V 6.5 s

RPMOS PMOS On-Resistance 120 m

RNMOS NMOS On-Resistance 100 m

ILEAK SW Pin Leakage Current or SW1,SW2

EN = 0V 1 A

VPFI PFI Falling Threshold l 1.17 1.2 1.23 V

PFI Hysteresis 15 mV

IPFI Pin Leakage Current or PFI Pin 0 30 nA

Logic (EN, CTL, VSEL, PGOOD, PFO)

VIL Input Low Logic Voltage EN, CTL, VSEL Pins l 0.4 V

VIH Input High Logic Voltage EN, CTL, VSEL Pins l 1.2 V

IIL, IIH Input Low, High Current or CTL CTL 1 A

RPD EN Pin Pull-Down Resistance 4.5 M

VSEL Pin Pull-Down Resistance EN = VIN 4.5 M

VOL Output Low Logic Voltage PGOOD, PFO Pins; Sinking 5mA l 70 200 mV

IOH Logic High Leakage Current PGOOD, PFO Pins; Pin Voltage = 5V 1 A

PGOOD Rising Threshold VOUT as a Percentage o Final Target 90 92.5 95 %

PGOOD Hysteresis VOUT as a Percentage o Final Target 3 %


4/16

LTC3625/LTC3625-1

3625f

Typical perForMance characTerisTics

Buck Output Current vs RPROG

Sleep Current vs VIN

PROG Voltage and PFI FallingThreshold vs Temperature

Buck Current Limitsvs Temperature

TA = 25C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT, LTC3625 unless otherwise specifed.

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition or extended periods may aect devicereliability and lietime.

Note 2: The LTC3625/LTC3625-1 internal switches are guaranteed tosurvive up to 3A o peak current. Internal current limits will restrict peakcurrent to lower levels.

Note 3: The LTC3625/LTC3625-1 are tested under pulsed load conditionssuch that TJ TA. The LTC3625E/LTC3625E-1 are guaranteed to meetspecications rom 0C to 85C junction temperature. Specications overthe 40C to 125C operating junction temperature range are assured bydesign, characterization and correlation with statistical process controls.The LTC3625I/LTC3625I-1 are guaranteed over the 40C to 125Coperating junction temperature range.

The junction temperature (TJ in C) is calculated rom the ambienttemperature (TA in C) and power dissipation (PD in Watts) according tothe ormula:

TJ

= TA

+ (PD

JA

)

where JA (in C/W) is the package thermal impedance.

Note 4: This IC includes overtemperature protection that is intended toprotect the device during momentary overload conditions. The maximumrated junction temperature will be exceeded when this protection is active.Continuous operation above the specied maximum operating junctiontemperature may impair device reliability or permanently damage thedevice.

Note 5: Measurements are tested with CTL = 0V.

VIN (V)

2.7 3.10

CURRENT

(A)

10

25

IVOUT

IVIN

3.5 4.3 4.7

3625 G01

5

20

15

3.9 5.1 5.5

VOUT = 4.8VVSEL = 0V

TEMPERATURE (C)

40 25 10 5 20 35 50 65 80 95 110 125

VPROG(

V) 1.205

1.210

1.215

3625 G02

1.195

1.180

1.220

1.200

1.190

1.185

VIN = 3.6VRPROG = 143k

TEMPERATURE (C)

40 25 10 5 20 35 50 65 80 95 110 125

CURRENT(mA)1050

1100

1150

1200

3625 G03

950

800

1000

900

850

IPEAK

IVALLEY

VIN = 3.6VRPROG = 143k

RPROG (k)

0

IBUCK(mA)

1000

2000

3000

500

1500

2500

100 200 300 400

3625 G04

500500 150 250 350 450

VIN = 3.6VVMID = 2VCTL = 0VIPROG

CLAMPED

Charge Termination Errorvs Temperature

TEMPERATURE (C)

40

OFFSET(%)

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.095

3625 G13

5 35 65 125801025 20 50 110

VIN = 3.6V

SLEEP THRESHOLD

WAKE THRESHOLD

Input and Output Sleep Currentsvs Temperature

TEMPERATURE (C)

40

CURRENT

(A)

25

20

15

10

5

095

3625 G14

5 35 65 125

IVIN

801025 20 50 110

VIN = 3.6VVSEL = 3.6V

LTC3625-1 IVOUTVOUT = 4.5V

LTC3625 IVOUTVOUT = 5.3V


5/16

LTC3625/LTC3625-1

3625f

Buck Input Power vs RPROG Buck Efciency vs IBUCK

RPROG (k)

0

INPUTPOWER(W)

8

7

6

5

4

3

2

1

0400

3625 G05

100 200 300 50035050 150 250 450

VIN = 5.5VVMID = 2.65VCTL = 0VVSEL = VIN

IPROGCLAMPED

IBUCK (mA)

200

EFFICIENCY(%)

80

90

100

2200

3625 G06

70

60

75

85

95

65

55

50700 1200 1700

VIN = 3.6VVMID = 2VCTL = 0V

Typical perForMance characTerisTicsTA = 25C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT, LTC3625 unless otherwise specifed.

Buck Input Power vs VMID

VMID (V)

0.20

INPUTPOWER(W)

1

2

3

4

6

0.6 1.0 1.4 1.8

3625 G07

2.2 2.6

5

VIN = 5.5VVSEL = VINCTL = 0

RPROG = 71.5k

RPROG = 143k

RPROG = 286k

Buck Efciency vs VMID Buck Output Current vs VMID

VMID (V)

0.240

EFFICIENCY(%)

50

60

70

80

100

0.6 1.0 1.4 1.8

3625 G08

2.2 2.6

90

VIN = 5.5VVSEL = VINCTL = 0

RPROG = 71.5k

RPROG = 143k

RPROG = 286k

VMID (V)

0.20

IBUCK(mA)

500

1000

1500

0.6 1.0 1.4 1.8

3625 G09

2.2

2000

2500

250

750

1250

1750

2250

2.6

VIN = 5.5V

VSEL = VINCTL = 0

RPROG = 71.5k

RPROG = 143k

RPROG = 286k

Boost Input Current vs VTOP

VTOP (V)

1.5

IBOOST(mA) 1500

2000

2500

0 1.0 2.5

3625 G10

1000

500

01.0 0.5 0.5 1.5 2.0

VIN = 3.6VVMID = 2.5V

VTOP = VOUT VMIDCTL = 0

NORMAL OPERATION

VOUTTRICKLE

CHARGEOPERATION

RFET vs TemperatureBoost Efciency vs VTOP

VTOP (V)

1.5

EFFICIENCY(%)

60

70

80

1.5

3625 G11

50

40

0.5 0.51.0 2.00 1.0 2.5

30

20

90

VIN = 3.6VVMID = 2.5VVTOP = VOUT VMIDCTL = 0

NORMAL OPERATION

VOUT TRICKLECHARGE OPERATION

TEMPERATURE (C)

40 25 10 5 20 35 50 65 80 95 110 125

PMOS

RDS(ON)()

NMOSRDS(O

N)()

0.15

3625 G12

0

0.20

0.10

0.05

0.20

0.05

0.25

0.15

0.10

VIN = 2.7VVIN = 5.5V

PMOS

NMOS

Charge Time vs RPROG

RPROG (k)

0

TIME

(SECONDS)

400

350

300

250

200

150

100

50

0400

3625 G15

100 200 300 50035050 150 250 450

SINGLEINDUCTOR

APPLICATION

DUALINDUCTOR

APPLICATION

VIN = 3.6VVSEL = 3.6VVOUT INITIAL = 0VCTOP = CBOT = 10F

IPROGCLAMPED


6/16

LTC3625/LTC3625-1

3625f

Typical perForMance characTerisTicsTA = 25C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT, LTC3625 unless otherwise specifed.

SW1 (Pin 1): Switch Pin or the Buck Regulator. Externalinductor connects between SW1 pin and VMID.

VIN (Pin 2): Input Voltage Pin. Bypass to GND with a 10For larger ceramic capacitor.

CTL (Pin 3): Logic Input. CTL sets the charge mode o theLTC3625/LTC3625-1. A logic high at CTL programs the partto operate with a single inductor; a logic low programsthe part to operate with two inductors. In the 2-inductorapplication the capacitor stack will charge approximatelytwice as quickly. CTL is a high impedance input and mustbe tied to either VIN or GND. Do not foat.

VSEL (Pin 4): Logic Input. VSEL selects the output volt-age o the LTC3625/LTC3625-1. A logic low at VSEL setsthe per-cell maximum voltage to 2.45V/2.05V (VOUT =4.8V/4.0V); a logic high sets the per-cell maximum volt-age to 2.70V/2.30V (VOUT = 5.3V/4.5V). When the part isenabled, VSEL has a 4.5M internal pull-down resistor; iEN is low, then VSEL is a high impedance input pin.

EN (Pin 5): Logic Input. Enables the LTC3625/LTC3625-1.Active high. Has a 4.5M internal pull-down resistor.

Charge Profle Into Matched

SuperCaps Charge Profle with CBOT > CTOP Charge Profle with CTOP > CBOT

pin FuncTions

PROG (Pin 6): Charge Current Program Pin. Connecting aresistor rom PROG to ground programs the buck outputcurrent. This pin servos to 1.2V.

PFI (Pin 7): Input to the Power Fail Comparator. This pinconnects to an external resistor divider between V

INand

GND. I this unctionality is not desired, PFI should betied to VIN.

PFO(Pin 8):Open-Drain Output o the Power-Fail Compara-tor. The part pulls this pin low i VIN is less than a valueprogrammed by an external divider. This pin is active lowin shutdown mode. I this unctionality is not desired PFOshould be let unconnected.

PGOOD (Pin 9): Logic Output. This is an open-drainoutput which indicates that VOUT has settled to its nalvalue. Upon start-up, this pin remains low until the outputvoltage, VOUT, is within 92.5% (typical) o its nal value.Once VOUT is valid, PGOOD becomes high impedance. IVOUT alls to 89.5% (typical) o its correct regulation level,PGOOD is pulled low. PGOOD may be pulled up throughan external resistor to an appropriate reerence level. Thispin is active low in shutdown mode.

TIME (SECONDS)

0

SINGLE

INDUCTOR

VOLTAGE

(V)

DUAL

INDUCTOR

VOLTAGE

(V)

0

2

4

120

3625 G16

6

4

20 40 60 80 100 140

2

0

6VOUT

VMID

VMID

VIN = 3.6V, VSEL = 3.6VRPROG = 143kCTOP = CBOT = 10F

VOUT

SINGLE INDUCTOR APPLICATION

DUAL INDUCTOR APPLICATION

TIME (SECONDS)

0

SINGLE

INDUCTOR

VOLTAGE

(V)

DUAL

INDUCTOR

VOLTAGE

(V)

0

2

4

200

3625 G17

6

4

50 100 150 250

2

0

6VOUT

VMID

VMID

VIN = 3.6V, VSEL = 3.6VRPROG = 143kCTOP = 10F, CBOT = 50F

VOUT



TIME (SECONDS)

0

SINGLE

INDUCTOR

VOLTAGE

(V)

DUAL

INDUCTOR

VOLTAGE

(V)

0

2

4

300

3625 G18

6

4

50 100 150 200 250 350

2

0

6VOUT

VMID

VMID

VOUT



VIN = 3.6V, VSEL = 3.6VRPROG = 143kCTOP = 50F, CBOT = 10F


7/16

LTC3625/LTC3625-1

3625f

pin FuncTions

VMID (Pin 10): Midpoint o Two Series Supercapacitors.The pin voltage is monitored and used, along with VOUT,to enable or shut down the buck and boost converters

during charging to achieve voltage balancing o the topand bottom supercapacitors.

VOUT (Pin 11): Output Voltage Pin. Connect VOUT to thepositive terminal o the top supercapacitor. The pin volt-age is monitored and used, along with VMID, to enable orshut down the buck and boost converters during charg-ing to achieve voltage balancing o the top and bottomsupercapacitors.

SW2 (Pin 12): Switch Pin or the Boost Regulator. Externalinductor connects between the SW2 pin and VMID. I CTLis logic high, then SW2 must be connected to SW1.

GND (Exposed Pad Pin 13): Ground. The exposed padmust be connected to a continuous ground plane onthe printed circuit board directly under the LTC3625/LTC3625-1 or electrical contact and to achieve ratedthermal perormance.

block DiagraM

8

+

PFO

7PFI

1.20V

4.44V/4.90V (LTC3625)3.7V/4.16V (LTC3625-1)

9

+

PGOOD

4VSEL

10VMID

THRESHOLDDETECTOR

5EN

3CTL

VMID_GOODSD_BUCK

6

13

2

PROG

MASTERLOGIC

OVERTEMPERATURESHUTDOWN 1.2V

+

+

GND

SW1

VIN

B

3625 BD

A

DSD_BOOST

REF/R PROGRAMMEDAVG OUTPUT CURRENT

SYNCHRONOUSBUCK CURRENT

REGULATOR

BUCK REGULATOR

BOOST REGULATOR

1

11

SW2

VOUT

C

2A AVGINPUT CURRENT

SYNCHRONOUSBOOST CURRENTREGULATOR

12

VMAXERVIN

VOUT


8/16

LTC3625/LTC3625-1

3625f

operaTion

The LTC3625/LTC3625-1 are dual cell supercapacitor char-gers. Their unique topology charges two series connectedcapacitors to a xed output voltage with programmable

charging current without overvoltaging either o the cells even i they are severely mismatched. No balancingresistors are required. The LTC3625/LTC3625-1 include aninternal buck converter between VIN and VMID to regulatethe voltage on CBOT (across the bottom capacitor) as wellas an internal boost converter between VMID and VOUT toregulate the voltage on CTOP(across the top capacitor). Theoutput current o the buck converter is user-programmedvia the PROG pin and the input current o the boost con-verter is set at 2A (typical).

Table 1 indicates the various unctions o the LTC3625/LTC3625-1 that can be digitally controlled.

Table 1. Digital Input Functions

PIN VALUE FUNCTION

CTL* 0 Part runs in 2-inductor application

1 Part runs in 1-inductor application

VSEL 0 4.8V/4.0V sleep threshold

1 5.3V/4.5V sleep threshold

EN 0 Part shuts down, VOUT becomes highimpedance

1 Part enables and regulates the output

*CTL pin must be hard tied to either V IN or GND.

VIN Undervoltage Lockout (UVLO)

An internal undervoltage lockout circuit monitors VIN andkeeps the LTC3625/LTC3625-1 disabled until VIN risesabove 2.90V/2.63V (typical) i VSEL is high or 2.63V/2.63V(typical) i VSEL is low. Hysteresis on the UVLO turns othe LTC3625/LTC3625-1 i VIN drops by approximately100mV below the UVLO rising threshold. When in UVLO,only current needed to detect a valid input will be drawnrom V

INand V

OUT.

Buck Converter

The buck converter regulates a user-programmed averageoutput current given by:

I hV

RBUCK PROG

PROG

= .1 2

where hPROG = 118,000 (typical).

The buck converter regulates the current hysteretically byswitching on the buck PMOS until a peak current limit isreached and then turning on the buck NMOS until a valley

current limit is reached. In the single inductor applicationthe boost NMOS is used in conjunction with the buckNMOS to increase eciency at high currents. The orwardcurrent limit is set to 1.1 IBUCK (typical) and the valleycurrent limit is set to 0.9 IBUCK (typical). Because o thismethod o regulation, overcurrent limit and reverse-currentlimit protection is automatically provided. The LTC3625/LTC3625-1 will continue to regulate its programmed cur-rent even into a grounded output.

In ault conditions where the PROG pin is shorted to ground,

or RPROG is conductive enough to program IBUCK to operateoutside o specication, the current out o the PROG pinwill be clamped to 22.5A (typical) and IBUCK will be set to2.65A (typical). I input current limit is not a concern, thePROG pin may be grounded to minimize charge times.

Boost Converter

The boost converter regulates a xed average input currento 2A (typical). The current is regulated hysteretically byswitching on the boost NMOS until the peak current limit o2.12A (typical) is reached, and turning on the boost PMOS

until the valley current limit o 1.88A (typical) is reached.In the single inductor application the buck NMOS is usedin conjunction with the boost NMOS to increase eciency.Because o this method o regulation, overcurrent limit andreverse-current limit protection is automatically provided.

In normal operation VOUT will increase with VMID so VOUTshould never be below VMID. In the case where there is areverse voltage on CTOP due to a aulty precondition or alarge load on the output, the boost converter will operatein trickle charge mode. In this mode the boost PMOS

gate will remain high and instead allow the SW2 node toincrease until SW2 VMAX + 1V to allow a higher reversevoltage across the inductor, and the current is ramped downto 0mA. This will result in a less ecient charge deliverythrough the PMOS. To keep dissipation low, IPEAK is limitedto 200mA (typical). In this mode the discharge phase isterminated i it lasts longer than 6.5s (typical).

The boost converter is disabled i VMID alls below theVMID(GOOD) hysteresis threshold o 1.2V (typical).


9/16

LTC3625/LTC3625-1

3625f

operaTion

Single Inductor Operation

With the CTL pin tied to VIN the LTC3625/LTC3625-1 will

operate in single inductor mode. In this mode the sameinductor serves in the power path or both the buck andthe boost converters. Thus, the buck converter and boostconverter will never run simultaneously.

Under certain conditions with a single inductor, a smallamount o current can fow rom the supercapacitors to VINwhen the boost charger is active. A 25mA load is requiredon VIN to prevent the VIN supply rom being pumped toa higher voltage while the boost is active. This minimumload is not needed in the two inductor application and itis also not needed when the charger is disabled.

A typical charge cycle or a ully discharged capacitor stackwill proceed as ollows:

1. The buck converter will turn on and regulate its outputcurrent ramping hysteretically between 1.1 IBUCK and0.9 IBUCK until the VMID(GOOD) threshold is met (1.35Vtypical).

2. Once the VMID(GOOD) threshold is reached, the boostconverter will turn on and regulate its input currentramping hysteretically between 2.12A and 1.88A untilV

MIDalls below the V

MID(GOOD)hysteresis threshold

(1.2V typical).

3. Phases 1 and 2 will alternate until VOUT is approximately2.4V. When VTOP (equal to VOUT VMID) is approximately50mV > VMID, the boost regulator will turn o and thebuck regulator will turn on. Likewise, when VMID isapproximately 50mV > VTOP, the boost regulator willturn on and the buck regulator will turn o.

4. Phase 3 will continue until VOUT has reached its pro-grammed output voltage. Once this happens, the partwill enter sleep mode and only minimal power will beconsumed (see the Electrical Characteristics table).

5. I the supercapacitors sel discharge or an external loadcause the output to drop by more than 135mV (typical),then the LTC3625/LTC3625-1 will exit sleep mode andbegin charging the appropriate supercapacitor.

In all cases whenever either o the converters is shutdown, it will switch to its appropriate discharge phase(NMOS on or the buck and PMOS on or the boost) until

the inductor current reaches 0mA. This optimizes chargedelivery to the output capacitors.

Charge time is dependant on the programmed buck outputcurrent as well as the value o the supercapacitors beingcharged. For estimating charge proles in the single induc-tor application, see the Typical Perormance Characteristicsgraph Charge Time vs RPROG.

The eective average VOUT reerred charge current canbe approximated as:

I IA

I ACHARGE BUCK BOOST

BUCK

+

0 52

2.

where

BOOST is the boost converter eciency, which istypically about 85% (see the Typical Perormance Char-acteristics graph Boost Eciency vs VTOP).

Seen another way, this is the maximum steady-state loadthe part can support without losing VOUT regulation.

Dual Inductor Operation

With the CTL pin tied to GND, the LTC3625/LTC3625-1will operate in dual inductor mode. In this mode twoinductors will serve as the power path or the buck andthe boost converters. This will allow both the buck andthe boost converter to run simultaneously. As a result, thetotal charge time will be greatly reduced at the cost o anadditional board component.

A typical charge cycle or a ully discharged capacitor stackwill proceed as ollows:

1. The buck converter will turn on and regulate its outputcurrent ramping hysteretically between 1.1 IBUCKand 0.9 IBUCK until the VMID(GOOD) threshold is met(1.35V typical).

2. Once the VMID(GOOD) threshold is reached, the boostconverter will turn on and regulate its input currentramping hysteretically between 2.12A and 1.88A. Thebuck converter will continue to run at the same time. Insome cases (IBUCK ~


10/16

LTC3625/LTC3625-1

0

3625f

operaTion

converter will turn o. Once VMID has again risen abovethe VMID(GOOD) threshold, the boost converter will bere-enabled. In the case where VOUT < VMID, the boost

converter will operate in trickle charge mode until VOUTexceeds VMID (see Boost Converter).

3. During phase 2, i CBOT exceeds its individual maximumthreshold voltage (2.45V/2.05V typical i VSEL is lowor 2.7V/2.3V typical i VSEL is high) or i VTOP exceedsVBOT by more than 50mV (typical), then the appropri-ate converter will turn o until the capacitor has allenbelow its hysteresis threshold (2.40V/2V typical i VSELis low and 2.65V/2.25V typical i VSEL is high or thebuck converter or VTOP < VMID 50mV typical or the

boost converter).4. Once VOUT has reached its programmed output voltage,

the part will enter sleep mode, and only minimal powerwill be consumed (see the Electrical Characteristicstable).

5. I the supercapacitors sel discharge or an external loadcause the output to drop by more than 135mV (typical),then the LTC3625/LTC3625-1 will exit sleep mode andbegin recharging the supercapacitor stack.

In all cases, whenever either o the converters is shut

down, it will switch to its appropriate discharge phase(NMOS on or the buck and PMOS on or the boost) untilthe inductor current reaches 0mA. This optimizes chargedelivery to the output capacitors.

Charge time is dependent on the programmed buck out-put current as well as the value o supercapacitors beingcharged. For estimating charge proles in the dual inductorapplication, see the Typical Perormance Characteristicsgraph Charge Time vs RPROG.

The eective average VOUT reerred charge current, while

both converters are continuously active, can be approxi-mated as:

I I AV

VCHARGE BUCK BOOST

MID

OUT

0 5 1 1 2.

And, while both supercapacitors are in balance and VMIDis above the VMID(GOOD) threshold as:

ICHARGE 0.5 IBUCK BOOST

where BOOST is the boost converter eciency which istypically around 85% (see the Typical Perormance Char-acteristics graph Boost Eciency vs VTOP).

Seen another way this is the maximum steady-state loadthe part can support without losing VOUT regulation.

PGOOD PIN

The PGOOD pin is an open-drain output used to indicatethat VOUT has approached its nal regulation value. PGOODremains active low until VOUT reaches 92.5% o its regula-tion value at which point it will become high impedance.I VOUT alls below 89.5% o its regulation voltage aterPGOOD has been asserted, PGOOD will once again pull

active low. PGOOD is an open-drain output and requiresa pull-up resistor to the input voltage o the monitoringmicroprocessor or another appropriate power source.PGOOD is pulled active low in shutdown or input UVLO.

Power-Fail Input Comparator

The PFI/PFO pins provide an input ailure notication tothe user. The PFI pin is a high impedance input pin thatshould be tied to a resistive divider rom VIN. PFO is anopen-drain output and requires a pull-up resistor to theinput voltage o the monitoring microprocessor or anotherappropriate power source. When PFI is above 1.2V, PFO ishigh impedance and will be pulled up through the externalresistor. I PFI drops below 1.2V, PFO will be pulled lowindicating a power ailure. This allows the user to programany desired input power ailure indication threshold. Thereis 15mV o hysteresis on the PFI pin. I this unctionalityis not desired the PFI pin should be tied to V IN. PFO ispulled active low in shutdown or input UVLO

Shutdown Operation

When the EN pin is pulled low the LTC3625/LTC3625-1 areput into shutdown. In this case, all o the active circuitry ispowered down and there will be less than 1A o leakagecurrent rom both VIN and VOUT. This allows the input tobe present or absent as well as the capacitor stacks to beully charged or discharged in shutdown without leakagebetween VIN, VOUT and GND.


11/16

LTC3625/LTC3625-1

3625f

applicaTions inForMaTion

Programming Charge Current/Maximum Input Current

The CBOT charge current is programmed with a single

resistor connecting the PROG pin to ground. The programresistor and buck output current are calculated using theollowing equation:

R hV

IPROG PROG

BUCK

= .1 2

where hPROG= 118,000 (typical). Excluding quiescent cur-rent, IBUCK is always greater than the average buck inputcurrent. An RPROG resistor value o less than 53.6k willcause the LTC3625/LTC3625-1 to enter overcurrent protec-tion mode and proceed to charge at 2.65A (typical).

The eective buck input current can be calculated as:

II V

VVIN

BUCK

BUCK

MID

IN

=

where BUCK is the buck converter eciency (see theTypical Perormance Characteristics graph Buck Eciencyvs VMID).

Output Voltage Programming

The LTC3625/LTC3625-1 have a VSEL input pin thatallows the user to set the output threshold voltage toeither 4.8V/4.0V or 5.3V/4.5V by orcing a low or high atthe VSEL pin respectively. In the single inductor applicationthe chip will balance the supercapacitors to within 50mV(typical) o each other, resulting in a possible 25mV oover/undercharge per cell. In the dual inductor applicationthe chip will balance the supercapacitors to within 100mV(typical) o each other, resulting in a possible 50mV oover/undercharge per cell.

Thermal Management

I the junction temperature increases above approximately150C, the thermal shutdown circuitry automatically de-activates the output. To reduce the maximum junctiontemperature, a good thermal connection to the PC boardis recommended. Connecting the exposed pad (Pin 13) othe DFN package to a ground plane under the device on twolayers o the PC board, will reduce the thermal resistanceo the package and PC board considerably.

VIN Capacitor Selection

The style and value o capacitors used with the LTC3625/

LTC3625-1 determine input voltage ripple. Because theLTC3625/LTC3625-1 use a step-down switching power sup-ply rom VIN to VMID, its input current waveorm containshigh requency components. It is strongly recommendedthat a low equivalent series resistance (ESR) multilayerceramic capacitor be used to bypass VIN.

Tantalum and aluminum capacitors are not recommendedbecause o their high ESR. The value o the capacitor onVIN directly controls the amount o input ripple or a givenIBUCK. Increasing the size o this capacitor will reduce theinput ripple.

Multilayer ceramic chip capacitors typically have excep-tional ESR perormance. MLCCs combined with a tightboard layout and an unbroken ground plane will yieldvery good perormance and low EMI emissions. There areseveral types o ceramic capacitors available, each havingconsiderably dierent characteristics. For example, X7Rceramic capacitors have the best voltage and temperaturestability. X5R ceramic capacitors have higher packingdensity but poorer perormance over their rated voltageand temperature ranges. Y5V ceramic capacitors have

the highest packing density, but must be used with cau-tion because o their extreme non-linear characteristic ocapacitance verse voltage.

The actual in-circuit capacitance o a ceramic capacitorshould be measured with a small AC signal as is expectedin-circuit. Many vendors speciy the capacitance versusvoltage with a 1VRMS AC test signal and as a result,overstate the capacitance that the capacitor will presentin the application. Using similar operating conditions asthe application, the user must measure or request romthe vendor the actual capacitance to determine i the

selected capacitor meets the minimum capacitance thatthe application requires.

Inductor Selection

Many dierent sizes and shapes o inductors are avail-able rom numerous manuacturers. Choosing the rightinductor rom such a large selection o devices can beoverwhelming, but ollowing a ew basic guidelines willmake the selection process much simpler.


12/16

LTC3625/LTC3625-1

3625f


The buck and boost converters are designed to work withinductors over a wide range o inductances. Choosing ahigher valued inductor will decrease operating requen-

cies, while a lower valued inductor will increase requencybut also increase peak current overshoot/undershoot. Formost applications a 3.3H inductor is recommended. Tomaximize eciency, choose an inductor with a low DCresistance. Choose an inductor with a DC current ratingat least as large as the maximum IPEAK the application willsee according to the specications table to ensure that theinductor does not saturate during normal operation. I thesingle inductor application is used, make sure to size theinductor or the higher o buck or boost peak currents.

Dierent core materials and shapes will change the size/cur-rent and price/current relationship o an inductor. Toroidor shielded pot cores in errite or Permalloy materialsare small and do not radiate much energy, but generallycost more than powdered iron core inductors with similarelectrical characteristics. Inductors that are very thin orhave a very small volume typically have much higher coreand DCR losses, and will not give the best eciency. Thechoice o which style inductor to use oten depends moreon the price versus size, perormance and any radiatedEMI requirements than on what the LTC3625/LTC3625-1

amily requires to operate.Table 2 shows several inductors that work well with theLTC3625/LTC3625-1 regulators. These inductors oer a

good compromise in current rating, DCR and physicalsize. Consult each manuacturer or detailed inormationon their entire selection o inductors.

Supercapacitor Selection

The LTC3625/LTC3625-1 are designed to charge super-capacitors o values greater than 0.1F per cell. In general,lower capacitance cells have higher ESRs, thereore lowercharge currents should be used to help reduce sleepmodulation towards the end o a charge cycle. In general,the ESR o a supercapacitor cell should not exceed:

ESRmV

IBUCK

100

where 100mV is the sleep threshold hysteresis. Highercapacitance cells typically have lower ESRs and canthereore be charged with higher currents. Typically, theLTC3625/LTC3625-1 are designed to charge supercapaci-tors with values up to 100F, but higher capacitance cellscould be used at the expense o greater charge time.Table 3 shows several supercapacitors that work well withthe LTC3625/LTC3625-1.

Printed Circuit Board Layout Considerations

In order to be able to deliver maximum current under allconditions, it is critical that the exposed pad on the backsideo the LTC3625/LTC3625-1 package be soldered to the PC

Table 2. Inductor Manuacturers

MANUFACTURER PART NUMBER INDUCTANCE (H) CURRENT (A) DCR (m) SIZE (mm)

Coiltronics DR73-3R3-R 3.3 3.0 20 7 7

Coilcrat MSS7341-332NL 3.3 3.2 20 7 7

Vishay IHLM2525CZER3R3M11 3.3 6.5 26 6.5 6.9

Sumida CDRH6D28P-3RON 3.0 3.0 24 7 7

TOKO B1077AS-3RON 3.0 3.3 30 7.6 7.6

Table 3. Supercapacitor Manuacturers

MANUFACTURER PART NUMBER VALUE (F) OPERATING VOLTAGE (V) MAXIMUM ESR (m) SIZE (mm)

Cooper Bussmann B1860-2R5107-R 100 2.5 20 18 60

Illinois Capacitor 107DCN2R7M 100 2.7 10 22 45

NESS Capacitor ESHSR-0100C0002R7 100 2.7 9 22 45

Tecate TPLS-100//22 X 45F 100 2.7 9 22 45

Maxwell BCAP120P250 120 2.5 2.5 26 51


13/16

LTC3625/LTC3625-1

3625f


board ground. Failure to make thermal contact betweenthe exposed pad on the backside o the package and thecopper board will result in higher thermal resistances.

Furthermore, due to its potentially high requency switch-ing circuitry, it is imperative that the input capacitor,inductors, and output bypass capacitors be as close tothe LTC3625/LTC3625-1 as possible, and that there be anunbroken ground plane under the IC and all o its externalhigh requency components. High requency currents, suchas the VIN and VOUT currents on the LTC3625/LTC3625-1,tend to nd their way along the ground plane in a myriad opaths ranging rom directly back to a mirror path beneaththe incident path on the top o the board. I there are slits or

cuts in the ground plane due to other traces on that layer,the current will be orced to go around the slits. I highrequency currents are not allowed to fow back throughtheir natural least-area path, excessive voltage will buildup and radiated emissions will occur. There should be agroup o vias under the grounded backside o the pack-age leading directly down to an internal ground plane. Tominimize parasitic inductance, the ground plane shouldbe on the highest possible layer o the PC board.

Any board resistance between inductor(s) and the posi-tive terminal o CBOT will add to the capacitors internal

ESR. Likewise, any resistance between the VOUT pinand the positive terminal o CTOP will add to its internalESR. Any added resistance to the capacitors will reducethe eective charging eciency. In the case o CBOT this

resistance can be kelvined out by a dedicated voltagesense trace rom the VMID pin to a point halway betweenthe bottom plate o CTOP and the top plate o CBOT. In the

case o CTOP, however, it is even more critical to keep anyresistance in the connection to a minimum. Excessiveseries resistance may cause the part to duty cycle in andout o sleep or prematurely shut down the boost, due tothe voltage seen at the part being equal to VOUT + IOUT ESR. Likewise the CBOTsupercapacitor should be providedwith a low impedance contact to the ground plane withan unbroken, low impedance, path back to the backsideo the LTC3625/LTC3625-1 package.

When laying out the printed circuit, the ollowing check-

list should be used to ensure proper operation o theLTC3625/LTC3625-1.

1. Are the bypass capacitors at VIN and VOUT as close aspossible to the LTC3625/LTC3625-1? These capacitorsprovide the AC current to the internal power MOSFETsand their drivers. Minimizing inductance rom thesecapacitors to the LTC3625/LTC3625-1 is a top priority.

2. Are the CBOTbypass capacitor and the power inductor(s)closely connected? The () terminal o the CBOT bypasscapacitor returns current to the GND plane, and then

back to CIN.3. Keep sensitive components away rom the SW pins.

4. Keep the current carrying traces rom VOUT to CTOP andthe inductors to CBOT to a minimum.

Typical applicaTions

450mA Charge Current 1-Inductor Application

VOUT

VMID

SW2

SW1

R371.5k

LTC3625-1

PROG GND

*25mA MINIMUM LOAD REQUIRED ON VIN

C2 0.1F

C3 0.1F

VOUT

4.0V/4.5V

3625 TA03

C110F

R1287k

R2100k

VIN*

2.7V TO 5.5VV

IN

VIN

VINENCTLVSELPGOODPFO

PFI

L1 3.3H


14/16

LTC3625/LTC3625-1

3625f


Solar Powered SCAP Charger with MPPT

VOUT

SW1

SW2

VMID

GND

CTL

EN

PFI

VSEL

GND

R3143k

LTC3625

PROG

L2 3.3H

C21F

C31F

3625 TA04

C110F

VINL1 3.3H

+

LT1784CS5V+

V

1

R5174k

R210.0k

C4390F16V

D3SOLAR PANEL6.0V OPEN CIRCUIT4.4V MPP

D21.2V

C510nF

R126.7k

R410k

D1CMSH3-40

C6100pF

2

5

3

4

+

VOUT

SW1

SW2

VMID

GND

PFO

CTL

5V

EN

PFI

VSEL

GND

R3143k

LTC3625

PROG

L13.3H

C2100F

Q1Si4421DY

Q2Si4421DY

C3100F

C110F

VIN

R2100k

R1287k

VIN

GND

CTL

SENSE

GATE

STAT

LTC4412

VIN1

VIN2

VOUT1

FB1

ITHM1

FB2

ITHM2

GND

GND

VOUT2

LTM4616

R4470k

R54.78k

R610k

3625 TA05

C7100F

C6100F

1.8V

C8100F

C522F

5V Power Ride-Through


15/16

LTC3625/LTC3625-1

3625f

Inormation urnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed or its use. Linear Technology Corporation makes no representa-tion that the interconnection o its circuits as described herein will not inringe on existing patent rights.

package DescripTionDE Package

12-Lead Plastic DFN (4mm 3mm)(Reerence LTC DWG # 05-08-1695)

4.00 p0.10(2 SIDES)

3.00p

0.10(2 SIDES)

NOTE:1. DRAWING PROPOSED TO BE A VARIATION OF VERSION

(WGED) IN JEDEC PACKAGE OUTLINE M0-2292. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS

3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEWEXPOSED PAD

1.70 p 0.10

0.75 p0.05

R = 0.115TYP

R = 0.05TYP

2.50 REF

16

127

PIN 1 NOTCHR = 0.20 OR0.35 s 45oCHAMFER

PIN 1TOP MARK

(NOTE 6)

0.200 REF

0.00 0.05

(UE12/DE12) DFN 0806 REV D

3.30 p0.10

0.25 p 0.050.50 BSC

2.50 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.20 p0.05

0.70 p0.05

3.60 p0.05

PACKAGEOUTLINE

1.70 p 0.05

3.30 p0.05

0.50 BSC0.25 p 0.05


VOUT

SW1

SW2

CTL

EN

GND

VSELVMID

LTC3625

PROG

L2 3.3H

C1100F

* M1IRF7424

UVDETECTOR

*EXPOSED PAD TOBE CONNECTED TO ATHERMAL PAD ISOLATEDFROM THE SYSTEM GROUND

FDS3672VIN

DC-A

64LT1737 FLYBACK

2

GND

12V

10

L1 3.3H

L4 3.3H

L3 3.3H

L6 3.3H

L5 3.3H

C2100F

R1143k

VOUT

CTL

EN

GND

VSEL

LTC3625

PROG

C3100F

VIN

C4100F

R2143k

VOUT

CTL

EN

GND

VSEL

LTC3625

PROG

C5100F

VIN

C6100F

R3143k

FDS3672

LTC4355

IDEAL DIODE

DC/DC

LTM4601A

VIN VOUT

GND GND

1.8V

GND

DC-B

7

11

DC-C

8

12

LT1737

*

SW1

SW2

VMID

SW1

SW2VMID

12V Power Ride-Through


16/16

LTC3625/LTC3625-1

3625f

Linear Technology CorporationLT 0710 PRINTED IN USA

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC3203/LTC3203B/LTC3203B-1/LTC3203-1

500mA Low Noise High Eciency Dual ModeStep-Up Charge Pumps

VIN: 2.7V to 5.5V, 3mm 3mm 10-Lead DFN Package

LTC3204/LTC3204B-3.3/LTC3204-5

Low Noise Regulating Charge Pumps Up to 150mA Output Current (LTC3204-5), Up to 50mA Output Current(LTC3204-3.3)

LTC3221/LTC3221-3.3/LTC3221-5

Micropower Regulated Charge Pump Up to 60mA Output Current

LTC3225/LTC3225-1 150mA Supercapacitor Charger Programmable Supercapacitor Charger Designed to Charge TwoSupercapacitors in Series to a Fixed Output Voltage (4.8V/5.3V Selectable)rom a 2.8V/3V to 5.5V Input Supply. Automatic Cell Balancing Prevents

Overvoltage Damage to Either Supercapacitor. No Balancing Resistors areRequired.

LTC3240-3.3/LTC3240-2.5 Step-Up/Step-Down Regulated Charge Pumps Up to 150mA Output Current

LT3420/LT3420-1 1.4A/1A Photofash Capacitor Charger withAutomatic Top-O

Charges 220F to 320V in 3.7 Seconds rom 5V, VIN: 2.2V to 16V,ISD < 1A, 10-Lead MS Package

LT3468/LT3468-1/LT3468-2

1.4A/1A/0.7A, Photofash Capacitor Charger VIN: 2.5V to 16V, Charge Time = 4.6 Seconds or the LT3468 (0V to 320V,100F, VIN = 3.6V), ISD < 1A, ThinSOT

TM Package

LTC3484-0/LTC3484-1/LTC3484-2

1.4A/0.7A/1A, Photofash Capacitor Charger VIN: 1.8V to 16V, Charge Time = 4.6 Seconds or the LT3484-0 (0V to 320V,100F, VIN = 3.6V), ISD < 1A, 2mm 3mm 6-Lead DFN Package

LT3485-0/LT3485-1/LT3485-2/LT3485-3

1.4A/0.7A/1A/2A Photofash Capacitor Chargerwith Output Voltage Monitor and IntegratedIGBT

VIN: 1.8V to 10V, Charge Time = 3.7 Seconds or the LT3485-0 (0V to 320V,100F, VIN = 3.6V), ISD < 1A, 3mm 3mm 10-Lead DFN Driver

LT3750 Capacitor Charger Controller Charges Any Size Capacitor, 10-Lead MS Package

LT3751 Capacitor Controller with Regulation Charges Any Size Capacitor, 4mm 5mm QFN-20 Package

LTC4425 Supercapacitor Charger with Current-LimitedIdeal Diode

CC/CV Linear Charger or 2-Cell Supercapacitor Stack rom a Li-Ion/Polymer Battery, USB Port or a 2.7V to 5.5V Current-Limited Supply,3mm 3mm DFN-12 and MSOP-12E Packages

Minimum External Component Application (500mA Charge Current)

VOUT

SW1

SW2

VMID

LTC3625

PROG GND

L13.3H C2 0.1F

VOUT4.8V/5.3V

C3 0.1F

*25mA MINIMUM LOAD REQUIRED ON VIN

3625 TA02

C1

10F

NCNC

VIN*2.7V TO 5.5V

VIN

PFICTLENVSELPGOODPFO

3625f-high efficiency 2-cell supercap charger

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