[3.5em]12th international satisfiability modulo theories …smtcomp.sourceforge.net › 2017 ›...
TRANSCRIPT
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12th InternationalSatisfiability Modulo Theories
Competition
SMT-COMP 2017
Matthias Heizmann (co-organizer)Giles Reger (co-organizer)
Tjark Weber (chair)
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Outline
I Main changes over last competitionI Benchmarks with ’unknown’ statusI Logics with algebraic data-types
AUFBVDTLIA, AUFDTLIA, QF DT, UFDT, UFDTLIA
I Unsat-core Track
I Statistics and selected results of competition
I Short presentation of solversBoolector, COLIBRI, CVC4, SMTInterpol, veriT, Yices
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SMT-COMP – Procedure
SMT-LIBusers
SMT-LIB benchmarkscurated by
Clark Barrett,Pascal Fontaine,Cesare Tinelli,
Christoph Wintersteiger
SMT solverdevelopers
StarExecmaintained by
Aaron Stump
Competition results
submitbenchmarks
uploadsolvers
uploadbenchmarks
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Solvers, Logics, and Benchmarks
I 15 teams participated
I Solvers:
Main track
Application track
Unsat-core track
19 2 non-competitive
4 2 non-competitive
2 2 non-competitive
I Logics:
Main track
Application track
Unsat-core track
40 5 experimental
14
39
I Benchmarks:
Main track
Application track
Unsat-core track
256973
5971
114233
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StarExec
Cluster of machines at the University of Iowa.
Hardware:
I Intel Xeon CPU E5-2609 @ 2.4 GHz, 10 MB cache
I 2 processors per node, 4 cores per processor
I Main memory capped at 60 GB per job pair
Software:
I Red Hat Enterprise Linux Server release 7.2
I Kernel 3.10.0-514, gcc 4.8.5, glibc 2.17
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Main Track
Main Track benchmark
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term0)
(assert term1)
(assert term2)
.
.
.(check-sat)
(exit)
any number of
set-info, declare-sort, define-sort,
declare-fun, define-fun, assert
in any order
← one single check-sat command
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Benchmarks with ’unknown’ status
Some benchmarks in SMT-LIB repository do not have a sat/unsatstatus.
Benchmarks with ’unknown’ status in SMT-COMP
2015
2016
2017
not used in competition
separate experimental track
included in Main Track
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New logics
Algebraic data-types
I defined in SMT-LIB 2.6 draft
I “experimental” this year (i.e., no winner determined)
benchmarks solvers
AUFBVDTLIA 1709 CVC4
AUFDTLIA 728 CVC4, vampire
QF DT 8000 CVC4
UFDT 4535 CVC4, vampire
UFDTLIA 303 vampire, CVC4
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Benchmarks with ’unknown’ status
Rules
I we trust the results of the solver(s)
I in case of disagreement we trust solvers that are sound onbenchmarks with known status
I if there is disagreement between otherwise sound solvers, weexclude the benchmark
Outcome
I There were 29 benchmarks with unknown status on whichsolvers disagreed on the result.
I On one benchmark (in BV) the corresponding solvers weresound on all benchmarks with known status.
I On 28 benchmarks (all in QF FP) the presumably wronganswers were given by unsound solvers.
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Benchmarks with ’unknown’ status
Rules
I we trust the results of the solver(s)
I in case of disagreement we trust solvers that are sound onbenchmarks with known status
I if there is disagreement between otherwise sound solvers, weexclude the benchmark
Outcome
I There were 29 benchmarks with unknown status on whichsolvers disagreed on the result.
I On one benchmark (in BV) the corresponding solvers weresound on all benchmarks with known status.
I On 28 benchmarks (all in QF FP) the presumably wronganswers were given by unsound solvers.
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Competition run of Main Track
I run all job pairs with 10 min timeout
I made preliminary results available
I rerun all job pairs that timed out with 20 min timeout
I made final results available on Friday (21st June)
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Main Track – Selected results – QF ABV
http://smtcomp.sourceforge.net/2017/results-QF ABV.shtml
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Main Track: Competition-Wide Scoring
Rank Solver Score (sequential) Score (parallel)
Z3 171.99 171.991 CVC4 161.38 161.762 Yices2 110.63 110.633 SMTInterpol 65.96 66.00
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Application Track
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Unsat-core Track
Motivation
I Important application of SMT-LIB
I One step towards verifiable proofs
History
2012
2016
2017
introduced}discontinued
reinstated as experimental track
“regular” track
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Unsat-core TrackMain Track benchmark
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term0)
(assert term1)
(assert term2)
.
.
.(check-sat)
(exit)
Solver input
(set-option :produce-unsat-cores true)
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert (! term0 :named y0))
(assert (! term1 :named y1))
(assert (! term2 :named y2))
.
.
.(check-sat)
(get-unsat-core)
(exit)
Solver output
unsat
(y0 y2)
timeout: 40min
Validation script
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term1)
(assert term2)———————–(assert term3)
.
.
.(check-sat)
(exit)
Validationsolver 1
Validationsolver 2
Validationsolver 3
Validationsolver 4
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
timeout: 5min each
Scoring scheme
n = # assert commands – # size of unsatisfiable core
e ={
1 result erroneous
0 otherwise
result erroneous if. wrong check-sat result or. unsat-core rejected by validating solvers
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Unsat-core TrackMain Track benchmark
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term0)
(assert term1)
(assert term2)
.
.
.(check-sat)
(exit)
Solver input
(set-option :produce-unsat-cores true)
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert (! term0 :named y0))
(assert (! term1 :named y1))
(assert (! term2 :named y2))
.
.
.(check-sat)
(get-unsat-core)
(exit)
Solver output
unsat
(y0 y2)
timeout: 40min
Validation script
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term1)
(assert term2)———————–(assert term3)
.
.
.(check-sat)
(exit)
Validationsolver 1
Validationsolver 2
Validationsolver 3
Validationsolver 4
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
timeout: 5min each
Scoring scheme
n = # assert commands – # size of unsatisfiable core
e ={
1 result erroneous
0 otherwise
result erroneous if. wrong check-sat result or. unsat-core rejected by validating solvers
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Unsat-core TrackMain Track benchmark
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term0)
(assert term1)
(assert term2)
.
.
.(check-sat)
(exit)
Solver input
(set-option :produce-unsat-cores true)
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert (! term0 :named y0))
(assert (! term1 :named y1))
(assert (! term2 :named y2))
.
.
.(check-sat)
(get-unsat-core)
(exit)
Solver output
unsat
(y0 y2)
timeout: 40min
Validation script
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term1)
(assert term2)———————–(assert term3)
.
.
.(check-sat)
(exit)
Validationsolver 1
Validationsolver 2
Validationsolver 3
Validationsolver 4
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
timeout: 5min each
Scoring scheme
n = # assert commands – # size of unsatisfiable core
e ={
1 result erroneous
0 otherwise
result erroneous if. wrong check-sat result or. unsat-core rejected by validating solvers
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Unsat-core TrackMain Track benchmark
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term0)
(assert term1)
(assert term2)
.
.
.(check-sat)
(exit)
Solver input
(set-option :produce-unsat-cores true)
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert (! term0 :named y0))
(assert (! term1 :named y1))
(assert (! term2 :named y2))
.
.
.(check-sat)
(get-unsat-core)
(exit)
Solver output
unsat
(y0 y2)
timeout: 40min
Validation script
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term1)
(assert term2)———————–(assert term3)
.
.
.(check-sat)
(exit)
Validationsolver 1
Validationsolver 2
Validationsolver 3
Validationsolver 4
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
timeout: 5min each
Scoring scheme
n = # assert commands – # size of unsatisfiable core
e ={
1 result erroneous
0 otherwise
result erroneous if. wrong check-sat result or. unsat-core rejected by validating solvers
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Unsat-core TrackMain Track benchmark
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term0)
(assert term1)
(assert term2)
.
.
.(check-sat)
(exit)
Solver input
(set-option :produce-unsat-cores true)
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert (! term0 :named y0))
(assert (! term1 :named y1))
(assert (! term2 :named y2))
.
.
.(check-sat)
(get-unsat-core)
(exit)
Solver output
unsat
(y0 y2)
timeout: 40min
Validation script
(set-logic ...)(set-info ...)
.
.
.(declare-sort ...)(define-sort ...)(declare-fun ...)(define-fun ...)(assert term1)
(assert term2)———————–(assert term3)
.
.
.(check-sat)
(exit)
Validationsolver 1
Validationsolver 2
Validationsolver 3
Validationsolver 4
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
sat/unknown/
unsat
timeout: 5min each
Scoring scheme
n = # assert commands – # size of unsatisfiable core
e ={
1 result erroneous
0 otherwise
result erroneous if. wrong check-sat result or. unsat-core rejected by validating solvers
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Unsat-core Track – Statistics245483job pairs
226501correct
check-sat responses
18982timeout/crash/
unknown
29incorrect
check-sat responses
92%8% ∼ 0.01%
30timeout/crash
226471get-unsat-core responses
∼0.01% ∼99.99%
8unsatisfiable core
rejected by validating solvers
226463unsatisfiable core validated
∼0.01%∼99.99%
I 19 times there was no consensus among the validating solvers( majority decision)
I 27525 (∼12%) times no independent validating solverapproved the correctness of the unsatisfiable core
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Unsat-core Track – Statistics245483job pairs
226501correct
check-sat responses
18982timeout/crash/
unknown
29incorrect
check-sat responses
92%8% ∼ 0.01%
30timeout/crash
226471get-unsat-core responses
∼0.01% ∼99.99%
8unsatisfiable core
rejected by validating solvers
226463unsatisfiable core validated
∼0.01%∼99.99%
I 19 times there was no consensus among the validating solvers( majority decision)
I 27525 (∼12%) times no independent validating solverapproved the correctness of the unsatisfiable core
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(Very) short presentations of
Solvers
that sent us slides.
Boolector, COLIBRI, CVC4, SMTInterpol, veriT, Yices
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Boolector at the SMTCOMP’17Aina Niemetz, Mathias Preiner, Armin Biere
Divisions
BV QF_BV QF_UFBV QF_ABV QF_AUFBV
Changes since 2016 (QF_BV)
� combination of prop.-based local search + bit-blasting now default
� experimental configuration with new SAT solver CaDiCaL
Major Improvements
� BV engine at SMT-COMP 2016 was a prototype implementation
−→ rewrite of BV engine with major improvements
1/1
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COLIBRI (QF_FP, QF_BVFP)I 776 errors due to a wrong backward propagation for fp.fmaI 1 error due to a mix between −0. and +0.
On the 308, non Wintersteiger benchmark of QF_FP in sec.
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CVC4 1.5
Clark Barrett (Stanford), Martin Brain (Oxford), Guy Katz (Stan-ford), Tim King (Google), Paul Meng (U Iowa), Aina Niemetz (Stan-ford), Mathias Preiner (Stanford), Andres Nötzli (Stanford), AndrewReynolds (U Iowa), Cesare Tinelli (U Iowa)
SMT 2017, July 22, 2017
1
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CVC4 1.5: Recent Developments
• A new theory of sets with cardinality and relations.
• A new theory of strings.
• A new theory of separation logic constraints.
• Support for many new heuristics for reasoning with quantifiers,including finite model finding.
• Improved heuristics for reasoning about non-linear arithmetic.
• Support for proofs for uninterpreted functions, arrays, bitvectors,and their combinations.
• Support for unsat cores.
• Native support for syntax-guided synthesis (sygus).
2
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Contact
We aim for CVC4 to be a versatile research platform for SMT and areopen to collaborators and contributors.
For more information:
• Contact one of the project leaders:• Clark Barrett [email protected]• Cesare Tinelli [email protected]
• Visit the website: cvc4.stanford.edu
3
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Quantifier FreeLinear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier FreeUninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
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Quantifier FreeLinear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier FreeUninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 31: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/31.jpg)
Quantifier FreeLinear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
mixed int/real
Quantifier FreeUninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 32: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/32.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 33: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/33.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpolsat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 34: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/34.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpolsat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 35: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/35.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 36: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/36.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 37: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/37.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 38: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/38.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
SMTInterpol
sat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 39: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/39.jpg)
Quantifier Free
Linear Arithmetic
y ≤ i + 1
i ≤ y
y − to int(y) < .3
Quantifier Free
Uninterpreted Functions
f (b) = v
f (a) 6= v
Quantifier FreeArrays
b = a〈i C v〉a[v ] = v
b[i ] ≥ i
f (i + y) = 2v
f (b) ≤ i
decides Satisfiability Modulo Theorycomputes Craig Interpolants
http://ultimate.informatik.uni-freiburg.de/smtinterpol
SMTInterpolsat
model
unsat
proof
unsat core
interpolants
b = a〈i C v〉a[v ] = v
f (a) 6= v⇒
i 6= v∨
f (b) 6= v⇒ ¬
f (b) = v
b[i ] ≥ i
f (b) ≤ i
![Page 40: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/40.jpg)
1/1
http://www.veriT-solver.org
Haniel Barbosa, Pascal Fontaine, Maximilian Jaroschek, MarekKosta, Thomas Sturm, and Vu Xuan Tung
University of Lorraine, CNRS, Inria, and LORIA (France), MPI Informatics andSaarland University (Germany), and JAIST (Japan)
What is new:I few improvements for quantifier handlingI fine-grained proofs for formula processingI veriT+raSAT+Redlog for supporting QF_[UF]NRAI veriT+Redlog for better handling (N|L)RA
Goals:I clean, small SMT for UF(N|L)IRA with quantifiers and proofsI for verification platforms (e.g. B, TLA+) and proof assistants
(e.g. Isabelle, Coq)
![Page 41: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/41.jpg)
Computer Science Laboratory, SRI International
Yices 2.6
Bruno Dutertre and Dejan JovanovicSRI International
SMTCOMP 2017Heidelberg, Germany
![Page 42: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/42.jpg)
Computer Science Laboratory, SRI International
Yices 2.6 in SMTCOMP 2017
Status
◦ No major change since last year◦ Supports linear and non-linear arithmetic, arrays, UF, bitvectors◦ Limited quantifier reasoning: ∃∀ fragments for bitvector, LRA◦ Includes two types of solvers: classic DPPL(T ) + MC-SAT
Entered in all the divisions that Yices supports
◦ Main track: Quantifier-free logics including linear and nonlinear arithmetic,bitvectors, and combination with UF and Arrays.◦ Application track: Same logics, except that the MC-SAT solver is not
incremental yet.
1
![Page 43: [3.5em]12th International Satisfiability Modulo Theories …smtcomp.sourceforge.net › 2017 › SMT-COMP-2017.pdf · 2017-09-05 · 12th International Satis ability Modulo Theories](https://reader035.vdocuments.site/reader035/viewer/2022081406/5f0ff8217e708231d446c9fe/html5/thumbnails/43.jpg)
Computer Science Laboratory, SRI International
What’s New
New Licence
◦ Yices 2 is now GPL
Distributions
◦ Prebuilt binaries + source tarfile at http://yices.csl.sri.com◦ Git repository on Github https://github.com/SRI-CSL/yices2
◦ Ubuntu/Debian package◦ Homebrew package for MacOS X
2
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Computer Science Laboratory, SRI International
What’s Next
MC-SAT Extensions
◦ Add support for incremental solving◦ Extends MC-SAT to bitvector problems
CDCL Solver
◦ New sat solver in progress
Miscellaneous
◦ Complete support for SMT-LIB 2.6◦ Fix some API issues
3
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Teams:
I Congratulations on your accomplishments!
I Thanks for your participation!