354 33 powerpoint-slides ch7

N. Senthil Kumar,M. Saravanan & S. Jeevananthan

© Oxford University Press 2013

Features and Interfacing of Programmable Devices for 8085 based

systems


Intel 8255 Programmable Peripheral interface

• Intel 8085 microprocessor can transfer data between external devices such as input devices and output devices through ports. Normally a register can act as an I/O port.

• But having a separate register and configuring them for input and output operation becomes difficult and tedious.

• So, Intel has designed a separate IC 8255 with the objective of interfacing input and output devices with Intel microprocessors.

• The 8255 is used on several of range of I/O cards that plug into an available slot in Personal Computer.


Introduction - 8255• The 8255 Programmable Peripheral Interface (PPI) is a

very popular and versatile input / output chip that can be easily programmed to function in several different configurations.

• This chip can do both digital input and output (DIO) from the processor in a preprogrammed manner.

• The common application of 8255 with 8085 include turning on a switch, to control movement by use of motors, to detect position etc.


Features of 8255• Each 8255 has three 8-bit TTL- compatible registers or

ports which will allow the programmers to control digital outputs of up to 24 bits or to read 24 bit inputs, or control a mixture of both input and output.

• The common features of Intel 8255 IC are as followed.• Three 8-bit ports named as Port A, Port B, Port C connected

to output pins.• Port C has been divided to two groups of 4 bits each as Port

C upper (PCU) and Port C lower (PCL). • Each of them can be programmed independently for Input

and output operation.


Features of 8255 contd..• All the ports can be programmed for simple I/O or

Handshake I/O for the data transfer in I/O modes.• Each Port C bit can be set/reset individually in BSR mode.• Port A bits and Port C Upper bits are grouped as Group A

(GA).• Port B bits and Port C Lower bits are grouped and called

as Group B (GB).


Block diagram of INTEL 8255


Block Diagram Description

• The block diagram of 8255 has three basic registers of 8 bits each and are called as Port A, Port B and Port C.

• The port A and upper 4 bits of Port C are grouped and called as Group A.

• Similarly, Port B and lower 4 bits of Port C are grouped as Group B.

• In addition to three registers A, B and C, there is another register called control register.

• The contents written into the control register decides the operating modes of the three parallel ports.


Block Diagram Description contd..

• In order to identify the four registers, 8255 uses two address lines A0 and A1.

• These lines get their signals from the 8085 processor address bus.

• The identification of the registers based on A0 and A1 is


Pin details of IC 8255


Pin diagram Description• The three ports of 8255 needs 8 lines each and so 24 pins

are allotted for ports and these lines are connected to external Input or output devices.

• D0-D7 are the lines required for interfacing 8255 with the processor.

• These data lines are connected to the data bus of the processor.

• Eight lines or pins are remaining. Out of these 8 lines, 2 lines A0 and A1 are allotted for selecting one of the 4 registers available in 255.


Pin diagram Description contd..

• The control signals for reading and writing to these registers re the active low is RD and WR signals.

• These signals are obtained from the processor control signals. • The entire chip is selected by activating the active low chip

select CS signal. • This signal is in general obtained from the decoder which

decodes the address lines and identifies the 8255 addressing. • A common reset signal can be applied to reset 8255 and can

be same as RESET OUT of 8085 processor.


Operating modes and control words of 8255

• The functional operation of each port is programmed by the software in other words by the programmer.

• The programming of 8255 is done by writing a control word to the control register of 8255.

• The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 8255.


Operating modes in 8255


Operating mode- description

• There are two different configurations of 8255 namely input /output mode (I/O mode) and Bit set reset mode (BSR mode).

• Again in I/O mode, there are three modes for the ports. The control word format for the I/O configuration and BSR configuration

• Group A and Group B accept “commands” from the Read/Write Control logic, receive “control words” from the internal data bus and issue proper commands to its associated ports.


Operating mode- description contd..

• Before using the chip, it has to be programmed to configure its operation.

• The configuration is done by the control word and it tells the 8255 whether ports are input or output and even tell whether ports are bi-directional or strobed.


I/O Control word Format


Control word - Description

• The MSB D7 bit is set to 1 to indicate that Input and output mode of the ports are configured in the I/O control word.

• Bits D6 and D5 are used select the operating modes of the group A.

• There are three basic modes of operation for group A and can be selected by the control word.


Description of MODE select bit

• Mode 0 - Basic Input/Output (Bits D6 and D5 are 0 and 0) - Ports A and B operate as either inputs or outputs and Port C higher order 4 bits can be operated as inputs or outputs.

• This mode uses simple I/O operation and no interrupts are used.

• The outputs written to the ports are latched and available at any time. Inputs available at the port pins are buffered through port latches.


Description of MODE select bit contd..

• Mode 1 - Strobed or Handshake Input/Output (Bits D5 and D6 are 0 and 1)- Port A is configured in mode1 but Port C is used for handshaking and control of data transfer in Port A.

• Input and output data are latched• Mode 2 - Bi-directional Bus (Bits D5 and D6 are 1 and X,

don’t care) Port A is bidirectional (both input and output) and Port C is used for handshaking.

• Port B cannot be programmed to have this mode.


Control word – Description contd..

• Bit D4 is used to select the direction of data flow in the Port A bits.

• That is it programs whether the port A bits are input pins or output pins.

• For making Port A bits as input pins, bit D4 of the control word is set to 1 and it is set to 0 to program Port A as output port.

• Bit D3 is used to input and output operation of Port C upper four bits.

• For making Port C upper bits as input pins, bit D3 of the control word is set to 1 and it is set to 0 to program the same as output port.



• Bit D2 of the control word is used to select the mode for the group B. As discussed earlier, only two operating modes are possible for Group B i.e., Mode 0 and Mode1.

• Mode 0 - Basic Input/Output for Group B is selected if bit D2 is programmed as 0. This mode uses simple I/O operation and no interrupts are used as discussed earlier.

• Mode 1 - Strobed or Handshake Input/Output is selected for group B if D2 bit is set to 1. Port B is configured in mode1 but Port C lower bits are used for handshaking and control of data transfer.



• Bit D1 is used to select the data direction for Port B pins. If it is 0, then Port B pins are configured as output pins and if it is 1, then the port B pins are configured as input pins.

• Bit D0 is used to select the data direction for Port C lower pins. If it is 0, then the Port pins are configured as output pins and if it is 1, then the port C lower order pins are configured as input pins.


BSR Mode control word format


Description – BSR Mode control word

• In Bit Set Rest (BSR) mode, any of the eight bits of Port C can be Set or Reset using a single control word written to the control register.

• This feature reduces software requirements in control-based applications and using mode 1 and 2 of other ports.

• When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were output ports.


I/O mode 1 operation

• This Mode 1 configuration of 8255 provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “hand shaking” signals.

• In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals.

• In mode 1 the ports are divided into two Groups - Group A and Group B. Each group contains one 8-bit port and one 4-bit control/data port.


I/O mode 1 operation contd..

• The 8-bit data port is either Port A or Port B and can be either input or output.

• Both inputs and outputs are latched. • The 4-bit control port is either Port C upper or Port C

lower bits and can be used for control and status of the 8-bit port.


Control and Handshake signal for Input operation in Mode1


Input Control and Operation

• The operation of handshake signals for the input operation in 8255 is explained with the above figure.

• The sequence of operations for the data input operation from an input device to microprocessor through 8255 is listed as followed.


Input Control and Operation contd..

• Step 1 • The input device places data in the data lines i.e., the Port A

or Port B lines. This is communicated to 8255 by making STB (Strobe Input) low. STB is an active low signal applied to PC4 or PC2.

• Step 2• 8255 acknowledges the receipt of the data to the input by

making IBF (Input Buffer Full) high. This also indicates that the data has been latched into the input port.



• Step 3• 8255 then makes INTR line (Interrupt Request) high and

applies an interrupt to the processor. This signal is applied with a condition that INTE (Interrupt Enable) must be high. INTE for Port A is controlled by bit set/reset of PC4 and INTE for port B is controlled by bit set/reset of PC2. PC2 and PC4 can be controlled using BSR mode.



• Step 4• The processor in the interrupt service routine reads the

data from the corresponding input port. Reading from the port is done by selecting the 8255 port and applying RD active low signal.

• Step 5• During Read operation the RD signal low. When RD signal

goes low, INTR signal is reset. IBF is reset by the rising edge of the RD input.



• The entire procedure explained above for mode1 allows an input device to request service from the CPU by simply sending its data into the port and giving STB signal.


Control and Handshake signal for Output operation in Mode1


Output Operation and Control

• The control signals or handshake signals used for the output in mode 1 of 8255

• The handshake signals used are OBF, ACK and INTR. • The sequence of operations taking place for data output

from the processor to an output device is listed below.


Output Operation and Control contd..

• Step 1• The processor will initiate the data transmission by writing the

data to be transmitted to the output device to the corresponding port of 8255.

• This is done by processor by sending the port address to 8255 and data on the data lines and then giving the active low WR signal.

• Step 2• To transfer the data to the output device, 8255 will make OBF

(Output Buffer Full- active low signal) “low” to indicate that the CPU has written data to be given to the specified port.

• The OBF flip flop will be set by the rising edge of the WR input.



• Step 3• The data available on the output port pins are then read by

the output device. • After receiving data from the port pins, the output device

acknowledges the same by making ACK low. • ACK is an active low input signal to 8255 from the

peripheral device indicating that it is accepting data. • OBF output signal of 8255 is reset by ACK input being low.



• Step 4• 8255 will now inform to the processor that data has been

transferred to the output device by making INTR (Interrupt Request) line high.

• A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU.

• INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”.



• Step 5• In the interrupt Service routine, the processor writes the

next data to be transmitted to the output device to the output port of 8255.

• INTR signal is reset by the falling edge of WR.


I/O mode 2 operation• In mode 2, data is transmitted and received via port A

pins (bi-directional bus I/O) with handshaking capability.• Only Port A can be configured in Mode 2 and is used as a

bi-directional port while port C is used for handshaking signals.

• Interrupt generation and enable/disable functions are also available through Port C pins.

• Meanwhile, Port B can be configured to be in Mode 0 or 1 and Port B cannot be configured for mode2.


I/O mode 2 operation contd..

• Both inputs and outputs are latched.• The 5-bit control port (Port C) is used for control and

status for the 8-bit, bi-directional bus port (Port A). • The basic control signal transmission and operation of

the data transfer in mode 2


Control of Port A data transfer in Mode 2


Control Signal and operation of Bi-Directional Bus I/O-

Mode 2 contd..• The input and output operation of 8255 in mode is

similar to the operation in mode 1 except that the Port A is bidirectional port.

• The data is transmitted and received through the Port A lines.

• For the output operation, as in mode 1, the data transfer is initiated by the processor by making the active low signal OBF low.



Mode 2 contd..• This indicates that the processor has written data to output

port. • The output device after reading the data will give an

acknowledgement by making ACK (Acknowledge signal – Active low signal) low.

• The processor will then be interrupted by 8255 to indicate that the output data port is ready for next data output or transmission.

• Here, the interrupt can be applied to processor only if INTE 1 flip flop associated with OBF and controlled by PC4 is set by the processor earlier



Mode 2 contd..• The input operation is also similar to mode 1 operation.

Here the data transfer is initiated by the input device by placing the data on the port pins.

• Then an active low control signal STB is given to 8255 by the input device for taking data.

• 8255 will now latch up the data to its port and then give an active high signal IBF to the input device.



Mode 2 contd..

• 8255 will then issue an interrupt signal to the processor to indicate that a data is readily available for read operation.

• Here, the interrupt can be applied to processor only if INTE2 flip flop associated with IBF and controlled by PC4 is set by the processor earlier.


Debouncing of Keys• Keys in general are any one type of Push-button

switches, toggle switches, and electromechanical relays and all these have spring contacts.

• Metal contacts make and break the circuit and carry the current in switches and relays. These contacts have mass and have spring to control the movement.

• Because the moving contacts have mass and spring with low damping they will be "bouncy" as they make and break.


Debouncing of Keys• When a normally open (N.O.) pair of contacts is closed,

the contacts will come together and bounce off each other several times before finally coming to rest in a closed position.

• The effect is called "contact bounce" or, in a switch, "switch bounce”.

• The waveform of the contact bouncing is shown in figure for breaking of contact from 1 to 0 positions.


Contact Bounce waveform


Debouncing of Keys• If such a switch is used for sensing by input ports of a

microprocessor, then there is a chance that the microprocessor responds several times and input can be sensed repeatedly even though the key pressed is only once.

• In general the bouncing of the switch may last for several milliseconds.

• The microprocessor works at microseconds speed and so the bouncing will be sensed by microprocessor several times.


Solution – Key Debouncing

• The simplest hardware solution uses an RC time constant to suppress the bounce and the circuit for the same is shown in figure

• The RC time constant has to be larger than the switch bounce and is in general selected around 0.1 seconds. The capacitor takes at least the twice time constant to change from one position to the other.

• During this time, any change in the switch bouncing will not be transmitted after the buffer. The buffer after the switch is used to make the transition from high-to-low or low-to-high sharp.


Hardware Solution – Debouncing of Key


Solution – Key Debouncing

• The key bouncing problem can be solved by software methods also. The easiest software method is to make the processor wait until the bouncing oscillation settle down.

• This wait-and-see technique is implemented using the software time delays. When the voltage from the switch changes, an “appropriate” delay routine is executed (10 ms), then the value of the voltage on the switch line is checked again to make sure the line has stopped bouncing.

• The delay is normally 10 ms as in most of the switches, the oscillations settle within that period.


Interfacing Seven Segment Displays

• Seven segment Light emitting diode displays are most commonly used low cost displays and are easiest to interface with microprocessors.

• Seven segment displays consist of seven LED segments. The seven segments are arranged in the form as shown in figure and the display of various digits from the seven segment display is also shown in the same figure.

• Seven segment displays are available in a single dual line in package (DIP). There are each pin for each segment and these pins are named from a to f and another LED is available for decimal point (dp).



• In addition to these eight pins, the seven segment displays have one more pin for power supply. Seven segment displays come in two types either in common anode or common cathode.

• In common anode display, the anode of all segment LEDs are tied together and taken out. So, to illuminate a segment, the common anode is connected to the supply and then the segment input i.e. a to f is connected to a low level logic 0.



• In common cathode display, the cathodes of all the LEDs are connected together and taken out.

• So, to illuminate a segment, the corresponding segment input is connected to the high level voltage or logic 1 and the common cathode is connected to the ground.

• This will forward bias the LEDs and illuminate them.


LED Arrangement in Seven Segment Display


Driver Circuit for single seven segment display


Driver Circuit - Description

• Figure shows the circuit required to drive a single seven segment LED display from four bit BCD output. The BCD to seven segment display decoder IC 7447 converts the four bit BCD code applied at its input in to the patterns required to display the BCD number.

• The patterns generated are active low outputs, meaning that logic 0 is given as output when a particular segment is to be illuminated. So, the common anode display is suitable for use with 7447.

• The complete circuit diagram for interfacing the seven segment display along with the address bus decoder and latch are given in the figure .


Complete Circuit for interfacing single seven segment display


Instruction used to Display Data

• The following instructions can be used to display the data in the seven segment display.• MVI A, control word• ; Load accumulator with the 8255 control word and• OUT control_register• ; output it to the control register of 8255• MVI A, data• ; Load accumulator with data to be displayed and • OUT PORT_A• ; output it to the port A, where display is connected


Interfacing Circuit-Description

• We can connect two seven segment displays to single eight bit port. One 7447 IC can be connected to lower four bits and another 7447 can be connected to the higher order 4 bits of the Port A.

• So with single 8255 which has 3 parallel I/O ports, we can connect 6 seven segment displays. This results in more complicated circuit.


Interfacing Circuit-Description

• The complexity of the circuit can be reduced by using a technique called Multiplexed display.

• By using multiplexed display many displays as much as eight can be connected with the two ports alone.

• The multiplexed display concept is discussed in chapter covering 8279 IC – Keyboard display controller IC.


Interfacing Analog to Digital Converter

• Introduction to analog to digital converter• The basic function of the analog to digital converter is to

convert the input analog voltage levels in to corresponding discrete digital signals.

• ADC is essential in a microprocessor based system as the microprocessor can only handle digital data but the real world signals are all in analog form only.


• There are many types of ADC. The major ones are counter ramp type ADC, dual slope ADC, Flash type ADC and Successive Approximation type ADC. Each type of ADC has its own advantages and disadvantages.

• Successive Approximation type ADC is commonly available ADC. This ADC has fixed conversion time for any analog input voltage level.


• The specifications of the ADC are the range of analog input voltage, the number of digital bits at the output, resolution, the conversion time and the number of analog input channels.

• The analog input voltage can be either unipolar or bipolar. Unipolar means the input voltage can have only one polarity like (0 to +5V) or (0 to +10V).

• Bipolar means the input voltage can range from one polarity to the other like (-5V to +5V) or (-10V to +10V).


• Most of the ADC chips come with an option of selecting one of these voltage ranges using Vref input pins.

• The ADC chips are available for different number of output binary bits. ADCs are available with 8 bits or 10 bits or 12 bits or 16 bits digital outputs.

• The number of bits will decide the number of voltage levels sensed. For example an eight bit ADC will have 28 possible levels i.e., 256 levels. The number of bits and the input voltage range will decide the resolution.


• The resolution of an ADC is defined as the smallest change in the input voltage that can be sensed or detected at the output.

• The resolution can be mathematically defined as the range of input voltage divided by the number of levels at the output.

• For example, an ADC with the input voltage range of (0 to+5V) with 8 bits at the output will have a resolution of (5/256) i.e., approximately 19.5mV.


• The conversion time of ADCs will be decided by the type of the ADC, and the clock frequency used in the converter circuits.

• Some ADC chips come with an option of having more than one analog input. One of these analog input channels are selected using select lines and an analog multiplexer circuit.

• The ADC chips also have a sample and hold circuit. The sample and hold circuit is used to maintain the analog input voltage constant when the conversion is in progress.


ADC chips and interfacing to microprocessor

• The single chip analog to digital converters available in the markets are having many options. Commonly available ADC chip family is ADC080X from National Semiconductor.

• ADC 0800, ADC 0804, ADC 0808, ADC 0816 are the common chips available in this family. ADC 0804 has one analog input channel with 8 bit output.

• ADC 0808/0809 has eight analog inputs with three bit channel select lines and an 8 bit output. ADC 0816 has 16 analog input channels with four select lines and 8 bit outputs.


• This section will discuss the operation and interfacing of ADC0816 with 8085 microprocessor through 8255 PPI.

• ADC 0816 is an 8-bit successive approximation type ADC chip with an in-built analog multiplexer which can select one of 16 analog inputs for conversion into digital format.

• One of 16 analog inputs IN0 to IN15 in the ADC0816 chip can be selected by the select lines A, B, C, D.


• The analog to digital conversion can be started by using the active high control signal SC.

• The conversion of the analog voltage on the input channel selected will then take place based on the clock signal applied to the ADC chip.

• After the conversion is over, ADC chip will issue an active high ‘end of conversion’ signal on the EOC line. The digital output can then be read from the data lines after issuing ‘Output Enable’ signal to the ADC chip.


Interfacing ADC0816 with 8255


• In the interfacing diagram the Port A of 8255 is used to output or send the channel select lines and the related control signals.

• Port B lines are used to get or input the digital result data from the ADC chip.


• Port C LSB is used to check the end of conversion signal. With this hardware arrangement, the ADC chip can only be interfaced with software polling method.

• For interrupt driven interface, the EOC signal can be connected to any interrupt input. Analog inputs can be applied to the analog input pins of ADC 0816.


Control Word Format


• The ADC conversion process can be started after applying the analog input to any of the channels.

• The conversion process is started by initializing 8255 with the proper control word.

• Then the Channel selection and Start conversion is done simultaneously as these two control bits are tied together in the hardware.


• The start conversion must be issued as a pulse for a minimum duration only. Then the conversion takes place in the ADC chip, if it is properly powered and clock pulses given.

• After the conversion, the logic high ‘End of conversion’ signal is issued by ADC chip. This is sensed in the software.

• Then the data is read from the data lines after issuing the logic high ‘Output Enable’ signal. The program for the ADC conversion process is given below as a software routine.


• The following routine assumes that the channel number to be converted is available in the memory location named CH_NUM.


Interfacing Digital to Analog Converter

• Digital to analog converters are used to get a proportional analog voltage or current for the digital data given out by the microprocessor.

• The D-A converters are essential in a microprocessor based systems as the real world applications are operating with analog data. Basically there are two types of DAC.

• They are R-2R ladder network and weighted resistor network. Many DAC chips are available in the market.


• The specifications of the DAC chips are the full scale output voltage, number of binary input bits, resolution, linearity and settling time.

• The DAC chips come with choices in the maximum output voltage as 5V, 10V or with a predefined maximum current output. The number of binary input bits can be 4 bits or 8 bits or 10 bits or 12 bits.

• The number of bits and the full scale output voltage both will determine the resolution. For example, an 8 bit DAC can have 256 input combinations and so has a resolution of (1/256) or 0.39 percentage of the full scale output.


• Similarly, the 10 bit DAC will have the resolution of (1/1024) or 0.0977 percentage of the full scale output.

• Linearity is a measure of how straight the output is when the output is changed from minimum value to the maximum value.

• The settling time is defined as the time take for the output to settle within pre-specified band after the input digital value is applied. Normally, pre-specified band is [final value±(1/2)*Minimum possible output].


• The settling time is an important specification as the DAC output may overshoot the correct value and may oscillate for some time before settling.

• The settling time for a DAC chip should be considered in applications where high frequency operation is essential.

• Digital to analog converters are required to generate the variable analog voltage essential for control applications Most of the speech synthesizers required a DAC to convert the binary data in to the corresponding analog speech signal.


• DAC 0800 is a common digital to analog converter chip that can be easily interfaced to 8085 through 8255. This section will describe the interfacing of DAC 0800 with the 8085 processor.

• As the DAC chip can only be connected to an output port of a processor, the 8255 PPI is essential in the interface. Any one port is enough to interface an 8-bit DAC with 8255.


• The other control signals are directly correspondingly connected to either logic 0 or logic 1. The DAC chip gives a proportional current output.

• This current output in most cases is difficult to measure and so a current to voltage (I to V) converter is used at the output. DAC chips have an inbuilt latch.

• This latch stores the digital input given by the port A and gives out a proportional voltage.


Interfacing DAC 0800 with 8085


• Four common applications such as square wave generation, ramp wave generation, staircase wave generation and sine wave generations are discussed.


Interfacing of stepper motor using 8255


• The stepper motor has six terminals – four terminals ABCD for excitation and two more for giving supply.

• The figure shows the four terminals ABCD connected to the 8255 ports through the transistor drivers.

• The transistor drivers or buffers are essential as the port pins cannot directly source the current required for the motor drive.


• As explained earlier, the motor terminals have to be excited in a proper sequence, so that rotor will have continuous rotation in one direction.

• Two types of excitation are possible with four phase motor. They are one phase excitation and two phase excitation.

• In one phase excitation, only one phase of the stepper motor is excited at a time and in two phase excitation, two phases are excited at a time.


• The exciting sequence is fixed for a rotation in a particular direction.

• The single phase excitation results in low current through the motor windings and it is also called wave mode.

• In two phase excitation, the excitation current through the motor winding is high and so it is called as high torque excitation.

• The table also gives the corresponding hexadecimal byte value to be given to the Port A assuming the MSB 4 bits as zero.


• The software part of driving the stepper motor mainly consists of giving the proper excitation sequence signal to port A terminals of the 8255. A proper delay can be inserted in between the subsequent excitation of the motor terminals to control the speed of rotation of the motor.

• Also a minimum delay must be maintained between the excitation of the coils so that the motor coils will get properly excited.

• This minimum delay also sets the maximum speed of operation of the stepper motor.


Interfacing intelligent LCD display

• Many alphanumeric liquid crystal displays are available in the market. These displays have an in-built controller IC and a display section.

• These displays can be easily interfaced to any microprocessor or microcontroller. The data displayed in LCD displays can be easily controlled and changed.


• Liquid Crystal Displays are created by placing thin layer of liquid crystal fluid in between two glass plates. Transparent electrically conductive films are pasted on the front and back glass plates in the shape of the character to be displayed.

• When a Voltage is applied between these two films, the electric field changes the behavior of the liquid crystal and so the light is transmitted through it or reflected by it. Hence the required display is seen visible.


• Modern LCD display devices come with a controller IC and related control inputs. It gets ASCII code of the data to be displayed and displays the character in the exact location.

• The LCD displays come with many options like from 8 characters display to 80 characters and from single line to 2 lines or 4 lines display. Almost all these devices have 14 pins for interfacing with microprocessor or microcontroller.


• Three pins E, R/W and RS are used for the control and handshake signals. Eight pins are used for transferring data to the display and can be connected to the data bus of the system.

• Two pins are allotted for supply and ground, one more pin is used for adjusting the contrast of display. The voltage applied to this pin can be varied to adjust the contrast.


• LCD display consists of internal RAM for storing the data to be displayed. Control signal RS given as input to LCD display will indicate whether the data available on the data lines is a command or a display data.

• RS is made zero to indicate that a command to LCD is being sent on the data lines. RS line is made high to indicate that the data lines contain display data to be read or written.

• R/W is also an input control signal given to the LCD display to indicate the direction of data transfer.


• Enable control input is a clock input that performs the required read or write operation. A 1 to 0 transition on this line will enable the corresponding operation decided by other control inputs.


• The display can be cleared by issuing a command with LSB alone as 1.

• Similarly cursor control, display position control, display method control can be done using appropriate control words.


• Port A is connected to the data lines of LCD display and Port C is connected to the control lines. PC.2 is connected to the Enable line of the LCD. RS signal is connected to the Port C LSB. Port C.1 is connected to the R/W control signal.


LCD interfacing through 8255


ASCII code and corresponding display pattern


• The programming part of the LCD interface is given below. The LCD display works with it’s own internal clock pulses. So, any command or data written to the LCD display must be enabled with EN signal.

• This EN signal must be applied for predefined time duration. Each command and data requires a minimum of 40microseconds to about 1.6 mseconds depending upon the type of LCD and it’s clock frequency.


• So, a separate subroutine is written to give proper control signals for the predefined delay time. Here two subroutines COMMAND and DISP are written to write a command word and a data for display respectively.

• These two subroutines use a delay routine commonly.


• The first step in the program is to clear the display and then to set the cursor to home position and start display form there.

• The simple program below is written to display an array of characters stored in memory locations starting from 9000H.

• The number of characters displayed is NUM_CHAR and it is initialized as a count in C register. All the characters are displayed continuously.


Keyboard and Display Interface IC 8279

• Intel 8085 processor interfacing with keys and displays has been discussed in the previous sections. It is seen that for displaying data, an external port IC like IC 8255 is necessary. Similarly, for key interfacing also, a port is necessary and the processor needs to check the inputs from the keys for identifying whether any key is pressed or not.

• Moreover, these simple interface circuits become more complicated when more number of display units and switches are interfaced to the processor.


• To reduce the hardware for large keyboard interfacing, the matrix keyboard concept is used. To interface more number of displays, the multiplexed display concept is used.

• This chapter introduces the Matrix keyboard and the multiplexed display concepts. These circuits again require more processing time.

• To reduce the processor involvement in the matrix keyboard scanning and multiplexed display, Intel has produced a dedicated IC 8279.


• This IC will relieve the processor from keyboard scanning and scanning multiplexed display. The hardware details about this IC and the programming of this IC are covered in this chapter.


Matrix Keyboard

• Single key switch interface to 8085 through 8255 has been discussed in the previous chapter. The limitation of this interface is that each switch must be allotted a separate port pin.

• The hardware complexity increases as more number of switches are interfaced. The solution to this problem is using a matrix keyboard.


• The Matrix keypad has more number of switches organized or connected in matrix form.

• The rows of the keyboard matrix are connected to the four output port lines. The column lines are connected to the four port lines of an input port.


• When no key is pressed, the column lines are connected to the (+5V) Vcc line and so the data at the input port pins will be all 1s.

• If a low or logic 0 is output on a single output port bit and if any switch in that row is pressed, then the corresponding column data bit will become logic 0 while other column bits will be logic 1.


• For example, let us assume that D0 of output port is made 0 while other bits of output port are at logic 1. If key 3 is pressed, then the input to D3 bit of the input port alone becomes zero while D0 to D2 input bits are at logic 1.

• So, by making D0 output line to 0, we can detect which key is pressed in the corresponding row.


• The technique to detect the key pressed among all the keys is as followed. Output 0 to a one row first and check any zero in the column input lines.

• If there is no zero, then output 0 in the next row and then check column input lines. Repeat the above procedure for all the rows.


Matrix keyboard organization


• Once a key is pressed, then steps must be taken to remove the contact bounce problem. Mechanical switches have a problem called ‘Contact Bounce’ because of their construction.

• Pressing a mechanical switch must produce a single pulse output. Practically, instead of producing a single clean pulse output, the switches generate a series of pulses because the switch contacts do not come to rest immediately.


• As the microprocessor is faster than manual key pressing, the single key pressed will be registered as multiple key presses. This is the main disadvantage of key bouncing.

• The signal from keys falls and rises a few times within a period of about 5ms as the contact bounces.

• So, the signal from the key must be must be made free from key bouncing transients. This technique is called as Debouncing of key.


• Key board debouncing can be accomplished in hardware or software. The bouncing of key signals occur within 5ms. A human cannot press and release a switch in less than 20ms.

• A debouncing logic will check the signal after 20ms and then recognize whether a key is pressed or not. This logic can be implemented in hardware or software.

• The hardware techniques employ SET-RESET flip flops or Non-inverting CMOS gates or integrating debouncer.


• The software technique uses the wait and see method. When signal from a switch is sensed, the program will wait for 10ms and look at the same key again.

• If the signal form the switch still indicates the key press, then the program decides that the user has pressed the key.

• Otherwise the signal received is rejected as noise.


• The software for sensing a key pressed in a keyboard matrix requires the scanning of the rows and columns and detecting a key pressed. Even after sensing a key, the software may be used for key debouncing.

• The software overhead for this high and the processor may be held up in scanning for a long time. To overcome this problem, Intel has produced IC8279.

• This IC can take care of keyboard scanning and debouncing and detect the key pressed.


Multiplexed Display

• The seven segment display discussed in the previous chapter uses individual port pins for each display. This requires one port for each seven segment display.

• In order to reduce the hardware complexity for more number of display devices, matrix display method is used. Here with two ports, as much as 8 display units can be interfaced.


Multiplexed Display Arrangements


• The data pins for all the display devices are tied together and connected to any one port pin. Any one display unit can be selected using another port line.

• Only one display unit is given active low data and the same is selected by the select lines.

• But, the user must see display on all the display units simultaneously.


• This is done by giving data and displaying it in each and every display unit at a very fast rate. Due to the persistence of vision, the human eye can hold the display image in it and the user can see as if all the display units are illuminated.

• As long as the displays are turned on and off fast enough, the eye will perceive them as if they are all on together.


• The software part for the matrix display consists of selecting one display unit and giving data to it and then repeating the same procedure for all the display units at a faster rate.

• The timer can be used to control the rate of display and refreshing the display. Again, this takes a lot of processor time.

• To take care of multiplexed display and its refreshing, IC 8279 is used.


Features, Block diagram and pin details of 8279

• Features• IC8279 is a programmable keyboard and display interface

controller IC designed by Intel for use with Intel microprocessors. The major features of this IC are listed below.

• Supports up to a maximum of 64 key matrix with 2-key lockout or N-key rollover options

• Supports up to 16 digit display interface with many options• Simultaneous keyboard and display operations• 8 character FIFO memory to store codes of keys pressed• 16 byte display-RAM to store display data to 16 digits


Block diagram

• IC8279 basically has three sections. The first section is the display section with its own display RAM. The next section is keyboard scan section with FIFO registers. The last one is the control logic with signals for interfacing to the processor.

• The control section basically consists of data bus buffer for interfacing to the processor.


• This I/O section uses the control signals such as A0, - control signal is used to select the IC and this is an active low signal. Similarly and are the active low control signals for indication of direction of data transfer on the data bus, DB0-DB7.

• A0 is the signal used to select any one of data or control registers. A logic 1 on A0 line means the data bus content is a command or status.


• A logic 0 means the data bus content is the data for the IC8279. Control and timing registers store the keyboard and display modes and other operating condition to be programmed.

• Even though there are many control registers and data registers, 8279 uses only two addresses – one with A0=0 and other with A0=1.

• This is done by using different control words for different operations. For example two different control words are available for accessing Display RAM and keyboard FIFO.


• First the corresponding control word is written and then the necessary register is accessed and the operation is done.

• SL3-SL0 are the four scan lines given out by 8279. There are two programmable options for the scan lines - Encoded mode and decoded mode. In encoded mode, the SL3-SL0 lines are binary counter outputs and need to be decoded externally for scanning keyboard and displays.

• In the decoded mode, the SL3-SL0 outputs are decoded with one of four line selection.


• The scan lines SL3-SL0 are common to both keyboards and displays. RL7 to RL0 are the eight return lines and are inputs used to sense key pressed in the keyboard matrix.


Internal Block Diagram of IC8279


• The other signals available in the 8279 are listed below. • BD: Output signal that blanks the displays.• CLK: Clock input used internally for timing. Maximum clock

frequency used is 3 MHz.• CN/ST: CoNtrol / STrobe, connected to the control key on the

keyboard.• Shift: Shift connects to Shift key on keyboard.• IRQ: Interrupt request, becomes 1 when a key is pressed, data

is available.• OUT A3-A0/B3-B0: Outputs that sends data to the most

significant/least significant nibble of display.• RESET: Connects to system RESET.


Pin details of IC8279


Programming of 8279 • IC8279 can be programmed to select the number of

displays, type of key scan, select the memory to write the display data, selection to blank display, select the key code read option and to control the interrupt request signal.

• All these operations or commands are written into 8279 through the data bus with logic 1 on A0 line. The most significant three bits of the control word differentiates the different operation.

• The first 3 bits of the byte sent to control port selects one of 8 control words


Keyboard / Display

Mode Set Control word• The mode set control word is used to set basic control

modes for the display and the key board interfacing. As mentioned in the previous section the most significant three bits of this control word is made as 000.

• The next two bits correspond to the display mode and the least significant three bits correspond to the key board control.


• The display control word definition bits DD will have four options. The options are for setting whether the display is for 8 digits or 16 digits. The other for display is whether to have calculator type right entry or typewriter like left entry.

• The key board interface has the options for encoded output or decoded output on SL3-SL0. For encoded keyboard option, SL3-SL0 scan outputs are active-high and follow binary bit pattern 0-7 or 0-15.


• For Decoded keyboard, scan outputs are active-low with only one low at any time. In strobed keyboard mode, an active high pulse on the CN/ST input pin strobes data from the RL pins into an internal FIFO.

• In 2-key lockout mode, 8279 detects only one key pressed. If two keys are pressed simultaneously, then the key which was released last is considered. All the keys are debounced using the internal hardware delay for debouncing.


• In N-key rollover mode, 8279 accepts all keys pressed from 1st to last. Even if two or more keys are pressed simultaneously, then all the keys are sensed and stored into the FIFO according to recognition by the keyboard scan.

• In sensor matrix mode, the debounce logic is suppressed and any key sensed in the matrix is directly stored into the sensor RAM.


• The clock command word programs the internal clock driver. The code PPPPP shown in table 7.9 corresponds to the binary code by which the input clock signal must be divided to achieve the desired operating frequency.

• With the five bits, the division is possible by 2 to 31. For example, for an operating frequency of 100KHz, the count should be 01010B (10D) for a 1 MHz CLK input.

• This control word decides the scan times and the debounce times.


• The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer (000 to 111). AI in figure 7.10 selects auto-increment for the address.

• If AI is set to 1, then address will be incremented after every read operation.

• So, continuous read operation will fetch the data from FIFO one after the other to the processor. In the scan keyboard mode, the AAA and AI become irrelevant.

• All data from the FIFO are read consecutively in the same order in which the data were entered into the FIFO.


• Writing the above command to the command register will set 8279 to get the display data and store them into the display RAM.

• If AI is set 1, then auto increment options similar to Read Display RAM will be implemented. Subsequent data written with 0 in A0 will be written into subsequent RAM addresses.


• Other Command words:• Other commands like reading display RAM, Blanking

display, clearing the display or FIFO, clearing the IRQ signal to the microprocessor may not be necessary for basic interfacing of keyboard and display.

• So, a summary of these commands are given below. The more details of these commands can be obtained from the datasheet of 8279.


• The display RAM – read control word selects the address of one of the display RAM positions and subsequent read operation using A0=0 will read data in that display RAM address.


• The display write inhibit control word inhibits writing to either the leftmost 4 bits of the display (left W) or rightmost 4 bits using I-I bits.

• Using this inhibit, it is possible to write to a digit in the display RAM without affecting the other digit being displayed. Masking using MM bits blank (turn off) lower or upper nibble of the display output data


Keyboard status word

• To determine if a character has been typed, the FIFO status register is checked. The keyboard status word contains status of FIFO, error and display availability.

• This status word can be read from 8279 when A0 is high. The status word format is given below. The LSB 3bits are used to indicate the number of keys pressed and available in the FIFO.

• The next bit F is used to indicate that FIFO is full. Underrun error bit U is used to indicate a read attempt from the empty FIFO.


• Overrun error bit O is used when the entry into a full FIFO is attempted. S/E is used to indicate multiple keys pressed. D bit is used to indicate the unavailability of the display.


Keyboard code word format:

• In the scanned keyboard mode, the character entered into the FIFO corresponds to the position of the switch in the key matrix and the status of the control and shift keys.

• The data read from the FIFO RAM has the following format. The MSB corresponds to the status of the control key while the next bit corresponds to the shift key.

• The next three bits are from the scan counter and indicate the row in which the key press was identified. The LSB three bits correspond to the column lines in which the key press was identified.


Display interface using 8279

• IC 8279 can be used to interface a maximum of 16 characters. The lines A0-A3 and B0-B3 are used to give the display data to the devices. The scan lines are used to select any one of the display device.


Interfacing seven segment display devices using IC8279


• The number of display devices used in the above scheme is six.

• The seven segment displays are all common anode type and a transistor driver is used with each display device.

• A PNP transistor drive is used to switch between the common anode and +5V.


• A logic low is required to turn on the transistor driver and the same is generated using the decoder IC. Common decoder ICs like 74138 can be used as this IC gives an active low output on any of its outputs.

• The segments of the display devices are all connected together on a common bus and connected to A3-A0 and B3-B0 outputs of 8279. As the displays are all common anodes, the data output for illuminating a LED must be logic low.

• This means that the logic 1 on all the data lines A3-A0 and B3-B0 will blank the display and logic 0 in all these lines will display all the segments.


• The software part for the display interface consists of initializing the 8279 for the encoded output and for eight digit display.

• Then writing the data for display into the display RAM will make the display in the digits. 8279 will automatically keeps the displays refreshed without the help from the processor.

• The following program assumes the 6 digit display is interfaced through 8279 The program given uses programmed and polled method of data transfer.


Keyboard interface using 8279• The keyboard matrix that can be interfaced using 8279 can be

of any size from 2x2 to 8x8. Pins SL3-SL0 sequentially scans each column through a counting operation.

• The 74LS138 decoder IC can drive 0's on one line at a time from the SL3-SL0 lines.

• The 8279 scans RL pins synchronously with the scan. RL pins incorporate internal pull-ups, no need for external resistor pull-ups. 8279 does the three jobs of key board scan – putting a low in a scan line, checking a low on the return lines and detecting the key pressed and then debouncing.


• Three column select lines SL0-SL2 are used to apply a low on any one column line and do consecutive scanning on all column lines.

• Any key pressed can be sensed by a low on the return lines. 8279 does this scanning automatically and stores the key code format into the FIFO RAM.

• In this example, the CNTL and SHIFT lines are not used and are connected to logic low.


Interfacing Matrix keyboard using IC8279


• The software program using 8085 mnemonics is given below. Initially, the mode set command word is written into the command port.

• Here the encoded scan keyboard with 2key lock out mode is used. After writing the command word, IC8279 starts scanning the key presses.

• Any key press can be sensed by reading the status word from 8279 and then checking the LSB 3 bits. Following program checks single key pressed and reads the key code from FIFO.


• The above program uses polled method of data transfer from 8279 FIFO to the processor by reading the status word.

• In order to save the processor time and to avoid the reading and checking of status register, the IRQ line of 8279 can be used to interrupt the processor.

• The IRQ signal is activated by the IC8279 whenever a key press is sensed and its code is loaded into the FIFO RAM.

• This interrupt request line can be tied to any one of the interrupt signals of the processor and the corresponding interrupt service routine can be used to read the key code from FIFO RAM.


354 33 powerpoint-slides ch7

Documents

bits of port c

io port

port b bits

port c upper bits

port c lower bits

port c upper pcu

port c lower pcl

output devices