3/4/20031 ece 551: digital system * design & synthesis lecture set 2 2.1: verilog – the basics...
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ECE 551: Digital System * Design & Synthesis
Lecture Set 22.1: Verilog – The Basics
2.2: Verilog – Simulation and Testbenches
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ECE 551 - Digital System Design & Synthesis Lecture 2.1 – Verilog – The Basics
Overview
Primitives
Modules
Styles
Structural Descriptions
Language Conventions
Number Representation
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Modules
The Module Concept Basic design unit Modules are:
• Declared - define the module and what it does includes both interface & implementation
• Instantiated Use the module in another design or testbench
Note: Module declarations cannot be nested
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Module Declaration *
module decoder_2_to_4 (A, D) ;
input [1:0] A ;output [3:0] D ;
// RTL Descriptionassign D = (A == 2'b00) ? 4'b0001 :
(A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ;
endmodule
Decoder2-to-4A[1:0] D[3:0]
2 4
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Bachus-Naur Form
Verilog syntax conforms to the Bachus-Naur Form (see Text Appendix ? And IEEE 1364-2001 Annex ??) Name ::= begins a definition | introduces an alternative (or) bold text correspond to Verilog key words [item] an optional item that may appear
once {item} an option item that may appear more
than once|... Other alternatives exist, but not
listed
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Module Declaration Syntaxmodule_declaration ::=
module_keyword module_identifier [list of ports]; {module_item} endmodule
module_keyword ::= module|macromodule
list_of_ports ::= (port {, port})
module_item ::=
module_item_declaration | parameter_override | continuous_assign | gate_instantiation | udp_instantiation | module_instantiation | specify_block | initial_construct | always_construct
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Module Declaration - * Annotated
module decoder_2_to_4 (A, D) ; /* module_keyword module_identifier (list of ports) */
input [1:0] A ; // input_declarationoutput [3:0] D ; // output_declaration
// RTL descriptionassign D = (A == 2'b00) ? 4'b0001 :
(A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ; /*
continuous_assign-ment */
endmodule
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Module Declaration– Verilog 2001
Examplemodule half_adder (input wire [1:0] x, output reg [1:0] z);//ANSI style: I/O & datatype declarations in module ports
// behavioral descriptionalways@(x)beginz[1] <= x[1] ^ x[0]; // x1 XOR x0z[0] <= x[1] & x[0]; // x1 AND x0endendmodule
Works in Modelsim
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Module Identifiers and PortsModule identifiers - must not be keywords!Ports
First example of signals Scalar: e. g., c_out Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3]
• Range is MSB to LSB (left to right)• Can refer to partial ranges - D[2:1]
Type: defined by keywords• input• output• inout (bi-directional)
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Module Instantiation Syntaxmodule _instantiation ::=
module_identifier [parameter_value_assignment] module_instance {, module_instance};
parameter_value_assignment ::= # (expression {, expression})
module_instance ::= name_of_instance ([list_of_module_connections])
name_of_instance ::= module_instance_identifier [range]
list of module connections ::= ordered_port_connection {, ordered_port_connection} | named_port_connection {, named_port_connection}
ordered_port_connection ::= [expression]named_port_connection ::= . port_identifier ([expression])
Example: full_add #4 FA[3:0](A, B, C, Sum, C_out); All modules instantiated in one statement must have same
delay.
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Module Instantiation Examplemodule decoder_3_to_8 (A, D) ; input [2:0] A ; output [7:0] D ; wire [7:0] D_temp;wire A2_bar;
not N0 (A2_bar, A[2]); // primitive instant. decoder_2_to_4 D0 (A[1:0], D_temp[3:0]);// module instant.
decoder_2_to_4 D1 (A[1:0], D_temp[7:4]);// module instant.and [3:0] (D[3:0], D_temp[3:0], {4 {A2_bar}}); and [3:0] (D[7:4], D_temp[7:4], {4{A[2]}}); endmodule
Decoder3-to-8A[2:0] D[7:0]
3 8
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Module Instantiation Examples
Single module instantiation for two module instances decoder_2_4 D0 (A[1:0], D_temp[3:0]), D1 (A[1:0], D_temp[7:4]);
Single module instantiation for array of instances half_add [3:0] (sum[3:0], c_out[3:0], A[3:0], B[3:0]);
Named port connections decoder_2_4 D0 (.D (D_temp[3:0]), .A (A[1:0]));
ports no longer have to be in order more likely to get ports correct
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Primitives Predefined Primitives
Built into Verilog Basic combinational and switch-level building
blocks for structural descriptions. For example, nand(c, a, b) // Output must be first
Have behavior, but no lower-level description User-Defined Primitives
Basic combinational and sequential structural building blocks
Have behavior based on lower-level descriptions using truth tables
Covered in detail later
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Built-in Primitives Combination logic primitives
and, nand, or, nor, xor, xnor (one output, multiple inputs)and(z, a[7:0]);
buf , not (multiple outputs, one input)not(a_not[7:0], a);
Three state logic primitives bufif0, bufif1, notif0, notif1 (multiple outputs, one input, one enable)
bufif1(a_buf[7:0], a, enable); Switch level primitives
MOS gates, CMOS gates, Bi-directionals , Pull Gates Useful when doing transistor-level design and simulation Not used in this course
See Appendix A for details
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Built-in Primitives
No declarations - can only be instantiated All output ports appear in list before any input ports Optionally specify: instance name and/or delay
and N25 (Z, A, B, C); // name specifiedand #10 (Z, A, B, X),
(X, C, D, E); // delay specifiedand #10 N30 (Z, A, B, D); // name and delay specified
/*Usually better to provide instance name for debugging.*/or N30 (Out1, A1, A2, A3), // 3-input OR
N41 (Out2, B1, B2); // 2-input OR
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Structural Model Example
module majority (V1, V2, V3, major) ;
input V1, V2, V3 ;output major ;
wire N1, N2, N3;
and A0 (N1, V1, V2), A1 (N2, V2, V3), A2 (N3, V3, V1);
or O0 (major, N1, N2, N3);
endmodule
andA0
V1V2
andA1
V2V3
andA2
V3V1
orO0
major
N1
N2
N3
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Descriptive Styles
Structural - instantiation of primitives and modules
RTL/Dataflow - continuous assignments
Behavioral - procedural assignments
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Style Example - Structural *
module half_add (X, Y, S, C);
input X, Y ;output S, C ;
xor (S, X, Y);and (C, X, Y);
endmodule
module full_add (A, B, CI, S, CO) ;
input A, B, CI ;output S, CO ;
wire N1, N2, N3;
half_add HA1 (A, B, N1, N2), HA2 (N1, CI, S, N3);
or G1 (CO, N3, N2);
endmodule
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Style Example - RTL/Dataflow
module full_add_rtl (A, B, CI, S, CO) ;
input A, B, CI ;output S, CO ;
assign S = A ^ B ^ CI; //continuous assignment
assign CI = A & B | A & CI | B & CI; //continuous assignment
endmodule
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Style Example - Behavioral
module full_add_bhv (A, B, CI, S, CO) ;
input A, B, CI ;output S, CO ;reg S, CO; /* variable required to “hold” values
between events */always@(A or B or CI) /*event list – change triggers
execution */ begin
S <= A ^ B ^ CI; // procedural assignment CO <= A & B | A & CI | B & CI;// procedural assignment end endmodule
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Connections
By position association module decoder_2_4_with_enable (A, E_n, D); decoder_2_4_with_enable DX (X[3:2], W_n, word); A = X[3:2], E_n = W_n, D = word
By name association module decoder_2_4_with_enable (A, E_n, D); decoder_2_4_with_enable DX
(.E_n(W_n), .A(X[3:2]), .D(word)); A = X[3:2], E_n = W_n, D = word
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Empty Port Connections
Empty Port Connections module decoder_2_4_with_enable (A, E_n, D); decoder_2_4_with_enable DX (X[3:2], , word);
E_n is at high-impedance state (z) decoder_2_4_with_enable DX (X[3:2], W_n ,);
Outputs D[3:0] unused. General rules
empty input ports => high impedance state (z) empty output ports => output not used
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Multiple Instantiations/Assignments
Instantiate multiple gates:nand #1 G1 (y1, a1, a2, a3),
G2 (y2, a2, a3),G3 (y3, a1, a3); // same
delay Assign multiple values
assign # 1 y1 = a1 ^ a2,y2 = a2 | a3,y3 = a1 & a3;
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Arrays of Instances - 1module array_of_xor (y, a, b)
input [3:0] a,b;output [3:0] y;xor [3:0] (y, a, b) // instantiates 4 XOR gates
endmodulemodule array_of_flops (q, data_in, clk, set, rst)
input [7:0] data_in; // one per flip-flopinput clk, set, rst; // shared signalsoutput [7:0] q; // one per flip-flop
/* instantiate flip-flops to form an 8-bit register */flip_flop M [7:0] (q, data_in, clk, set, rst)
endmodule
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Arrays of Instances - 2
module add_array (A, B, CIN, S, COUT) ;
input [3:0] A, B ;input CIN ;output [3:0] S ;output COUT ;
wire [3:1] carry;
/* Instantiate four full-adders to form a 4-bit ripple- carry adder */ full_add FA[3:0] (A,B,{carry, CIN},S,{COUT, carry});
endmodule
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Hierarchy Established by instantiation of modules and primitives within modules Typically use a top-down design methodology Verify the design using bottom-up strategy For example:
Add_full
Add_half orAdd_half
nand notxor
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Language Conventions
Verilog is case-sensitive Don’t use the same name for different items
in the same scope All Verilog key words are lower case Identifiers have upper case or lower case
letters, decimal digits, and underscore Specify “strings” in double quotes // and /* comment */ are used for comments Names beginning with $ denote built-in
systems tasks for functions (e.g., $monitor)
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Representing Numbers
Numbers can be represented in: decimal (d or D), hex (h or H), octal (o or O), and binary (b or B)
Representation for numbers is<size>’<base_format><number>
wheresize: gives size in bits (optional) – default at least
32base_format: tells base (d, h, o, or b) – default
decimalnumber: a value expressed in the specified base
Real numbers can use scientific notation (e.g., +1.02e-4)
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Examples of Representing * Numbers
Number Decimal Equivalent Stored4’d3 3 00118’ha 10 000010108’o26 22 000101105’b111 7 001118’b0101_1101 93 010111018’bx1101 - xxxx1101
Numbers whose most significant bit is x or z are extended with x or z.
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Things to Know Module Syntax & Its Use Combinational Logic Primitives & Their Use Description Styles Structural Description
Connections Multiple Instances Arrays
Continuous Assignment Hierarchical Design Language Conventions & Number Representation
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Lecture 2.2 - Simulation and Testbenches
Overview Simulation
Event-Driven Simulation Simulation with Transport Delays Simulation with Inertial Delays Verilog Simulation Scheduling Semantics
Stimulus Generation & Response Monitoring Generic Simulation Structure Testbench Approach
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Verilog Simulation Signals
Values {0, 1, x, z} x - Unknown, ambiguous z - High impedance, open circuit
Strengths Signals have strength values for “switch
level” simulation Not used in this course
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Event-Driven Simulation
Hypothetical Approach: Divide time into small increments and simulate all element outputs for each increment of time.
Problem: Computationally very intensive and slow.
Alternative Approach: Simulate an element only when its inputs have changed.
Why effective? For any time increment, few signals are changing, so activity limited.
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Event-Driven Simulation
Formally, an event occurs when a signal changes in value.
Simulation is event-driven if new values are computed: only for signals affected by events that
have already occurred, only at those times when changes can
occur.
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Event-Driven Simulation
Operation of simulator depends on a time-ordered event queue.
Initial events on the list consist of input changes. These changes cause events to be scheduled (placed on the queue) for execution at a later time.
If the event queue becomes empty, all simulation activity ceases until another input change occurs.
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Event-Driven Simulation
Example:
A
B
CX
Y
Z
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Event-Driven Simulation
Zero Delay Model
A B CX Y Z
x x x x x x
1** 1** 0 1 1 0
1 0** 1 0 1 1
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Event-Driven SimulationUnit Delay Model
A B CX Y Z
x x x x x x
1** 1** x x
0* x x x
x x
1 1
x01 1 1* 1*0*01 1 1 1
001 0** 1 101*1 0 1 1
011 0 0* 11*11 0 0 1
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Simulation with Transport Delay
Example:
A
B
CX
Y
Z
1 2
2
3
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Z=1 X=1
6 Y=0 Z=1
5 Y=1 Z=0
4 Y=0
2 B=1* X=1
Simulation with Transport Delay
Linked Event Queue1 A=1* B=0*
3 B=0* X=0
C=1
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Simulation with Transport Delay Waveforms
A
X
B
Y
Z
C
X
X X X
X X X
X X X X X
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Simulation with Inertial Delay
What is inertial delay? Multiple events cannot occur on the output in a
time less than the delay. Example AND with delay = 2
A
B
C
C
Transport Delay
Inertial Delay
1 ns
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Simulation with Inertial Delay Waveforms
A
X
B
Y
Z
C
X
X X X
X X X
X X X X X1 82 53 4 6 7
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3 B=0* X=0
6 Y=0 C=1Z=1
Linked Event Queue
Simulation with Inertial Delay
1 A=1* B=0*
2 B=1* X=1
4 X=1Y=0X=1 Z=1
5 Y=1 Z=0
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Simulation with Inertial Delay
Material Moved to previous slide
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Verilog Simulation Scheduling Semantics
To be covered later in relation to execution of assignment statements
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Stimulus Generation and Response Monitoring
Generic Simulation Structure
UUTModule
Test Vectors,Force Files,Waveforms
Stimulus
ResponseVectors,Waveforms
Response
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Testbench Approach - 1
Use Verilog module to produce testing environment including stimulus generation and/or response monitoring
UUTModule
Stimulus Response
Testbench Module
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Stimulus Generation Example 1:`timescale 1ns /1nsmodule com_test_bench_v;
reg[8:0] stim; wire[3:0] S; wire C4;
adder_4_b_v a1(stim[8:5], stim[4:1], stim[0], S, C4);
//Continued on next slideendmodule
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Stimulus Generation Example 1 - 2
//Generate stimulusinitial
begin stim = 9'b000000000; #10 stim = 9'b111100001; #10 stim = 9'b000011111; #10 stim = 9'b111100010; #10 stim = 9'b000111110; #10 stim = 9'b111100000; #10 stim = 9'b000011110; #10 $stop;
end
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Stimulus Generation * Example 2
module test_NAND_latchreg preset, clear; // inputswire q, qbar; // outputsNand_latch M1(q, q_bar, present, clear) // instantiate UUTinitial
begin $monitor ($time, “preset = %b, clear = %b, q = %b,
qbar = %b”, preset, clear, q, qbar); #10 preset = 0; #10 preset = 1; $stop;// Hit Enter to proceed #10 clear = 0; #10 clear = 1; #10 $finish; // Returns control to OS
end //This is not a thorough test - input combinations contain x’s endmodule
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Testbench Approach - 2
Other Testbench Stimuli Generators Counters (Good for up to 8 or 9 input
variables) Linear Feedback Shift Registers Loadable Shift Register with
Initialization Memory Memory Containing Test Vectors FSM
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Testbench Approach - 3
Testbench Response Analyzers Comparison to Memory Containing
Response Vectors Linear Feedback Shift Register Comparison to Behavioral Verilog Model
Response Finite State Machine (FSM)
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Summary
Simulation is vital to validation Event-driven simulation is an efficient
approach Inertial delays are harder to simulate Verilog has a specification for simulation
semantics (to be discussed later) A testbench is a useful alternative to
input stimulation files and output response files.