32-bit unsigned multiplier by using csla & claa
TRANSCRIPT
![Page 1: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/1.jpg)
G.SAMBASIVA RAO 11KR1A0410 P.KALYANI 11KR1A0424 N.CHAITANYA 11KR1A0418 T.AKHILA 11KR1A0430
Project associated by
Under The Esteemed Guidance Of Ms.V.MAHESWARI M.Tech.,
Assistant Professor
![Page 2: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/2.jpg)
Aim Of The ProjectThe main of our project is design a 32-bit
multiplier by using either CLAA and CSLA based on area,delay time and power required for the multiplier.
![Page 3: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/3.jpg)
Digital computer arithmetic is an aspect of logic design with the objective of developing appropriate algorithms in order to achieve an efficient utilization of the available hardware.
The basic operation of additions implemented to the operation of multiplication.
Multiplications and additions are most widely used arithmetic computations performed in all digital signal processing applications.
In this project we are going to the performance of different adders implemented to the multipliers based on area and time needed for calculation.
![Page 4: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/4.jpg)
Carry Look A Head Adder:-
ADDER DESIGN
Carry Look Ahead Adder can produce carries faster due to parallel generation of the carry bits by using additional circuitry. This technique uses calculation of carry signals in advance, based on input signals. The result is reduced carry propagation time. For example, ripple adders are slower but use the least energy.
![Page 5: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/5.jpg)
CARRY SELECT ADDER
This adder can be used for the construction of add and shift multiplier which have lowest area, high speed and minimum power consumption.
![Page 6: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/6.jpg)
Algorithm for array multiplier In this algorithm we are using two 4-bits one is multiplier second one is multiplicand.
Example:-
1 0 1 0 multiplier”A”
1 0 1 1 multiplicand “B”
1 0 1 0
1 0 1 0
0 1 1 1 1
0 0 0 0
0 0 1 1 1
1 0 1 0
0 1 1 0 1
0 1 1 0 1 1 1 0
![Page 7: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/7.jpg)
Array Multiplier Using CLA &CSA
product register size be 64 bits. Let themultiplicand registers size be 32 bits. Store the multiplier in least significant half of the product register.
Repat the following steps in for 32 times.
A partial schematic of the multiplier
![Page 8: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/8.jpg)
VHDL SIMULATIONS
The VHDL simulation of the two multipliers is presented waveforms, timing diagrams and the design summary for both the CLAA and CSLA based multipliers.
The VHDL code for both multipliers, using CLAA and CSLA, are generated.
![Page 9: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/9.jpg)
Simulation result
![Page 10: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/10.jpg)
PERFORMANCE ANALYSIS:-
Area Analysis The performance analysis for the area of CLAA and CSLA based multipliers are represented in the form of the diagram
CLAA
Area analysis chart
![Page 11: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/11.jpg)
Delay Analysis
The performance analysis for the delay time of CLAA and CSLA based multipliers are represented in the form of the diagram.
Delay analysis chart
![Page 12: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/12.jpg)
Area Delay Product Analysis:-
The performance analysis for the area delay product of CLAA and CSLA based multipliers are represented in the form of the diagram.
Area delay product analysis chart
![Page 13: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/13.jpg)
AnalysisThe analysis of the project in brief is given in
below table
Multiplier type
Delay(ns) Area Delay area product
CLAA basedmultiplier
98.5 2957Logic cells
291264.5
CSLA basedmultiplier
99.5 2039Logic cells
202880.5
![Page 14: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/14.jpg)
Advantages Cost effective compared to other proposed architectures . High speed, Low power, Less area . Modified CSLA Can be used to implement Wallace tree
Multiplier and Baug- Wooley multiplier.
![Page 15: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/15.jpg)
ApplicationsData paths in Microprocessors.Digital Adders are the core block of DSP
processors.Extensively used in processing units such as
ALU.Forming dedicated integer and floating point
units.In Multiply-accumulate (MAC) structures.Digital Signal processing. High speed Integrated circuit.
![Page 16: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/16.jpg)
A design and implementation of a VHDL-based 32 bit unsigned
multiplier with CLAA and CSLA was presented.
VHDL was used to model and simulate our multiplier. Using CSLA improves the overal performance of the multiplier.
Thus a 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier.
![Page 17: 32-bit unsigned multiplier by using CSLA & CLAA](https://reader035.vdocuments.site/reader035/viewer/2022081512/58abc8371a28ab68068b536d/html5/thumbnails/17.jpg)