3 phase controller cd 00040795

8/12/2019 3 Phase controller CD 00040795

1/50

April 2006 Rev 4 1/50

50

L6711

3 Phase controller with dynamic VID and selectable DACs

Features

2A integrated gate drivers

Fully differential current reading across

inductor or LS MOSFET

0.5% Output voltage accuracy

6 bit programmable output from 0.8185V to

1.5810V in 12.5mV steps

5 bit programmable output from 0.800V to

1.550V in 25mV steps

Dynamic VID management

Adjustable reference voltage offset

3% active current sharing accuracy

Digital 2048 step soft-start

Programmable over voltage protection

Integrated temperature sensor

Constant over current protection

Oscillator internally fixed at 150kHz (450kHzripple) externally adjustable

Output enable

Integrated remote sense buffer

TQFP48 7x7 Package with exposed pad

Applications

High current VRM/VRD for desktop / Server /

Workstation CPUs

High density DC/DC Converters

Order codes

Description

The device implements a three phase step-down

controller with a 120 phase-shift between each

phase with integrated high current drivers in a

compact 7x7mm body package with exposed pad.

The device embeds selectable DAC: the output

voltage ranges from 0.8185V to 1.5810V with

12.5mV steps (VID_SEL = OPEN) or from 0.800V

to 1.550V with 25mV steps (VID_SEL = GND;

VID5 drives an optional +25mV offset) managingdynamic VID with 0.5% accuracy over line and

temp variations. Additional programmable offset

can be added to the voltage reference with a

single external resistor.

The device assures a fast protection against load

over current and load over/under voltage. An

internal crowbar is provided turning on the low

side mosfet if an over-voltage is detected.

In case of over-current, the system works in

Constant Current mode until UVP.

Selectable current reading adds flexibility in

system design.

TQFP48 (Exposed Pad)

Part Number Package Packing

L6711 TQFP48 Tube

L6711TR TQFP48 Tape & Reel

www.st.com

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Contents L6711

2/50

Contents

1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4

1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Current reading and current sharing control loop . . . . . . . . . . . . . . . . 19

7.1 Low-side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2 Inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.1 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.2 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.3 Integrated thermal sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.1 VID_SEL = OPEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11.2 VID_SEL = GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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L6711 Contents

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12 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

13 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

14 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 33

14.1 UVP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

14.2 Programmable OVP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

14.3 Preliminary OVP protection (Pre-OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

14.4 Over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

14.5 Low side sense overcurrent (CS_SEL=OPEN) . . . . . . . . . . . . . . . . . . . . 35

14.5.1 TON Limited output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

14.5.2 Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14.6 Inductor sense over current (CS_SEL = SGND) . . . . . . . . . . . . . . . . . . . 37

15 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

16 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

16.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

17 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

18 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

18.1 Power connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

18.2 Power connections related. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

18.3 Current sense connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

19 Embedding L6711-based VRDs... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

20 TQFP48 Mechanical data & package dimensions . . . . . . . . . . . . . . . . 48

21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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Typical application circuit and block diagram L6711

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1 Typical application circuit and block diagram

1.1 Application circuit

Figure 1. Typical application circuit for LS MOSFET current sense

FBR

FBG

L1

45

46

47

BOOT1

UGATE1

PHASE1

LGATE12

PGND13

CS1-14

CS1+15

Rg

Rg

HS1

LS1

L2

44

43

42

BOOT2

UGATE2

PHASE2

LGATE240

PGND239

CS2-16

CS2+17

Rg

Rg

HS2

LS2

L3

34

33

32

BOOT3

UGATE3

PHASE3

LGATE336

PGND335

CS3-18

CS3+19

Rg

Rg

HS3

LS3

SS_END30

COUT

Vcc_core

LOAD

12

11

N.C. N.C.

4837

VSEN10

FB8

RFB

COMP7

RF

CF

OUTEN13

VID428

VID327

VID226

VID125

VID024

VID_SEL29

VID523

OUTEN

VID4

VID3

VID2

VID1

VID0

VID_SEL

VID5

OVP9

CS_SEL21

TC20

OFFSET6

OSC/FAULT22

VCC4

SGND5,31

VCCDR338

VCCDR241

VCCDR11

LIN

SS_END

VIN

GNDIN

CIN

L

6711

L6711 REF. SCH. (MOSFET)

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Typical application circuit and block diagram L6711

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1.2 Block diagram

Figure 3. Block diagram

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

HS1 HS1 HS2 LS2 HS3 LS3

B

OOT1

U

GATE1

P

HASE1

V

CCDR1

L

GATE1

P

GND1

B

OOT2

U

GATE2

P

HASE2

V

CCDR2

L

GATE2

P

GND2

B

OOT3

U

GATE3

P

HASE3

V

CCDR3

L

GATE3

P

GND3

CURRENT SHARING

CORRECTION

3PHASE

OSCILLATOR

CH3 CURRENT

READING

CH2 CURRENT

READING

CH1 CURRENT

READING

OCP1

OCP2

OCP3

AV

ERAGECURRENT

L6711

CONTROL LOGICAND PROTECTIONS

PWM1 PWM2 PWM3

PWM1 PWM2 PWM3

OUTEN

OCP2

OCP3

OCP1

DIGITAL

SOFT START

TEMPERATURE

COMPENSATION

OFFSET

DAC

WITHDYNAMIC

VIDCONTROL

CS_SEL

CS3-

CS3+

CS2-

CS2+

CS1-

CS1+

SGND

VCC

VCC

OVP

OVP

12.5AOUTEN

OSC

OUTEN

TC

VID0

VID1

VID2

VID3

VID4

VID5

VID_SEL

ITC

IDROOP

CS_SEL

VCCDR

VCC

1.240V

IOS

IOS

OFFSET

FB

COMP

VSEN

FBR

FBG

OVP115% / OVP

SS_END

64k

64k

64k

64k

ERROR AMPLIFIER

REMOTE

BUFFER

TOTAL CURRENT

CURRENT SHARING

CORRECTION

CURRENT SHARING

CORRECTION

IFB

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L6711 Pins description and connection diagrams

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2 Pins description and connection diagrams

2.1 Pin descriptions

Figure 4. Pins connection (top view)

48

47

46

45

44

43

42

41

40

39

38

37

13

14

15

16

17

18

19

20

21

22

23

24

36 35 34 33 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8 9 10 11 12

OUTEN

CS1-

CS1+

CS2-

CS2+

CS3-

CS3+

TC

CS_SEL

OSC / FAULT

VID5

VID0

N.C.

PHASE1

UGATE1

BOOT1

BOOT2

UGATE2

PHASE2

VCCDR2

LGATE2

PGND2

VCCDR3

N.C.

LGATE3

PGND3

BOOT3

UGATE3

PHASE3

SGND

SS_

END

VID_

SEL

VID4

VID3

VID2

VID1

VCCDR1

LGATE1

PGND1

VCC

SGND

OFFSET

COMP

FB

OVP

VSEN

FBR

FBG

L6711

Table 1. Pins description

N Name Description

1 VCCDR1

Channel 1 LS driver supply: it can be varied from 5V to 12V buses.

It must be connected together with other VCCDRx pins.

Filter locally with at least 1F ceramic cap vs. PGND1.

2 LGATE1Channel 1 LS driver output.

A little series resistor helps in reducing device-dissipated power.

3 PGND1Channel 1 LS driver return path.

Connect to Power Ground Plane.

4 VCC Device supply voltage. The operative supply voltage is 12V 15%.Filter with 1F capacitor (Typ.) vs. SGND.

5 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground.

6 OFFSET

Offset programming pin, internally fixed at 1.240V.

Short to SGND to disable the offset generation or connect through a resistor ROFFSETto

SGND to program an offset (positive or negative, depending on TC status) to the regulated

output voltage as reported in the relative section.

7 COMPThis pin is connected to the error amplifier output and is used to compensate the controlfeedback loop.

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8 FB

This pin is connected to the error amplifier inverting input and is used to compensate the

voltage control feedback loop.

Connecting a resistor between this pin and VSEN pin allows programming the droop effect.

9 OVP

Over Voltage protection setup pin: it allows programming the OVP intervention.

Internally pulled-up to 5V, it sources a constant 12.5A current.

Leaving the pin floating the OVP threshold is set to 115% (Typ.) of the programmed voltage

Connecting a resistor ROVPto SGND, it sets the OVP threshold to a fixed programmable

voltage (see relevant section for further details). Filter with 10nF vs. SGND in this case.

10 VSEN

Manages Over&Under-voltage conditions. It is internally connected with the output of the

Remote Sense Buffer for Remote Sense of the regulated voltage.

If no Remote Sense is implemented, connect it directly to the regulated voltage in order to

manage OVP and UVP.

11 FBR Remote sense buffer non-inverting input.It has to be connected to the positive side of the load to perform a remote sense.

12 FBGRemote sense buffer inverting input.

It has to be connected to the negative side of the load to perform a remote sense.

13 OUTEN

Output Enable pin; internally 3V pulled-up, it can be pulled-up with a resistor up to 3.3V.

If forced to a voltage lower than 0.3V, the device stops operation with all mosfets OFF: all the

protections are disabled in this condition except pre-OVP.

Cycle this pin to recover latch from protections; filter with 1nF (Typ.) capacitor vs. SGND.

14 CS1-

Channel 1 Current Sense Negative Input pin.

It must be connected through an Rg resistor to the LS mosfet drain (or to the LS-side of the

sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed

(CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the output-side ofthe output inductor (or the output-side of the sense resistor used and placed between thechannel 1 inductor and the output of the converter) through Rg resistor.

The net connecting the pin to the sense point must be routed as close as possible to the CS1+

net in order to couple in common mode any picked-up noise.

15 CS1+

Channel 1 Current Sense Positive Input pin.

It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side of

the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed

(CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the phase-side of

the output inductor (or the inductor-side of the sense resistor used and placed between the

channel 1 inductor and the output of the converter) through Rg resistor and an R-C network

across the inductor.

The net connecting the pin to the sense point must be routed as close as possible to the CS1-


16 CS2-




(CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the output-side of

the output inductor (or the output-side of the sense resistor used and placed between the

channel 2 inductor and the output of the converter) through Rg resistor.

The net connecting the pin to the sense point must be routed as close as possible to the CS2+


Table 1. Pins description (continued)

N Name Description

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17 CS2+


It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side ofthe sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed







18 CS3-




(CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the output-side of

the output inductor (or the output-side of the sense resistor used and placed between the

channel 3 inductor and the output of the converter) through Rg resistor.The net connecting the pin to the sense point must be routed as close as possible to the CS3+


19 CS3+


It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side of

the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed







20 TC

Temperature Compensation pin.

Connect through a resistor RTCand filter with 10nF vs. SGND to program the temperature

compensation effect.

Short to SGND to disable the compensation effect.

21 CS_SEL

Current Reading Selection pin, internally 5V pulled-up.

Leave floating to sense current across low-side mosfets or a sense resistor placed in series to

the LS mosfet source. Maximum duty cycle is dynamically limited and Track&Hold is enabled

to assure proper reading of the current.

Short to SGND to read current across inductors or a sense resistor placed in series to the

output inductors. No duty cycle limitation and no Track&Hold performed in this case.

22OSC /

FAULT

Oscillator pin.

It allows programming the switching frequency of each channel: the equivalent switchingfrequency at the load side results in being tripled.

Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced)

from (into) the pin with an internal gain of 6kHz/A (See relevant section for details).

If the pin is not connected, the switching frequency is 150kHz for each channel (450kHz on the

load).

The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this

condition, cycle VCC or the OUTEN pin.


N Name Description

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Pins description and connection diagrams L6711

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23, 24

to 28

VID5,

VID0-4

Voltage IDentification pins.

Internally pulled-up to 3V, connect to SGND to program a logic 0 while leave floating (as wellas pull-up with a resistor up to 3.3V) to program a logic 1.

They are used to program the output voltage as specified in Table 5and Table 6together with

VID_SEL and to set the OVP/UVP protection thresholds accordingly.

See relevant section for details about DAC selection.

29 VID_SEL

VID_SELect pin. Through this pin it is possible to select the DAC table used for the regulation.

Leave floating to use a VRD10.x compliant DAC (See Table 1) while short to SGND to use a

VRM-Hammer compliant DAC (See Table 3).

See relevant section for details about DAC selection.

30 SS_ENDSoft start end signal. It is an open collector output, set free after finishing the soft start.

Pull-up with a resistor to a voltage lower than 5V, if not used may be left floating.

31 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground.

32 PHASE3Channel 3 HS driver return path. It must be connected to the HS3 mosfet source and provides

the return path for the HS driver of channel 3.

33 UGATE3Channel 3 HS driver output.


34 BOOT3

Channel 3 HS driver supply. This pin supplies the relative high side driver.

Connect through a capacitor (100nF Typ.) to the PHASE3 pin and through a diode to VCC

(cathode vs. boot).



36 LGATE3

Channel 3 LS driver output.


37 N.C. Not internally connected.

38 VCCDR3






40 LGATE2Channel 2 LS driver output.


41 VCCDR2








44 BOOT2


Connect through a capacitor (100nF Typ.) to the PHASE2 pin and through a diode to VCC

(cathode vs. boot).


N Name Description

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45 BOOT1


Connect through a capacitor (100nF Typ.) to the PHASE1 pin and through a diode to VCC(cathode vs. boot).





48 N.C. Not internally connected.

PADTHERMAL

PAD

Thermal pad connects the silicon substrate and makes a good thermal contact with the PCB to

dissipate the power necessary to drive the external mosfets. Connect to the GND plane with

several vias to improve thermal conductivity.


N Name Description

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Maximum ratings L6711

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3 Maximum ratings

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

VCC, VCCDRx To PGNDx 15 V

VBOOTx-

VPHASExBoot Voltage 15 V

VUGATEx-

VPHASEx15 V

LGATEx, PHASEx to PGNDx-0.3 to

Vcc+0.3V

VID0 to VID5 -0.3 to 5 V

All other pins to PGNDx -0.3 to 7 V

VPHASEx Sustainable Positive Peak Voltage. T


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L6711 Electrical specifications

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4 Electrical specifications

Table 4. Electrical characteristcs

(VCC=12V15%, TJ= 0C to 70C unless otherwise specified)

Symbol Parameter Test condition Min. Typ. Max. Unit

VCCsupply current

ICC VCC supply currentHGATEx and LGATEx open

VCCDRx=VBOOTx=12V18 23 mA

ICCDRxVCCDRx supply

currentLGATEx open; VCCDRx=12V 1.5 2 mA

IBOOTx BOOTx supply current

HGATEx open;PHASEx to

PGNDx

VCC=BOOTx=12V

1 1.5 mA

Power-ON

Turn-On VCC

thresholdVCC Rising; VCCDRx=5V 8.2 9.2 10.2 V

Turn-Off VCC

thresholdVCC Falling; VCCDRx=5V 6.5 7.5 8.5 V

Turn-On VCCDRx

Threshold

VCCDRx Rising

VCC=12V4.2 4.4 4.6 V

Turn-Off VCCDRx

Threshold

VCCDRx Falling

VCC=12V4.0 4.2 4.4 V

Oscillator and inhibit

fOSC Initial AccuracyOSC = OPEN

OSC = OPEN; TJ=0 to 125C

135

127150

165

178

kHz

kHz

OUTENIL Output Enable

Threshold

Input Low 0.3 V

OUTENIH Input High 0.5 V

dMAX Maximum duty cycle

OSC = OPEN: CS_SEL =

OPEN;

IFB=0

72 80 %

OSC = OPEN; CS_SEL =

OPEN;

IFB=105A

30 40 %

Vosc Ramp Amplitude 3 V

FAULT Voltage at pin OSC OVP or UVP Active 4.70 5.0 5.30 V

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Electrical specifications L6711

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Reference and DAC

Output Voltage

Accuracy

VRD10.x DAC

FBR = VOUT; FBG = GNDOUT-0.5 - 0.5 %

HAMMER DAC

FBR = VOUT; FBG = GNDOUT-0.6 - 0.6 %

IVID,

IVID_SEL

VID, VID_SEL

pull-up Current

VIDx = GND

VID_SEL=GND3 4.5 6 A

VID, VID_SEL

pull-up Voltage

VIDx = OPEN

VID_SEL = OPEN3 V

VIDIL

VID, VID_SEL

ThresholdInput Low 0.4 V

VIDIH Input High 0.8 V

Error amplifier

A0 DC Gain 80 dB

SR Slew-Rate COMP = 10pF 15 V/ s

Differential amplifier (remote buffer)

DC Gain 1 V/V

CMRRCommon Mode

Rejection Ratio40 dB

SR Slew Rate VSEN = 10pF 15 V/ s

Differential current sensing and offset

ICSx- Bias Current ILOAD= 0 50 A

ICSx+ Bias Current 50 A

Current Sense

Mismatch-3 - 3 %

IOCTHOver Current

ThresholdICSx-(OCP)-ICSx-(0) 30 35 40 A

IFB

Droop Current

deviation from nominalvalue

OFFSET = TC = SGND

IFB= 0 to 75A -3.5 - +3.5 A

Offset Current

ILOAD=0; IOFFSET =100A;

TC = SGND-90 -100 -110 A

ILOAD=0; IOFFSET =100mA;

TC Enabled90 100 110 A

IOFFSETOFFSET pin Current

Range0 - 250 A

VOFFSET OFFSET pin Voltage IOFFSET= 0 to 250A 1.240 V

Table 4. Electrical characteristcs (continued)



NFOx AV

IAV G------------------------------

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L6711 Electrical specifications

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Thermal sensor

VTCTC Voltage at

Tamb= 27C

RTC=100k

RTC=50k

RTC=5k

0.612

0.593

0.530

0.645

0.625

0.558

0.677

0.656

0.586

V

Gate drivers

tRISE HGATEHigh Side

Rise Time

BOOTx-PHASEx=10V;

CHGATExto PHASEx=3.3nF15 30 ns

IHGATExHigh Side

Source CurrentBOOTx-PHASEx=10V 2 A

RHGATExHigh Side

Sink Resistance BOOTx-PHASEx=12V; 1.5 2 2.5

tRISE LGATELow Side

Rise Time

VCCDRx=10V;

CLGATExto PGNDx=5.6nF30 55 ns

ILGATExLow Side

Source CurrentVCCDRx=10V 1.8 A

RLGATExLow Side

Sink ResistanceVCCDRx=12V 0.7 1.1 1.5

Protections and SS_END

VSS_ENDL SS_END Voltage Low ISS_END= -4mA 0.4 V

ISS_ENDH SS_END Leakage VSS_END= 5V 1 A

UVP Under Voltage Trip VSEN Falling 55 60 65 %

OVP

Over Voltage

Threshold

VSEN Rising;

OVP = OPEN112 115 118 %

Over Voltage

Threshold

VSEN Rising;

OVP = 90kto SGND1.54 1.64 1.74 V

Preliminary

OVP

Turn-ON Threshold VCC = VCCDRx Rising 4 V

PreOVP Threshold FBR Rising 1.8 V

PreOVP Hysteresis 350 mV

Table 4. Electrical characteristcs (continued)



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VID Tables L6711

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5 VID Tables

Note: Since the VIDx pins program the maximum output voltage, according to VRD 10.x specs,

the device automatically regulates to a voltage 19mV lower avoiding use of any external

component to lower the regulated voltage. This improves the system tolerance performance

since the reference already offset is trimmed during production within 0.5%.

Table 5. Voltage IDentification (VID) Codes.

VID_SEL = OPEN (VRD 10.x DAC with -19mV auto-offset)

VID5 VID4 VID3 VID2 VID1 VID0Output

(V)VID5 VID4 VID3 VID2 VID1 VID0

Output

(V)

0 0 1 0 1 0 0.8185 0 1 1 0 1 0 1.1935

1 0 1 0 0 1 0.8310 1 1 1 0 0 1 1.2060

0 0 1 0 0 1 0.8435 0 1 1 0 0 1 1.2185

1 0 1 0 0 0 0.8560 1 1 1 0 0 0 1.2310

0 0 1 0 0 0 0.8685 0 1 1 0 0 0 1.2435

1 0 0 1 1 1 0.8810 1 1 0 1 1 1 1.2560

0 0 0 1 1 1 0.8935 0 1 0 1 1 1 1.2685

1 0 0 1 1 0 0.9060 1 1 0 1 1 0 1.2810

0 0 0 1 1 0 0.9185 0 1 0 1 1 0 1.2935

1 0 0 1 0 1 0.9310 1 1 0 1 0 1 1.3060

0 0 0 1 0 1 0.9435 0 1 0 1 0 1 1.3185

1 0 0 1 0 0 0.9560 1 1 0 1 0 0 1.3310

0 0 0 1 0 0 0.9685 0 1 0 1 0 0 1.3435

1 0 0 0 1 1 0.9810 1 1 0 0 1 1 1.3560

0 0 0 0 1 1 0.9935 0 1 0 0 1 1 1.3685

1 0 0 0 1 0 1.0060 1 1 0 0 1 0 1.3810

0 0 0 0 1 0 1.0185 0 1 0 0 1 0 1.3935

1 0 0 0 0 1 1.0310 1 1 0 0 0 1 1.4060

0 0 0 0 0 1 1.0435 0 1 0 0 0 1 1.4185

1 0 0 0 0 0 1.0560 1 1 0 0 0 0 1.4310

0 0 0 0 0 0 1.0685 0 1 0 0 0 0 1.4435

1 1 1 1 1 1 OFF 1 0 1 1 1 1 1.4560

0 1 1 1 1 1 OFF 0 0 1 1 1 1 1.4685

1 1 1 1 1 0 1.0810 1 0 1 1 1 0 1.4810

0 1 1 1 1 0 1.0935 0 0 1 1 1 0 1.4935

1 1 1 1 0 1 1.1060 1 0 1 1 0 1 1.5060

0 1 1 1 0 1 1.1185 0 0 1 1 0 1 1.5185

1 1 1 1 0 0 1.1310 1 0 1 1 0 0 1.5310

0 1 1 1 0 0 1.1435 0 0 1 1 0 0 1.5435

1 1 1 0 1 1 1.1560 1 0 1 0 1 1 1.5560

0 1 1 0 1 1 1.1685 0 0 1 0 1 1 1.5685

1 1 1 0 1 0 1.1810 1 0 1 0 1 0 1.5810

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L6711 VID Tables

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Table 6. Voltage IDentification (VID) Codes.

VID_SEL = SGND (Hammer DAC)

HAMMER DAC HAMMER DAC +25mV

VID5 VID4 VID3 VID2 VID1 VID0Output

(V)VID5 VID4 VID3 VID2 VID1 VID0

Output

(V)

1

0 0 0 0 0 1.550

0

0 0 0 0 0 1.575

0 0 0 0 1 1.525 0 0 0 0 1 1.550

0 0 0 1 0 1.500 0 0 0 1 0 1.525

0 0 0 1 1 1.475 0 0 0 1 1 1.500

0 0 1 0 0 1.450 0 0 1 0 0 1.475

0 0 1 0 1 1.425 0 0 1 0 1 1.450

0 0 1 1 0 1.400 0 0 1 1 0 1.425

0 0 1 1 1 1.375 0 0 1 1 1 1.400

0 1 0 0 0 1.350 0 1 0 0 0 1.375

0 1 0 0 1 1.325 0 1 0 0 1 1.350

0 1 0 1 0 1.300 0 1 0 1 0 1.325

0 1 0 1 1 1.275 0 1 0 1 1 1.300

0 1 1 0 0 1.250 0 1 1 0 0 1.275

0 1 1 0 1 1.225 0 1 1 0 1 1.250

0 1 1 1 0 1.200 0 1 1 1 0 1.225

0 1 1 1 1 1.175 0 1 1 1 1 1.200

1 0 0 0 0 1.150 1 0 0 0 0 1.175

1 0 0 0 1 1.125 1 0 0 0 1 1.150

1 0 0 1 0 1.100 1 0 0 1 0 1.125

1 0 0 1 1 1.075 1 0 0 1 1 1.100

1 0 1 0 0 1.050 1 0 1 0 0 1.075

1 0 1 0 1 1.025 1 0 1 0 1 1.050

1 0 1 1 0 1.000 1 0 1 1 0 1.025

1 0 1 1 1 0.975 1 0 1 1 1 1.000

1 1 0 0 0 0.950 1 1 0 0 0 0.975

1 1 0 0 1 0.925 1 1 0 0 1 0.950

1 1 0 1 0 0.900 1 1 0 1 0 0.925

1 1 0 1 1 0.875 1 1 0 1 1 0.900

1 1 1 0 0 0.850 1 1 1 0 0 0.875

1 1 1 0 1 0.825 1 1 1 0 1 0.850

1 1 1 1 0 0.800 1 1 1 1 0 0.825

1 1 1 1 1 OFF 1 1 1 1 1 OFF

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Device description L6711

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6 Device description

The device is a three phase PWM controller with embedded high current drivers that

provides complete control logic and protections for a high performance step-down DC-DCvoltage regulator optimized for advanced microprocessor power supply. Multi phase buck is

the simplest and most cost-effective topology employable to satisfy the increasing current

demand of newer microprocessors and modern high current DC/DC converters and POLs. It

allows distributing equally load and power between the phases using smaller, cheaper and

most common external power mosfets and inductors. Moreover, thanks to the 120 of phase

shift between each phase, the input and output capacitor count results in being reduced.

Phase interleaving causes in fact input rms current and output ripple voltage reduction and

show an effective output switching frequency increase: the 150kHz free-running frequency

per phase, externally adjustable through a resistor, results tripled on the output.

The controller includes multiple DACs, selectable through an apposite pin (VID_SEL),

allowing compatibility with both VRD 10.x and Hammer specifications, also performing D-

VID transitions accordingly. The output voltage can be precisely selected, programming theVID and VID_SEL pins, from 0.8185V to 1.5810V with 12.5mV binary steps (VRD 10.x

compliant mode - 6 BIT with -19mV offset already programmed during production) or from

0.800V to 1.550V with 25mV steps (VRM Hammer compliant mode - 5 BIT, VID5 programs

a 25mV positive offset in this case), with a maximum tolerance on the output regulated

voltage of 0.5% (0.6% for Hammer) over temperature and line voltage variations.

The device permits easy and flexible system design by allowing current reading across

either inductor or low side mosfet in fully differential mode simply selecting the desired way

through the CS_SEL pin. In both cases, also a sense resistor in series to the related

element can be considered to improve reading precision. The current information read

corrects the PWM output in order to equalize the average current carried by each phase

limiting the error at 3% over static and dynamic conditions unless considering the sensing

element spread.

The device provides a programmable Over-Voltage protection to protect the load from

dangerous over stress and can be externally set to a fixed voltage through an apposite

resistor or it can be set internally with a fixed percentage, latching immediately by turning

ON the lower driver and driving high the FAULT pin. Furthermore, preliminary OVP

protection also allows the device to protect load from dangerous OVP when VCC is not

above the UVLO threshold.

Over-Current protection provided, with an OC threshold for each phase, causes the device

to enter in constant current mode until the latched UVP. Depending on the reading mode

selected, the device keeps constant the peak (inductor sensing) or the valley (LS sensing)

of the inductor current ripple.

The device drives high the FAULT pin after each latching event: to recover it is enough tocycle VCC or the OUTEN pin.

A compact 7x7mm body TQFP48 package with exposed thermal pad allows dissipating the

power to drive the external mosfet through the system board.

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L6711 Current reading and current sharing control loop

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7 Current reading and current sharing control loop

The device embeds a flexible, fully-differential current sense circuitry that is able to read

across both low side or inductor parasitic resistance or across a sense resistor placed inseries to that element. The fully-differential current reading rejects noise and allows placing

sensing element in different locations without affecting the measurement's accuracy. The

kind of sense element can be simply chosen through the CS_SEL pin: setting this pin free,

the LS mosfet is used while shorting it to SGND, the inductor will be used instead. Details

about connections are shown in Figure 5.

The high bandwidth current sharing control loop allows current balance even during load

transients: a current reference equal to the average of the read current (I AVG) is internally

built and the error between the read current and this reference is converted to a voltage that

with a proper gain is used to adjust the duty cycle whose dominant value is set by the

voltage error amplifier.

Figure 5. Current reading connections selectable through CS_SEL pin.

7.1 Low-side current readingLeaving CS_SEL pin OPEN, the current flowing trough each phase is read using the voltage

drop across the low side mosfets RdsONor across a sense resistor in its series and it is

internally converted into a current. The transconductance ratio is issued by the external

resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points

(see Figure 6right). The proprietary current sense circuit tracks the current information for a

time TTRACK= TSW/3 (TSW= 1/FSW) centered in the middle of the low-side mosfet

conduction time (OFF Time, see Figure 6left) and holds the tracked information during the

rest of the period.

This device sources a constant 50A current from the CSx+ pin: the current reading circuitry

uses this pin as a reference and the reaction keeps the CSx- pin to this voltage during the

reading time (an internal clamp keeps CSx+ and CSx- at the same voltage sinking from theCSx- pin the necessary current during the hold time; this is needed when LS mosfet RdsON

sense is implemented to avoid absolute maximum rating overcome on CSx- pin). The

current that flows from the CSx- pin is then given by the following equation (SeeFigure 6-

right):

where:

RdsONis the on resistance of the low side mosfet and Rg is the transconductance resistor

used between CSx- and CSx+ pins toward the reading points; IPHASExis the current carried

by the relative phase and I INFOxis the current information signal reproduced internally.

L RL

Rg(RC)

Cg

Rg

CSx+

CSx-

PHASEx

OUT

IPHASECS_SEL

Rg(a)

LS MOSFET Current Sense Inductor Current Sense

CSx-

CSx+

LGATEx

Rg

Rg

IPHASE

CS_SEL

ICSx- 50ARdsON

Rg----------------- IPHASEx+ 50A IINFOx+= = IINFOx

RdsONRg

----------------- IPHASEx=

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Current reading and current sharing control loop L6711

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50A offset allows negative current reading, enabling the device to check for dangerous

returning current between the phases assuring the complete current equalization. From the

current information of each phase, information about the total current delivered (IDROOP=

IINFO1+ IINFO2+ IINFO3) and the average current for each phase (IAVG= (IINFO1+ IINFO2+

IINFO3)/3 ) is taken. IINFOXis then compared to IAVGto give the correction to the PWMxoutput in order to equalize the current carried by the three phases.

Figure 6. Current reading across LS mosfet: timing (left) and circuit (right) for each

phase.

7.2 Inductor current reading

Shorting CS_SEL pin to SGND, the current flowing trough each phase is read using the

voltage drop across the output inductor or across a sense resistor (R SENSE) in its series and

internally converted into a current. The transconductance ratio is issued by the external

resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points

(see Figure 5right).

The current sense circuit always tracks the current sensed and still sources a constant 50A

current from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this

voltage. To correctly reproduce the inductor current an R-C filtering network must be

introduced in parallel to the sensing element.

The current that flows from the CSx- pin is then given by the following equation (See Figure

7):

Where IPHASExis the current carried by the relative phase.

Considering now to match the time constant between the inductor and the R-C filter applied

(Time constant mismatches cause the introduction of poles into the current reading networkcausing instability. Moreover, it is also important for the load transient response and to let

the system show resistive equivalent output impedance), it results:

where

IINFOxis the current information reproduced internally.

50A offset allows negative current reading, enabling the device to check for dangerous

returning current between the phases assuring the complete current equalization. From the

0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

IPHASEx

ILSx

IINFOx

TTRACK TSW

CSx+

CSx-

LGATEx IPHASEx

50A

ICSx-Rg

Rg

ICSx- 50ARLRg-------

1 sL

RL-------+

1 s Rg RC( ) Cg +------------------------------------------------

IPHASEx +=

Rg RC( ) Cg ICSx- 50ARLRg-------- IPHASEx+ 50A IINFOx+= = IINFOx IPHASEx

RLRg--------=

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L6711 Current reading and current sharing control loop

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current information of each phase, information about the total current delivered (IDROOP=

IINFO1+IINFO2+ IINFO3) and the average current for each phase (IAVG= (IINFO1+ IINFO2+

IINFO3)/3) is taken. IINFOXis then compared to IAVGto give the correction to the PWM output

in order to equalize the current carried by the three phases.

Since Rg is designed considering the OC protection, to allow further flexibility in the systemdesign, the resistor in series to CSx+ can be split in two resistors as shown in Figure 7.

Figure 7. Inductor current sense

Design Equations:

Rg RC( )L

RL Cg------------------=

Rg RC( ) Rg a( )+ Rg=

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DAC Selection L6711

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8 DAC Selection

The device embeds a selectable DAC that allows the output voltage to have a tolerance of

0.5% (0.6% for Hammer DAC) recovering from offsets and manufacturing variations. TheVID_SEL pin selects the DAC table used to program the reference for the regulation as

shown in Table .

VID pins are inputs of an internal DAC that is realized by means of a series of resistors

providing a partition of the internal voltage reference. The VID code drives a multiplexer thatselects a voltage on a precise point of the divider. The DAC output is delivered to an

amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, VPROG).

Internal pull-ups are provided (realized with a 5A current generator up to 3V Typ); in this

way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0"

it is enough to short the pin to SGND.

Programming the "11111x" code (NOCPU, VID5 is irrelevant), the device shuts down: all

mosfets are turned OFF and SS_END is shorted to SGND. Removing the code causes the

device to restart.

The voltage identification (VID) pin configuration also sets the Over / Under Voltage

protection (OVP/UVP) thresholds.

Table 7. DAC Selection

VID_SEL Selected DAC

OPEN

VRM / VRD 10.x DAC.

Output voltage ranges from 0.8185V to 1.5810V with 12.5mV steps (See Table 5).

Since the VIDx pins program the maximum output voltage, according to VRD 10.x

specs, the device automatically regulates with 19mV offset avoiding use of any external

component to lower the regulated voltage.

Since the -19mV offset is programmed during the production stage, no further error isintroduced to generate the offset since it is automatically recovered during the trimming

stage.

SGND

VID5 Hammer DAC

OPEN Output voltage ranges from 0.800V to 1.550V with 25mV steps (See Table 6).

SGND

Output voltage ranges from 0.825V to 1.575V with 25mV steps (See Table 6).

Since the +25mV offset is programmed during the production stage, no further

error is introduced to generate the offset since it is automatically recovered

during the trimming stage.

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L6711 Remote voltage sense

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9 Remote voltage sense

The device embeds a Remote Sense Buffer to sense remotely the regulated voltage without

any additional external components. In this way, the output voltage programmed isregulated between the remote buffer inputs compensating motherboard or connector

losses. The very low-offset amplifier senses the output voltage remotely through the pins

FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense)

and reports this voltage internally at VSEN pin with unity gain eliminating the errors.

Keeping the FBR and FBG traces parallel and guarded by a power plane results in common

mode coupling for any picked-up noise.

If remote sense is not required, it is enough connecting the resistor RFBdirectly to the

regulated voltage: VSEN becomes not connected and still senses the output voltage

through the remote buffer. In this case the FBG and FBR pins must be connected anyway to

the regulated voltage (See Figure 8).

Warning: The remote buffer is included in the trimming chain in order

to achieve 0.5% accuracy (0.6% for the Hammer DAC) on the

output voltage when the RB is used: eliminating it from the

control loop causes the regulation error to be increased by

the RB offset worsening the device performances!

Figure 8. Remote buffer connections

RB used (up to 0.5% Accuracy) RB Not Used (Precision worsened)

VID

FB COMP VSEN

64k

FBR FBG

64k

64k

64k

RF CF

RFB

To Vcore(Remote Sense)

VID

FB COMP VSEN

64k

FBR FBG

64k

64k

64k

RF CF

RFB

To Vcore

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Voltage positioning L6711

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10 Voltage positioning

Output voltage positioning is performed by selecting the reference DAC and by

programming the different contributors to the IFBcurrent (see Figure 9). This current,sourced from the FB pin, causes the output voltage to vary according to the external RFB

resistor: this allows programming precise output voltage variations depending on the

sensed current (Droop Function) as well as offsets for the regulation.

The three contributors to the IFBcurrent value are:

Droop Function (green);

Offset (red);

Integrated Temperature Compensation (fuchsia).

Moreover, the embedded Remote Buffer allows to precisely programming the output voltage

offsets and variations by recovering the voltage drops across distribution lines.

The output voltage is then driven by the following relationship (IOFFSETsign depends on TCsetting):

Figure 9. Voltage positioning and droop function

10.1 Droop function

Droop function allows the device to satisfy the requirements of high performance

microprocessors, reducing the size and the cost of the output capacitor. This method

"recovers" part of the drop due to the output capacitor ESR in the load transient, introducing

a dependence of the output voltage on the load current: a static error proportional to the

output current causes the output voltage to vary according to the sensed current. As shown

in figure 4-right, the ESR drop is present in any case, but using the droop function the total

deviation of the output voltage is minimized.The information about the total current delivered (IDROOP) is sourced from the FB pin (see

Figure 9): connecting a resistor between this pin and VSEN (i.e. the output voltage), the total

current information flows only in this resistor because the compensation network between

FB and COMP has always a capacitor in series (CF, see Figure 9). The voltage regulated is

then equal to:

Where VID is the reference programmed through VIDx and VID_SEL (Only the IDROOP

contribute to IFBhas been considered).

VID RFB IFB VID RFB IDROOP IOFFSET ITC( )=

VMAX

VMIN

VNOM

ESR DROP

RESPONSE WITHOUT DROOP

RESPONSE WITH DROOP

IDROOP

VID

FB COMP

IFB

VSEN

64k

FBR FBG

64k

64k

64k

RF CF

RFB


IOFFSET

ITC

VOU T VID RFB IDROOP=

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L6711 Voltage positioning

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Since IDROOPdepends on the current information about the three phases, the output

characteristic vs. load current is given by:

Where RSENSEis the chosen sensing element resistance (Inductor DCR or LS RdsON), IOUT

is the output current of the system and R DROOPis its equivalent output resistance (The

whole power supply can be then represented by a "real" voltage generator with a voltage

value of VID and an equivalent series resistance RDROOP).

RFBresistor can be also designed according to the RDROOPspecifications as follow:

Figure 10. Voltage positioning with offset

10.2 Offset

The OFFSET pin allows programming a positive or a negative offset (VOS) for the output

voltage.

When the Integrated Thermal Sensor is disabled (TC = SGND) a resistor ROFFSET

connected vs. SGND increases the output voltage: since the pin is internally fixed at 1.240V,

the current programmed by the resistor ROFFSETis mirrored and then properly subtracted

from the IFBcurrent (see Figure 10) as follow (Only the IOFFSETcontribute to IFBhas been

considered):

The device will add the programmed offset VOSto the output programmed voltage

(considering now also the droop effect) subtracting the relative offset current from the

feedback current IFB:

VID RFB IDROOP

VID RFB

RSENSE

Rg---------------------

IOU T

VID RDROOP IOU T= =

RFB RDROOPRg

RSENSE---------------------=

1.240V

IOFFSET

1:1

ROFFSET

OFFSETTC

IDROOP

VID

FB COMP

IFB

VSEN

64k

FBR FBG

64k

64k

64k

RF CF

RFB


IOFFSET

VOU T VID RFB IOFFSET+ VID RFB1.240V

ROFFSET------------------------

+ VID VOS+= = =

VID RFB IFB VID RFB IDROOP IOFFSET( )= VID RFB IOFFSET RDROOP IOU T+=

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Voltage positioning L6711

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Offset resistor can be designed by considering the following relationship (RFBis fixed by the

Droop effect):

Offset automatically given by the DAC selection or by VID5 when VID_SEL=SGND differs

from the offset implemented through the OFFSET pin: the built-in feature is trimmed in

production and assures 0.5% error (0.6% for the Hammer DAC) over load and line

variations while implementing the same offset through the OFFSET pin causes additional

errors to be considered in the total output voltage precision.

When the Integrated Thermal Sensor is enabled (see Figure 11and following section), the

pin programs, in the same way as before, a negative offset. This is to compensate the

positive native offset introduced by the ITS. The effect of the programmed offset on the

output voltage results (IOFFSETis now added to IFBand no more subtracted as before):

Offset resistor is designed to compensate the ITS native offset as described in the following

section.

The Offset function can be disabled by shorting the pin to SGND.

Figure 11. Voltage positioning with integrated thermal sensor

10.3 Integrated thermal sensor

Current sense elements have non-negligible temperature variations: considering either

inductor or LS mosfet sense, the sensing elements modify proportionally to varying

temperature. As a consequence, the sensed current is subjected to a measurement error

that causes the regulated voltage to vary accordingly.

To recover from this temperature related error, a temperature compensation circuit is

integrated into the controller: the internal temperature is sensed and the droop current is

corrected (according to a scaling external resistor RTC) in order to keep constant the

regulated voltage.

ROFFSET

1.240V

VOS-------------------

RFB=

VOU T VID RFB IOFFSET VID RFB1.240

ROFFSET------------------------

VID VOS= = =

1.240V

IOFFET

ITC

1:1

VTC=A+B(TJ-25)

RTC ROFFSET

OFFSETTC

1:1

IDROOP

VID

FB COMP

IFB

VSEN

64k

FBR FBG

64k

64k

64k

RF CF

RFB


IOFFSET

ITC

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The ITS circuit subtracts from the IFBcurrent a current proportional to the sensed

temperature as follow (see Figure 11, Only the IDROOPand ITCcontributes to IFBhave been

considered):

where

where A and B are positive constants depending on the value of the external resistor R TC

(see Figure 12), TJis the device junction temperature and TMOSis the mosfet (or the used

sensing element) temperature.

The resistor RTCcan be designed in order to zero the temperature influence on the output

voltage at a fixed current as follow:

obtaining the following relationship:

where RSENSEis the sensing element resistance value (at TMOS= 25C), B is the constant

obtainable from

Figure 12, kTis the Temperature Coupling Coefficient between the sensing element and the

Controller (it results KT= (TJ-25)/(TMOS-25)) and is the Temperature Coefficient of the

sensing element. Since RTCdepends from the constant B depending in turn from RTC, an

iterative process is required to properly design the RTCvalue. As a consequence of the

nature of the thermal sensor, a negative offset is needed to compensate the native offset

introduced by the ITS at a referenced temperature Tref and it is obtainable by connecting a

ROFFSETresistor between the OFFSET pin and SGND as follow:

To disable this function, short the pin to SGND.

Figure 12. Integrated thermal sensor constant vs. external resistor RTC

VOU T T,IOU T( ) VID RFBRSENSE TMOS( )

Rg------------------------------------------ IOU T ITC TJ( )=

ITC TJ( )1

RTC----------- A B TJ 25( )+[ ]=

RFBRSENSE TMOS 25( )

Rg------------------------------------------------------------------- IOU T

RFBRTC----------- B TJ 25( ) + 0=

RTCRg

RSENSE---------------------

B kT

IOU T--------------------=

IOFFSET ITC Tre f( )A B Tre f 25( )+

RTC----------------------------------------------= =

450

475

500

525

550

575

600

625

650

0 10 20 30 40 50 60 70 80 90 100

1.50

1.60

1.70

1.80

1.90

2.00

0 10 20 30 40 50 60 70 80 90 100A [mV] vs. RTC[K] B [mV/C] vs. RTC[K]

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Dynamic VID transitions L6711

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11 Dynamic VID transitions

The device is able to manage Dynamic VID Code changes that allow Output Voltage

modification during normal device operation.

OVP and UVP signals are masked during every VID transition and they are re-activated

after the transition finishes.

When changing dynamically the regulated voltage (D-VID), the system needs to charge or

discharge the output capacitor accordingly. This means that an extra-current ID-VIDneeds to

be delivered, especially when increasing the output regulated voltage and it must be

considered when setting the over current threshold. This current result:

where dVOUTis the selected DAC LSB (12.5mV for VRD10.x or 25mV for Hammer DAC)

and TVIDis the time interval between each LSB transition.

Overcoming the OC threshold during the dynamic VID causes the device to enter the

constant current limitation slowing down the output voltage dV/dt also causing the failure in

the D-VID test.

The way in which the device modifies the reference depends on the VID_SEL status and

then on the kind of DAC selected.

Figure 13. Dynamic VID transition, VRD10.x DAC

ID VIDCOU T dVOU T

dTVI D--------------------------------------=

Tsw/3

x 4 Step VID TransitionVRD10.x DAC

t

t

t

VID

Sampled

VID

Sampled

VID

Sampled

RefMoved(1)

RefMoved(2)

RefMoved(3)

RefMoved(4)

VID

Sta

ble

VID [0,5]

Int. Reference

Vout

Tsw

VID

Sampled

VID

Sampled

RefMoved(1)

RefMoved(1)

RefMoved(1)

VID

Sampled

VID

Sampled

4 x 1 Step VID Transition - VRD10.x DAC

TVID

VID

Sampled

VID

Sampled

VID

Sampled

VID

Sampled

VID

Sampled

VID

Sta

ble

VID

Sta

ble

VID

Sta

ble

RefMoved(1)

VID

Sampled

VID

Sampled

VID

Sta

ble

VID

Sampled

VID

Sampled

VID

Sampled

t

VID Clock

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11.1 VID_SEL = OPEN.

Selecting the VRD10.x DAC, the device checks for VID code modifications on the rising

edge of a clock that is three times the switching frequency of each phase and waits for a

confirmation on the following falling edge. Once the new code is stable, on the next rising

edge, the reference starts stepping up or down in LSB increments (12.5mV) every clock

cycle (still 3FSW) until the new VID code is reached. During the transition, VID code

changes are ignored; the device re-starts monitoring VID after the transition has finished on

the next rising edge available.

Warning: if the new VID code is more than 1 LSB higher than the

previous, the device will execute the transition stepping the

reference with a frequency equal to 3FSWuntil the new code

has reached: for this reason it is recommended to carefully

control the VID change rate in order to carefully control the

slope of the output voltage variation.

Warning: DVID sample and hold clock depends on the switching

frequency FSW. To correctly perform DVID transition so

following the VID change rate, it is required to have at least 2

complete cycles of the FDVIDclock between every VID

transition. If the VID update-rate is, for example, 5s, the

minimum operating frequency results to be FSW> 133kHz.

Figure 14. Dynamic VID Transition, Hammer DAC

4 Step VID Transition - Hammer DAC

t

t

t

VID

Sampled

VID

Changed

VID

Sampled

VID [0,5]

Int. Reference

Vout

Tsw

RefMoved(1)

RefMoved(2)

RefMoved(3)

RefMoved(4)

VID

Sampled

t

VID

Stable

VID

Sampled

VID Clock

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11.2 VID_SEL = GND.

Selecting the HAMMER DAC, the device checks for VID code modifications on the rising

edge of a clock that is the same frequency of each phase and waits for a confirmation on the

following falling edge. Once the new code is stable, on the next rising edge the reference

starts stepping up or down in LSB increments (25mV) every clock cycle until the new VID

code is reached. During the transition, VID code changes are ignored; the device re-starts

monitoring VID after the transition has finished on the next rising edge.

If the new VID code is more than 1 bit higher than the previous, the device will execute the

transition stepping the reference every switching cycle until the new code has reached

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12 Enable and disable

The device has three different supplies: VCC pin to supply the internal control logic,

VCCDRx to supply the low side drivers and BOOTx to supply the high side drivers. If thevoltage at pins VCC and VCCDRx are not above the turn on thresholds specified in the

Electrical Characteristics, the device is shut down: all drivers keep the mosfets off to show

high impedance to the load. Once the device is correctly supplied, proper operation is

assured but the device can be controlled in different ways:

OUTEN pin. It can be used to control the power sequencing in complex systems.

Setting the pin free, the device implements a soft start up to the programmed voltage.

Shorting the pin to SGND, it resets the device (SS_END is shorted to SGND in this

condition and protections are disabled except pre-OVP) from any latched condition and

also disables the device keeping all the mosfet turned off to show high impedance to

the load. It can be then cycled to recover from any latched condition such as OVP and

UVP.

NOCPU (VID [0;5]=11111x) In this condition (VID5 state is irrelevant) the device isdisabled and keeps all the mosfet turned off to show high impedance to the load.

Nevertheless, it waits for any VID code transition to power up implementing a soft start.

During this condition, SS_END pin is shorted to SGND.

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Soft start L6711

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13 Soft start

During soft start, a ramp is generated increasing the loop reference from 0V to the final

value programmed by VID in 2048 clock periods as shown in

Figure 15. Once the soft start begins, the reference is increased: upper and lower MOS

begin to switch and the output voltage starts to increase with closed loop regulation. At the

end of the digital soft start, the SS_END signal is then driven high.

The Under Voltage comparator is enabled when the reference voltage reaches 0.6V while

Over Voltage Comparator is always enabled during soft start with a threshold equal to the

115% of the programmed reference or the threshold programmed by ROVP(see relevant

section).

Figure 15. Soft start

VCC=VCCDR

VLGATEx

SS_END

VOUT

t

t

t

t

Turn ON threshold

2048 Clock Cycles

(CH1=VOUT; CH2=LGATEx; CH3=SS_END)

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L6711 Output voltage monitor and protections

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14 Output voltage monitor and protections

The device monitors through pin VSEN the regulated voltage in order to manage the OVP /

UVP conditions.

14.1 UVP protection

If the output voltage monitored by VSEN drops below the 60% of the reference voltage for

more than one clock period, the device turns off all mosfets and the OSC/FAULT is driven

high (5V). The condition is latched; to recover it is required to cycle Vcc or the OUTEN pin.

14.2 Programmable OVP protection

Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), the

device provides a programmable Over Voltage protection; when the voltage sensed

overcomes the programmed threshold, the controller permanently switches on all the low-

side mosfets and switches off all the high-side mosfets in order to protect the load. The

OSC/ FAULT pin is driven high (5V) and power supply or OUTEN pin cycling is required to

restart operations.

The OVP threshold is programmed through the OVP pin: leaving the pin floating, it is

internally pulled-up and the threshold is set at 115% (Typ.) of the programmed output

voltage. Connecting the OVP pin to SGND through a resistor ROVP, the OVP threshold

becomes a fixed voltage as follow:

OVPTH= 1.455 ROVP 12.5

14.3 Preliminary OVP protection (Pre-OVP)

While VCC pin is under the turn-ON threshold, a preliminary-OVP protection turns on the

low side mosfets as long as the FBR pin voltage is greater than 1.8V. This protection is

enabled when VCC stays within the device turn-on threshold and the PreOVP turn on

threshold and depends also on the OUTEN pin status as detailed in Figure 16- left.

A simple way to provide protection to the output in all conditions when the device is OFF

(then avoiding the unprotected red region in Figure 16) consists in supplying the controller

through the 5VSBbus as shown in Figure 16- right.

Both Over Voltage and Under Voltage are active also during soft start (see the relevant

section).

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Output voltage monitor and protections L6711

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Figure 16. Output voltage protections and typical principle connections to assure

complete protection.

14.4 Over current

Depending on the current reading method selected, the device limits the peak or the bottom

of the inductor current entering in constant current until setting UVP as below explained.

The Over Current threshold has to be programmed, by designing the Rg resistors, to a safe

value, in order to be sure that the device doesn't enter OCP during normal operation of the

device. This value must take into consideration also the extra current needed during the

Dynamic VID Transition ID-VIDand, since the device reads across mosfets RdsONor inductor

DCR, the process spread and temperature variations of these sensing elements.

Moreover, since also the internal threshold spreads, the Rg design must consider its

minimum value IOCTH(min)as follow:

where IOCPx is the current measured by the current reading circuitry when the device enters

Quasi Constant Current (LS Mosfet Sense) or Constant Current (Inductor Sense), IOCPx

must be calculated starting from the corresponding output current value IOUT(OCP)as follow

(ID-VIDmust also be considered when D-VID are implemented):

where IOUT(OCP)is still the output current value at which the device enters Quasi ConstantCurrent (LS Mosfet Sense) or Constant Current (Inductor Sense),IPPis the inductor current

ripple in each phase and ID-VIDis the additional current required by D-VID (when applicable).

In particular, since the device limits the peak or the valley of the inductor current (according

to CS_SEL status), the ripple entity, when not negligible, impacts on the real OC threshold

value and must be considered.

Vcc

PreOVP TurnON

Vcc TurnON

Preliminary OVP EnabledFBR Monitored

No ProtectionProvided

(OUTEN = 1)

Programmable OVPVSEN Monitored

(OUTEN = 0)

Preliminary OVPFBR Monitored

VCC

VCCDR1

VCCDR2

VCCDR3

+12V

+5VSB

RgIO CP x m ax( ) RS EN SE m ax( )

IO CT H m in( )---------------------------------------------------------------------=

IOCPx=

IO UT O CP( )3

---------------------------

Ipp

2-----------

ID-VID3

-------------- Low Side Mosfet Sense+

IO UT O CP( )3

---------------------------

Ipp

2-----------

ID-VID3

-------------- Inductor DCR Sense+ +

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14.5 Low side sense overcurrent (CS_SEL=OPEN)

The device detects an Over Current condition for each phase when the current information

IINFOxovercomes the fixed threshold of IOCTH(35A Typ). When this happens, the device

keeps the relative LS mosfet on, skipping clock cycles, until the threshold is crossed back

and IINFOx results being lower than the IOCTHthreshold. This implies that the device limits

the bottom of each inductor current ripple.

After exiting the OC condition, the LS mosfet is turned off and the HS is turned on with a

duty cycle driven by the PWM comparator.

Keeping the LS on, skipping clock cycles, causes the on-time subsequent to the exit from

the OC condition to increase. Considering now that the device, with this kind of current

sense, has maximum on-time dependence with the delivered current given by the following

relationship:

Where IOUTis the output current (IOUT = IPHASEx) and TSWis the switching period (TSW

=1/FSW).

This linear dependence has a value at zero load of 0.80 TSWand at maximum current of

0.40 TSWtypical and results in two different over current behaviors of the device:

14.5.1 TONLimited output voltage.

This happens when the maximum ON time is reached before that the current in each phase

reaches IOCPx(IINFOx


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14.5.2 Constant current operation

This happens when the on-time limitation is reached after the valley current in each phase

reaches IOCPx(IINFOx> IOCTH).

The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON untilthe current read becomes lower than IOCPx(IINFOx< IOCTH) skipping clock cycles. The high

side mosfet can be then turned ON with a TONimposed by the control loop after the LS turn-

off and the device works in the usual way until another OCP event is detected.

This means that the average current delivered can slightly increase in Quasi-Constant-

Current operation since the current ripple increases. In fact, the ON time increases due to

the OFF time rise because of the current has to reach the IOCPxbottom. The worst-case

condition is when the ON time reaches its maximum value.

When this happens, the device works in Constant Current and the output voltage decrease

as the load increase. Crossing the UVP threshold causes the device to latch driving high the

OSC pin (Figure 18shows this working condition).

It can be observed that the peak current (Ipeak) is greater than IOCPxbut it can bedetermined as follow:

Where VoutMINis the UVP threshold, (inductor saturation must be considered). When that

threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device

stops working. Cycle the power supply or the OUTEN pin to restart operation.

The maximum average current during the Constant-Current behavior results:

In this particular situation, the switching frequency for each phase results reduced. The ON

time is the maximum allowed (TonMAX) while the OFF time depends on the application:

The transconductance resistor Rg can be designed considering that the device limits the

bottom of the inductor current ripple and also considering the additional current deliveredduring the quasi-constant-current behavior as previously described in the worst case

conditions.

Moreover, when designing D-VID compatible systems, the additional current due to the

output filter charge during dynamic VID transitions must be considered.

where

IPEAK IOCPxVIN VoutMI N

L-------------------------------------- TonMA X+ IOCPx

V IN VoutMI N

L-------------------------------------- 0.40 TSW += =

IMAX,TOT 3 IMA X 3 IOCPxIpeak IOCPx

2-------------------------------------+

= =

TOF F LIpeak IOCPx

Vou t------------------------------------- = F

1

TonMax TOF F+---------------------------------------=


IO CT H m in( )---------------------------------------------------------------------= IOCPx

IO UT O CP( )3

---------------------------

IPP

2------------

ID-VID3

--------------+=

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Figure 18. Constant current operation

14.6 Inductor sense over current (CS_SEL = SGND)

The device detects an over current when the IINFOxovercome the fixed threshold IOCTH.

Since the device always senses the current across the inductor, the IOCTHcrossing willhappen during the HS conduction time: as a consequence of OCP detection, the device will

turn OFF the HS mosfet and turns ON the LS mosfet of that phase until I INFOxre-cross the

threshold or until the next clock cycle. This implies that the device limits the peak of the

inductor current.

In any case, the inductor current won't overcome the IOCPxvalue and this will represent the

maximum peak value to consider in the OC design.

The device works in Constant-Current, and the output voltage decreases as the load

increase, until the output voltage reaches the UVP threshold. When this threshold is

crossed, all mosfets are turned off, the FAULT pin is driven high and the device stops

working. Cycle the power supply or the OUTEN pin to restart operation.

The transconductance resistor Rg can be designed considering that the device limits theinductor current ripple peak. Moreover, when designing D-VID systems, the additional

current due to the output filter charge during dynamic VID transitions must be considered.

where

TonMA TonMA

IOCP

Ipea

IMA

Vout

Iout

3IOCPx(IDROOP=105A)

IMAX,TO

UVP

Droopeffect

a) Maximum current for each phase b) Output Characteristic


IO CT H m in( )---------------------------------------------------------------------= IOCPx

IO UT O CP( )3

---------------------------

IPP

2------------

ID-VID3

--------------+ +=

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Oscillator L6711

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15 Oscillator

The internal oscillator generates the triangular waveform for the PWM charging and

discharging with a constant current an internal capacitor. The switching frequency for eachchannel, FSW, is internally fixed at 150kHz so that the resulting switching frequency at the

load side results in being tripled.

The current delivered to the oscillator is typically 25A (corresponding to the free runningfrequency Fsw=150kHz) and it may be varied using an external resistor (ROSC) connectedbetween the OSC pin and SGND or VCC (or a fixed voltage greater than 1.24V). Since the OSCpin is fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into)the pin considering the internal gain of 6KHz/A.

In particular connecting ROSCto SGND the frequency is increased (current is sunk from the

pin), while connecting ROSCto VCC=12V the frequency is reduced (current is forced into the

pin), according to the following relationships:

Maximum programmable switching frequency depends on the Current Reading Method

selected. When reading across LS mosfet, the maximum switching frequency per phase

must be limited to 500kHz to avoid current reading errors causing, as a consequence,

current sharing errors. When reading across the inductor, higher switching frequency can be

approached (device power dissipation must be checked prior to design high switching

frequency systems).

Figure 19. ROSCvs. switching frequency

ROS Cvs. GND: FSW 150kHz1.237

ROS C k( )---------------------------- 6

kHz

A-----------+ 150kHz

7.422 106

ROSC k( )-----------------------------+= =

ROS Cvs. 12V: FSW 150kHz12-1.237

ROS C k( )---------------------------- 6

kHz

A-----------+ 150kHz

6.457 107

ROS C k( )-----------------------------+= =

0

2000

4000

6000

8000

10000

12000

14000

25 50 75 100 125 150

0

200

400

600

800

1000

150 250 350 450 550 650 750 850

ROSC[k] to SGND vs. Selected FSW[kHz]ROSC[k] to 12V vs. Selected FSW[kHz]

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16 Driver section

The integrated high-current drivers allow using different types of power MOS (also multiple

MOS to reduce the equivalent RdsON), maintaining fast switching transition.

The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for

return. The drivers for the low-side mosfets use VCCDRx pin for supply and PGNDx pin for

return. A minimum voltage of 4.6V at VCCDRx pin is required to start operations of the

device. VCCDRx pins must be connected together.

The controller embodies a sophisticated anti-shoot-through system to minimize low side

body diode conduction time maintaining good efficiency saving the use of Schottky diodes:

when the high-side mosfet turns off, the voltage on its source begins to fall; when the

voltage reaches 2V, the low-side mosfet gate drive is suddenly applied. When the low-side

mosfet turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side

mosfet gate drive is suddenly applied.

If the current flowing in the inductor is negative, the source of high-side mosfet will neverdrop. To allow the turning on of the low-side mosfet even in this case, a watchdog controller

is enabled: if the source of the high-side mosfet doesn't drop for more than 240ns, the low

side mosfet is switched on so allowing the negative current of the inductor to recirculate.

This mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as

signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the

switching noise immunity. The separated supply for the different drivers gives high flexibility

in mosfet choice, allowing the use of logic-level mosfet. Several combination of supply can

be chosen to optimize performance and efficiency of the application.

Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion

(See maximum duty cycle limitations) can be chosen freely.

16.1 Power dissipation

Two main terms contribute in the device power dissipation: bias power and drivers' power.

The first one depends on the static consumption of the device through the supply pins and it

is simply quantifiable as follow:

PDC= VCC (ICC+ 3 ICCDRx+ 3 IBOOTx)

Drivers' power is the power needed by the driver to continuously switch on and off the

external mosfets; it is a function of the switching frequency and total gate charge of the

selected mosfets. It can be quantified considering that the total power P SWdissipated to

switch the mosfets (easy calculable) is dissipated by three main factors: external gateresistance (when present), intrinsic mosfet resistance and intrinsic driver resistance. This

last term is the important one to be determined to calculate the device power dissipation.

The total power dissipated to switch the mosfets results:

PSW= 3 (QG_HS VBOOT+ QG_LS VCCDR) FSW

External gate resistors helps the device to dissipate the switching power since the same

power PSWwill be shared between the internal driver impedance and the external resistor

resulting in a general cooling of the device.It is important to determine the device dissipated

power in order to avoid the junction working beyond its maximum operative temperature.

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Driver section L6711

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Moreover, since the device has an exposed pad to better dissipate the power, also

3 phase controller cd 00040795

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