3 General-Purpose Programmable Peripheral Devices

The 8255A Programmable Peripheral InterfaceThe 8255A is a widely used, programmable, parallel I/O device.It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O.It is flexible, versatile, and economical (when multiple I/O ports are required).It is an important general-purpose I/O device that can be used with almost any microprocessor.

The 8255A I/O Ports

The 8255A has 24 I/O pins that can be grouped primarily in two 8-bit parallel ports: Port A and Port B, with the remaining eight bits as Port C.

The eight bits of port C can be used as individual bits or be grouped in two 4-bit ports:CUPPER (CU) , CLOWER (CL).

The functions of these ports are defined by writing a control word in the control register.

Pin Configuration and Names

Block Diagram

Block Diagram

Expanded version of the Internal Structure and the Control Logic

RD (Read): This control signal enables the Read operation. When the signal is low, the MPU reads data from a selected I/O port.

WR (Write): This control signal enables the Write operation. When the signal goes low, the MPU writes into a selected I/O port or the control register.

RESET (Reset): This is an active high signal; it clears the control register and sets all ports in the input mode.

CS, A0, and A1: These are device select signals. CS is connected to a decoded address, and A0 and A1 are generally connected to MPU address lines A0 and A1(respectively)

Ports SelectionThe CS signal is the master Chip Select, and A0 and A1 specify one of the I/O ports or the control register as given below:

Addressing for the example above

Communication StepsTo communicate with peripherals through the 8255A, three steps are necessary:

1. Determine the addresses of ports A, B, and C and of the control register according to the Chip Select logic and address lines A0 and A1.2. Write a control word in the control register.3. Write I/O instructions to communicate with peripherals through ports A, B, and C.

CS A1 A0 Selection0 0 0 Port A0 0 1 Port B0 1 0 Port C0 1 1 Control Register1 X X No Selection

CSA7 A6 A5 A4 A3 A2 A1 A0

Hex Address

Selection

100000 0 0 80H A100000 0 1 81H B100000 1 0 82H C100000 1 1 83H Control Register

Operation ModesMainly there are two main Modes, BSR Mode, and I/O Mode.

I/O Mode The I/O mode can be activated by setting D7 to 1, the rest of the control word can specify

the detailed configuration for each port. Keep in mind that there are 2 Groups and 3 Ports, A,B, and C. C contains 2 sub Ports, CLower, and CUpper. They are configured differently, but addressed

with the same address

Control Groups

Mode 0Simple Input/output configuration

Applies to Group A, and Group B In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit ports.

Each port (or half-port, in case of C) can be programmed to function as simply an input port or an output port.

The input/output features in Mode 0 are as follows: Outputs are latched . Inputs are not latched . Ports do not have handshake or interrupt capability

Configuration for Mode 0Mode 0 Mode 0

D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 00 0/1 0/1 0 0/1 0/11 to configure Input, 0 to configure output

I/O

Group BPort B

CLower

Group ACUpper

Port A

Example: Mode 0Given the Following circuit, write a program to input from Port B and Port CL, the output to Port A and CU Things we need to do:

Input from B , Output to A Input from CL , Output to CH

Solution:Step 1) Configure the Ports Addresses (Memory Addressing)From the hardware configuration, we know that the port addresses are as following:

A15 A14 A13 A12 A11 A12 A11 A0 A7 A6 A5 A4 A3 A2 A1 A0 AddPort A 1 X X X X X X X X X X X X X 0 0 8000HPort B 1 X X X X X X X X X X X X X 0 1 8001HPort C 1 X X X X X X X X X X X X X 1 0 8002H

CR 1 X X X X X X X X X X X X X 1 1 8003HA range of addresses can be used, we’ll adopt the following:

Port A = 8000H Port B = 8001H Port C = 8002H Control Register = 8003H

Step 2) Configure I/O Mode for the Control RegisterMode 0 Output Output Mode 0 Input Input

D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 00 0 0 0 1 1Control word = 10000011 = 83H

Step 3) Program CodeMVI A,83H Load accumulator with the control wordSTA 8003H Write word in the control register to initialize the portsLDA 8001H Read switches at port BSTA 8000H Display the reading at port ALDA 8002H Read switches at port CANI 0FH Mask the upper four bits of port C; these bits are not input dataRLC

Rotate and place data in the upper half of the accumulatorRLCRLCRLCSTA 8002H Display Data at PortHLT

Mode 1Input or Output with Handshake

Applies to Group A, and Group B In Mode 1, handshake signals are exchanged between the MPU and peripherals prior to data transfer. The features of this mode include the following:

Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output ports.

Each port uses three lines from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions.

Input and output data are latched. Interrupt logic is supported.

Configuration for Mode 1Mode 1 Mode 1

D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 01 0/1 X 1 0/1 X1 to configure Input, 0 to configure output

Mode 1 - Input ConfigurationHandshake Signals Functions

STB (Strobe Input): Generated by a peripheral device to indicate that it has transmitted a byte of data. The 8255A, in response to STB, generates IBF and INTR.

IBF (Input Buffer Full): Is an acknowledgment by the 8255A to indicate that the input latch has received the data byte.

INTR (Interrupt Request): An output signal that may be used to interrupt the MPU. This signal is generated if STB,IBF, and INTE (Internal flip-flop) are all at logic 1.

INTE (Interrupt Enable): An internal flip-flop used to enable or disable the generation of the INTR signal. The two flip flops INTEA and INTEB

are controlled by bits PC4 and PC2, respectively, through the BSR mode .

Note: to enable INTE for Port A, and Port B, we need to access the control Register through the BSR Mode. It is later discussed

Input Timing waveform

Basically, this is the structure of operation1) An Input device initiates STB Signal.2) The 8255A generates an IBF response when the data is received.3) The 8255A generates an INTR signal if INTE is enabled

Then the microprocessor can read the signal from the latched port.

Status and Control WordControl Word

Mode 1 Mode 1D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 01 1 X 1 1 X1 to configure Input, 0 to configure output

Status Word for Mode 0 InputD7 D6 D5 D4 D3 D2 D1 D0

I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB

The status word can be read from Port C, we are mostly interested in the IBF Latch at D5 and D1 which specifies whether data is availableThis word is meant only to be Read, other information include interrupt availability and the status of the Interrupt latch enable INTE

Programming NotesThere are two programming models for operation in Mode 1

Status Check I/O1) Read Port C2) If IBF is set

Read from Peripheral

Interrupt Based I/O1) When Data is available an interrupt

is set2) An Interrupt procedure reads data

Mode 1 - Output ConfigurationHandshake Signals Functions

OBF (Output Buffer Full): An output signal that goes low when the MPU writes data into the output latch of the 8255A. This signal indicates to an output peripheral that new data are ready to be read.

ACK (Acknowledge): An input signal from a peripheral that goes low when the peripheral receives the data from the 8255A ports.

INTR (Interrupt Request): An output signal, it can be used to interrupt the MPU to request the next data byte for output. The INTR is set when OBF, ACK, and INTE are all active.

INTE (Interrupt Enable): An internal flip-flop, needs to be set to generate the INTR signal. The two flip-flops INTEA and INTEB are controlled by bits PC6 and PC2, respectively, through the BSR mode.

Note: to enable INTE for Port A, and Port B, we need to access the control Register through the BSR Mode. It is later discussed

Output Timing waveform

Basically, this is the structure of operation1. The 8255A generates an OBF signal (Data ready for write)2. The output device generates ACK when the data is received.3. The 8255A generates an INTR signal if INTE is enabled

Status and Control WordControl Word

Mode 1 Mode 1D7 D6 D5 D4 D3 D2 D1 D0

I/O Group B Port A CUpper Group A Port B CLower

1 01 0 X 1 0 X1 to configure Input, 0 to configure output

Status Word for Mode 0 InputD7 D6 D5 D4 D3 D2 D1 D0

OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB

The status word can be read from Port C, we are mostly interested in the IBF Latch at D5 and D1 which specifies whether data is available

Example: Mode 1The following Figure shows an interfacing circuit using the 8255A in Mode 1. Port A is designed as the input port for a keyboard with interrupt I/O, and port B is designed as the output port for a printer with status check I/O.

Things we need to do:1. Find port addresses by analyzing the decode logic.2. Determine the control word to set up port A as input and port B as output in Mode 1.3. Determine the BSR word to enable INTEA (port A).4. Determine the masking byte to verify the OBFB line in the status check I/O (port B).5. Write initialization instructions and a printer subroutine to output characters that are stored

in memory.