250ma, low quiescent current, ultra-low noise, high ... thermal shutdown uvlo current limit 2 am...

1FEATURES DESCRIPTION

APPLICATIONS

TPS734xxDDC

TSOT23-5

(TOP VIEW)

OUT

NR

IN

GND

EN

1

2

3

5

4

TPS73401DDC

TSOT23-5

(TOP VIEW)

OUT

FB

IN

GND

EN

1

2

3

5

4

TPS734xxDRV

2mm x 2mm SON-6

(TOP VIEW)

IN

N/C

EN

6

5

4

OUT

NR

GND

1

2

3

GND

TPS73401DRV

2mm x 2mm SON-6

(TOP VIEW)

IN

N/C

EN

6

5

4

OUT

FB

GND

1

2

3

GND

TPS734xx

www.ti.com ........................................................................................................................................ SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009

250mA, Low Quiescent Current, Ultra-Low Noise, High PSRRLow-Dropout Linear Regulator

2• 250mA Low Dropout Regulator with EN The TPS734xx family of low-dropout (LDO),low-power linear regulators offers excellent ac• Low IQ: 44µAperformance with very low ground current. High• Multiple Output Voltage Versions Available:power-supply rejection ratio (PSRR), low noise, fast

– Fixed Outputs of 1.0V to 4.3V Using start-up, and excellent line and load transientInnovative Factory EEPROM Programming response are provided while consuming a very low

44µA (typical) ground current. The TPS734xx is– Adjustable Outputs from 1.25V to 6.2Vstable with ceramic capacitors and uses an advanced• High PSRR: 60dB at 1kHz BiCMOS fabrication process to yield a typical dropout

• Ultra-low Noise: 28µVRMS voltage of 125mV at 250mA output. The TPS734xxuses a precision voltage reference and feedback loop• Fast Start-Up Time: 45µsto achieve overall accuracy of 2% over all load, line,• Stable with a Low-ESR, 2.0µF Typical Outputprocess, and temperature variations. It is fullyCapacitance specified from TJ = –40°C to +125°C and is offered in

• Excellent Load/Line Transient Response low-profile ThinSOT-23, 2mm × 2mm SON, and 3mmx 3mm SON packages that are ideal for wireless• 2% Overall Accuracy (Load/Line/Temp)handsets, printers, and WLAN cards.• Very Low Dropout: 125mV at 250mA

• ThinSOT-23, 2mm × 2mm SON-6, and 3mm x3mm SON-8 Packages

• WiFi, WiMax• Printers• Cellular Phones, SmartPhones• Handheld Organizers, PDAs

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2007–2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ABSOLUTE MAXIMUM RATINGS (1)

DISSIPATION RATINGS

TPS734xx

SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

PRODUCT VOUT(2)

TPS734xxyyyz XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).YYY is package designator.Z is package quantity.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.

(2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;minimum order quantities may apply. Contact factory for details and availability.

Over operating temperature range (unless otherwise noted).

PARAMETER TPS734xx UNITVIN range –0.3 to +7.0 VVEN range –0.3 to VIN +0.3 VVOUT range –0.3 to VIN +0.3 VVFB range –0.3 to VFB (TYP) +0.3 VPeak output current Internally limitedContinuous total power dissipation See Dissipation Ratings TableJunction temperature range, TJ –55 to +150 °CStorage junction temperature range, TSTG –55 to +150 °CESD rating, HBM 2 kVESD rating, CDM 500 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.

DERATING FACTORBOARD PACKAGE RθJC RθJA ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°CLow-K (1) DDC 90°C/W 280°C/W 3.6mW/°C 360mW 200mW 145mWHigh-K (2) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mWLow-K (1) DRV 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mWHigh-K (2) DRV 20°C/W 65°C/W 15.4mW/°C 1.54W 845mW 615mW

(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g)copper traces on top of the board.

(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g)internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board

2 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

http://www.ti.com

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBVS089F&partnum=TPS734xx

ELECTRICAL CHARACTERISTICS

TPS734xx


Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,VEN = VIN, COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V.Typical values are at TJ = +25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIN Input voltage range (1) 2.7 6.5 VVFB Internal reference (TPS73401) 1.184 1.208 1.232 V

VOUT Output voltage range (TPS73401) VFB 6.3 VVOUT Output accuracy Nominal TJ = +25°C –1.0 +1.0 %

Over VIN, VOUT + 0.3V ≤ VIN ≤ 6.5VVOUT Output accuracy (1) –2.0 ±1.0 +2.0 %IOUT, Temp 1mA ≤ IOUT ≤ 250mAΔVOUT%/ ΔVIN Line regulation (1) VOUT(NOM) + 0.3V ≤ VIN ≤ 6.5V 0.02 %/VΔVOUT%/ ΔIOUT Load regulation 500µA ≤ IOUT ≤ 250mA 0.005 %/mA

Dropout voltage (2)VDO IOUT = 250mA 125 219 mV(VIN = VOUT(NOM) – 0.1V)ICL Output current limit VOUT = 0.9 × VOUT(NOM) 300 580 900 mA

IGND Ground pin current 500µA ≤ IOUT ≤ 250mA 45 65 µAISHDN Shutdown current (IGND) VEN ≤ 0.4V 0.15 1.0 µA

IFB Feedback pin current (TPS73401) –0.5 0.5 µAf = 100Hz 60 dB

Power-supply rejection ratio f = 1kHz 56 dBPSRR VIN = 3.85V, VOUT = 2.85V,

f = 10kHz 41 dBCNR = 0.01µF, IOUT = 100mAf = 100kHz 28 dBCNR = 0.01µF 11 x VOUT µVRMSOutput noise voltageVN BW = 10Hz to 100kHz, VOUT = 2.8V CNR = none 95 x VOUT µVRMS

CNR = none 45 µsStartup time,

CNR = 0.001µF 45 µsVOUT = 0 ~ 90%,TSTR VOUT = 2.85V, CNR = 0.01µF 50 µsRL = 14Ω, COUT = 2.2µF

CNR = 0.047µF 50 µsVEN(HI) Enable high (enabled) 1.2 VIN VVEN(LO) Enable low (shutdown) 0 0.4 VIEN(HI) Enable pin current, enabled VEN = VIN = 6.5V 0.03 1.0 µA

Shutdown, temperature increasing 165 °CTSD Thermal shutdown temperature

Reset, temperature decreasing 145 °CTJ Operating junction temperature –40 +125 °C

Undervoltage lock-out VIN rising 1.90 2.20 2.65 VUVLO

Hysteresis VIN falling 70 mV

(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.(2) VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V.

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 3


DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAMS

Thermal

Shutdown

UVLO

Current

Limit

3.3MW

Overshoot

Detect

500kW

1.208V

Bandgap

IN

EN

FB

OUT

GND

400W

Thermal

Shutdown

UVLO

Current

Limit

2 Am

Overshoot

Detect

500kW

Quickstart

1.208V

Bandgap(1)

IN

EN

NR

OUT

GND

400W

NOTE (1): Fixed voltage versions between 1.0V to 1.2V have a 1.0V bandgap circuit

instead of a 1.208V bandgap circuit.

PIN CONFIGURATIONS

TPS734xxDDC

TSOT23-5

(TOP VIEW)

OUT

NR

IN

GND

EN

1

2

3

5

4

TPS73401DDC

TSOT23-5

(TOP VIEW)

OUT

FB

IN

GND

EN

1

2

3

5

4

TPS734xxDRV

2mm x 2mm SON-6

(TOP VIEW)

IN

N/C

EN

6

5

4

OUT

NR

GND

1

2

3

GND

TPS73401DRV

2mm x 2mm SON-6

(TOP VIEW)

IN

N/C

EN

6

5

4

OUT

FB

GND

1

2

3

GND

TPS734xx


Figure 1. Fixed Voltage Versions Figure 2. Adjustable Voltage Versions

PIN DESCRIPTIONSTPS734xx

NAME DDC DRV DRB DESCRIPTIONIN 1 6 8 Input supply.

GND 2 3, Pad 4 Ground. The pad must be tied to GND.Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts theEN 3 4 5 regulator into shutdown mode. EN can be connected to IN if not used.Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise

NR 4 2 3 generated by the internal bandgap. This allows output noise to be reduced to very lowlevels.Adjustable version only; this is the input to the control loop error amplifier, and is used to setFB 4 2 3 the output voltage of the device.Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0µF ceramic) isOUT 5 1 1 needed from this pin to ground to assure stability.

N/C — 5 2, 6, 7 Not internally connected. This pin must either be left open, or tied to GND.



TYPICAL CHARACTERISTICS

0.5

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4

0.5

-

-

-

-

-

Change in V

(%)

OU

T

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V (V)IN

TJ = 40 C- ° TJ = 0 C°

TJ = +125 C°

TJ = +85 C°

TJ = +25 C°

I = 100mAOUT0.5

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4

0.5

-

-

-

-

-

Ch

an

ge

in

V(%

)O

UT

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V (V)IN

TJ = 40 C- °

TJ = 0 C°

TJ = +125 C°

TJ = +85 C°

TJ = +25 C°

I = 100mAOUT

2.86

2.85

2.84

2.83

2.82

2.81

2.80

2.79

2.78

2.77

2.76

2.75

2.74

V(V

)O

UT

Load (mA)

TJ = 40 C- °

TJ = +125 C°

TJ = +85 C°

Y-axis range is 2% of 2.8V±

0 50 100 150 200 250

2.55

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

2.45

V(V

)O

UT

Load (mA)

TJ = 40 C- °

TJ = +125 C° TJ = +85 C°

TJ = 0 C°

TJ = +25 C°

Y-axis range is 2% of 2.5V±

0 50 100 150 200 250

500

450

400

350

300

250

200

150

100

50

0

I(n

a)

GN

D

-40 -25 -10 5 20 35 50 65 80 95 110 125

T ( )J C°

VIN = 6.5V

VEN = 0.4V

VIN = 5.0V

VIN = 3.3V

60

50

40

30

20

10

0

I(

A)

mG

ND

0 50 100 150 200 250

I (mA)OUT

TJ = 40 C- °

TJ = +125 C°

TJ = +85 C°

TJ = 0 C°

TJ = +25 C°

TPS734xx


Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ =

+25°C.

TPS73401 LINE REGULATION TPS73425 LINE REGULATION

Figure 3. Figure 4.

TPS73401 LOAD REGULATION TPS73425 LOAD REGULATION

Figure 5. Figure 6.

TPS73425 GROUND PIN CURRENT vs TPS73425 GROUND PIN CURRENT (DISABLE)OUTPUT CURRENT vs TEMPERATURE

Figure 7. Figure 8.



400

350

300

250

200

150

100

50

0

V(m

V)

DO

0 50 100 150 200 250

I (mA)OUT

TJ = 40 C- °

TJ = +125 C°

TJ = +85 C°

TJ = 0 C°

TJ = +25 C°

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

90

80

70

60

50

40

30

20

10

0

PS

RR

(d

B)

C = 10 FOUT m

C = 0.01 FNR m

I = 250mAOUT

I =

100mAOUT

I = 200mAOUT

I = 1mAOUT

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

90

80

70

60

50

40

30

20

10

0

PS

RR

(d

B)

C = 2.2 FOUT m

C = 0.01 FNR m

I = 200mAOUT

I =

100mAOUT

I = 250mAOUT

I = 1mAOUT

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

90

80

70

60

50

40

30

20

10

0

PS

RR

(d

B)

C = 2.2 FOUT m

C = 0.01 FNR m

I = 200mAOUT

I =

100mAOUT

I =

200mAOUT

I = 1mAOUT

30

25

20

15

10

5

0

Tota

l N

ois

e (

V)

mR

MS

0 5 10 15 20 25

C ( F)mOUT

I = 1mA

C = 0.01 FOUT

NR m

140

120

100

80

60

40

20

0

Tota

l N

ois

e (

V)

mR

MS

0.01 0.1 1 10

C (nF)NR

I = 1mA

C = 2.2 FOUT

OUT m

TPS734xx


TYPICAL CHARACTERISTICS (continued)Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ =+25°C.

TPS73401 DROPOUT VOLTAGE vs POWER-SUPPLY RIPPLE REJECTION vs FREQUENCYOUTPUT CURRENT (VIN – VOUT = 1.0V)

Figure 9. Figure 10.

POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY(VIN – VOUT = 0.5V) (VIN – VOUT = 0.3V)


TPS73425 TPS73425TOTAL NOISE vs CNR TOTAL NOISE vs COUT




10 s/divm

VOUT

VEN

C = 10 FOUT m

C = 2.2 FOUT m

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.5-

Vo

lta

ge

(V

)

10 s/divm

VEN

VOUTC = 2.2 FOUT m

C = 10 FOUT m

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.5-

Voltage (

V)

20 s/divm

100mV/div

100mV/div

100mA/div

VOUT

VOUT

IOUT

C = 1.0 FOUT m

C = 2.2 FOUT m

V = 2.7VIN

1mA

250mA

50ms/div

Volts

7

6

5

4

3

2

1

0

-1

VIN

I = 250mAOUT

VOUT

20 s/divm

20mV/div

20mV/div

1V/div

VOUT

VOUT

VIN

I =OUT 250mA

dVIN

dt= 1V/ sm

C = 2.2 FOUT m

C =OUT 1.0 Fm

2.7V

3.7V

TPS734xx


TYPICAL CHARACTERISTICS (continued)Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ =+25°C.

TPS73425TURN-ON RESPONSE TPS73425

(VIN = VEN) ENABLE RESPONSE OVER STABLE VIN


TPS73410 TPS73410POWER-UP/POWER-DOWN LOAD TRANSIENT RESPONSE


TPS73410LINE TRANSIENT RESPONSE

Figure 19.



APPLICATION INFORMATIONInput and Output Capacitor Requirements

Feedback Capacitor RequirementsGNDEN NR

IN OUT

TPS734xx

Optional bypass capacitor

to reduce output noise

and increase PSRR.

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

VIN

VEN

2.2 F

Ceramic

m

VOUT

Output NoiseGNDEN FB

IN OUT

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

TPS73401

2.2 F

Ceramic

m

VIN

VEN

R1

R2

CFB

VOUT

(R + R )1 2

R2

VOUT = ´ 1.208

TPS734xx


The TPS734xx family of LDO regulators combinesthe high performance required of many RF and Although an input capacitor is not required forprecision analog applications with ultra-low current stability, it is good analog design practice to connectconsumption. High PSRR is provided by a high gain, a 0.1µF to 1µF low equivalent series resistancehigh bandwidth error loop with good supply rejection (ESR) capacitor across the input supply near theat very low headroom (VIN – VOUT). Fixed voltage regulator. The ground of this capacitor should beversions provide a noise reduction pin to bypass connected as close as the ground of output capacitor;noise generated by the bandgap reference and to a capacitor value of 0.1µF is enough in this condition.improve PSRR while a quick-start circuit fast-charges When it is difficult to place these two ground pointsthis capacitor at startup. The combination of high close together, a 1µF capacitor is recommended.performance and low ground current also make the This capacitor counteracts reactive input sources andTPS734xx an excellent choice for portable improves transient response, noise rejection, andapplications. All versions have thermal and ripple rejection. A higher-value capacitor may beover-current protection and are fully specified from necessary if large, fast rise-time load transients are–40°C to +125°C. anticipated, or if the device is located several inches

from the power source. If source impedance is notFigure 20 shows the basic circuit connections for sufficiently low, a 0.1µF input capacitor may befixed voltage models. Figure 21 gives the connections necessary to ensure stability.for the adjustable output version (TPS73401). R1 andR2 can be calculated for any output voltage using the The TPS734xx is designed to be stable with standardformula in Figure 21. ceramic output capacitors of values 2.2µF or larger.

X5R and X7R type capacitors are best because theyhave minimal variation in value and ESR overtemperature. Maximum ESR of the output capacitorshould be < 1.0Ω, so output capacitor type should beeither ceramic or conductive polymer electrolytic.

(TPS73401 only)The feedback capacitor, CFB, shown in Figure 21 isrequired for stability. For a parallel combination of R1and R2 equal to 250kΩ, any value from 3pF to 1nFcan be used. Fixed voltage versions have an internal30pF feedback capacitor that is quick-charged at

Figure 20. Typical Application Circuit for start-up. The adjustable version does not have thisFIxed Voltage Versions quick-charge circuit, so values below 5pF should be

used to ensure fast startup; values above 47pF canbe used to implement an output voltage soft-start.Larger value capacitors also improve noise slightly.The TPS73401 is stable in unity-gain configuration(OUT tied to FB) without CFB.

In most LDOs, the bandgap is the dominant noisesource. If a noise reduction capacitor (CNR) is usedwith the TPS734xx, the bandgap does not contributesignificantly to noise. Instead, noise is dominated bythe output resistor divider and the error amplifier

Figure 21. Typical Application Circuit for input. To minimize noise in a given application, use aAdjustable Voltage Versions 0.01µF noise reduction capacitor; for the adjustable

version, smaller value resistors in the output resistorspace divider reduce noise. A parallel combination that

gives 2µA of divider current has the same noisespace performance as a fixed voltage version. To further



Startup and Noise Reduction Capacitor

V = x VN OUT

11

V

mVRMS

(1)

Board Layout Recommendations to Improve

Transient Response

Internal Current Limit

Undervoltage Lock-Out (UVLO)

Shutdown

Minimum Load

Dropout Voltage

TPS734xx


optimize noise, equivalent series resistance of the As with any linear regulator, PSRR and transientoutput capacitor can be set to approximately 0.2Ω. response are degraded as (VIN – VOUT) approachesThis configuration maximizes phase margin in the dropout. This effect is shown in the Typicalcontrol loop, reducing total output noise by up to Characteristics section.10%.

Noise can be referred to the feedback point (FB pin)such that with CNR = 0.01µF, total noise is given Fixed voltage versions of the TPS734xx use aapproximately by Equation 1: quick-start circuit to fast-charge the noise reduction

capacitor, CNR, if present (see the Functional BlockDiagrams). This architecture allows the combinationof very low output noise and fast start-up times. The

The TPS73401 adjustable version does not have the NR pin is high impedance so a low leakage CNRnoise-reduction pin available, so ultra-low noise capacitor must be used; most ceramic capacitors areoperation is not possible. Noise can be minimized appropriate in this configuration.according to the above recommendations.

Note that for fastest startup, VIN should be appliedfirst, then the enable pin (EN) driven high. If EN istied to IN, startup is somewhat slower. Refer to thePSRR and Noise Performance Typical Characteristics section. The quick-start switch

To improve ac performance such as PSRR, output is closed for approximately 135µs. To ensure thatnoise, and transient response, it is recommended that CNR is fully charged during the quick-start time, athe board be designed with separate ground planes 0.01µF or smaller capacitor should be used.for VIN and VOUT, with each ground plane connectedonly at the GND pin of the device. In addition, theground connection for the bypass capacitor should

As with any regulator, increasing the size of theconnect directly to the GND pin of the device.output capacitor reduces over/undershoot magnitudebut increases duration of the transient response. Inthe adjustable version, adding CFB between OUT and

The TPS734xx internal current limit helps protect the FB improves stability and transient response. Theregulator during fault conditions. During current limit, transient response of the TPS734xx is enhanced bythe output sources a fixed amount of current that is an active pull-down that engages when the outputlargely independent of output voltage. For reliable overshoots by approximately 5% or more when theoperation, the device should not be operated in device is enabled. When enabled, the pull-downcurrent limit for extended periods of time. device behaves like a 400Ω resistor to ground.

The PMOS pass element in the TPS734xx has abuilt-in body diode that conducts current when thevoltage at OUT exceeds the voltage at IN. This The TPS734xx utilizes an undervoltage lock-outcurrent is not limited, so if extended reverse voltage circuit to keep the output shut off until internaloperation is anticipated, external limiting may be circuitry is operating properly. The UVLO circuit has aappropriate. de-glitch feature so that it typically ignores

undershoot transients on the input if they are lessthan 50µs duration.

The enable pin (EN) is active high and is compatiblewith standard and low voltage TTL-CMOS levels.When shutdown capability is not required, EN can be The TPS734xx is stable and well-behaved with noconnected to IN. output load. To meet the specified accuracy, a

minimum load of 1mA is required. Below 1mA atjunction temperatures near +125°C, the output candrift up enough to cause the output pull-down to turnThe TPS734xx uses a PMOS pass transistor to on. The output pull-down limits voltage drift to 5%achieve low dropout. When (VIN – VOUT) is less than typically but ground current could increase bythe dropout voltage (VDO), the PMOS pass device is approximately 50µA. In typical applications, thein its linear region of operation and the input-to-output junction cannot reach high temperatures at light loadsresistance is the RDS, ON of the PMOS pass element. because there is no appreciable dissipated power.Because the PMOS device behaves like a resistor in The specified ground current would then be valid atdropout, VDO approximately scales with output no load conditions in most applications.current.



Thermal Information

Thermal Protection Power Dissipation

PD VINVOUT IOUT (2)

Package Mounting

TPS734xx


Thermal protection disables the output when the The ability to remove heat from the die is different forjunction temperature rises to approximately +165°C, each package type, presenting differentallowing the device to cool. When the junction considerations in the PCB layout. The PCB areatemperature cools to approximately +145°C the around the device that is free of other componentsoutput circuitry is again enabled. Depending on power moves the heat from the device to the ambient air.dissipation, thermal resistance, and ambient Performance data for JEDEC low- and high-K boardstemperature, the thermal protection circuit may cycle are given in the Dissipation Ratings table. Usingon and off. This cycling limits the dissipation of the heavier copper increases the effectiveness inregulator, protecting it from damage as a result of removing heat from the device. The addition of platedoverheating. through-holes to heat-dissipating layers also

improves the heatsink effectiveness.Any tendency to activate the thermal protection circuitindicates excessive power dissipation or an Power dissipation depends on input voltage and loadinadequate heatsink. For reliable operation, junction conditions. Power dissipation is equal to the producttemperature should be limited to +125°C maximum. of the output current time the voltage drop across theTo estimate the margin of safety in a complete design output pass element, as shown in Equation 2:(including heatsink), increase the ambienttemperature until the thermal protection is triggered;use worst-case loads and signal conditions. For goodreliability, thermal protection should trigger at least+35°C above the maximum expected ambient Solder pad footprint recommendations for thecondition of your particular application. This TPS734xx are available from the Texas Instrumentsconfiguration produces a worst-case junction web site at www.ti.com.temperature of +125°C at the highest expectedambient temperature and worst-case load.

The internal protection circuitry of the TPS734xx hasbeen designed to protect against overload conditions.It was not intended to replace proper heatsinking.Continuously running the TPS734xx into thermalshutdown degrades device reliability.


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PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS73401DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OCW

TPS73401DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OCW

TPS73401DRVR ACTIVE WSON DRV 6 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 CBG

TPS73401DRVT ACTIVE WSON DRV 6 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 CBG


CU NIPDAU Level-1-260C-UNLIM -40 to 125 CBI


CU NIPDAU Level-1-260C-UNLIM -40 to 125 CBI


CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVW


CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVW

TPS73433DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OEV

TPS73433DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OEV


CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVX


CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVX

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.

http://www.ti.com/product/TPS734?CMP=conv-poasamples#samplebuy












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PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

Addendum-Page 2

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS73401DDCR SOT-23-THIN

DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS73401DDCT SOT-23-THIN

DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS73401DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS73401DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2







TPS73433DDCR SOT-23-THIN

DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS73433DDCT SOT-23-THIN

DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3



PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS73401DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0

TPS73401DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0

TPS73401DRVR WSON DRV 6 3000 203.0 203.0 35.0

TPS73401DRVT WSON DRV 6 250 203.0 203.0 35.0

TPS73418DRVR WSON DRV 6 3000 203.0 203.0 35.0

TPS73418DRVT WSON DRV 6 250 203.0 203.0 35.0

TPS73430DRVR WSON DRV 6 3000 205.0 200.0 33.0

TPS73430DRVR WSON DRV 6 3000 203.0 203.0 35.0

TPS73430DRVT WSON DRV 6 250 205.0 200.0 33.0

TPS73430DRVT WSON DRV 6 250 203.0 203.0 35.0

TPS73433DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0

TPS73433DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0

TPS73433DRVR WSON DRV 6 3000 203.0 203.0 35.0

TPS73433DRVT WSON DRV 6 250 203.0 203.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2018

Pack Materials-Page 2

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.

DRV 6 WSON - 0.8 mm max heightPLASTIC SMALL OUTLINE - NO LEAD

4206925/F

www.ti.com

PACKAGE OUTLINE

C

6X 0.350.25

1.6 0.1

6X 0.30.2

2X1.3

1 0.1

4X 0.65

0.80.7

0.050.00

B 2.11.9

A

2.11.9

(0.2) TYP

WSON - 0.8 mm max heightDRV0006APLASTIC SMALL OUTLINE - NO LEAD

4222173/B 04/2018

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

1

34

6

(OPTIONAL)PIN 1 ID

0.1 C A B0.05 C

THERMAL PADEXPOSED

7

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 5.500

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EXAMPLE BOARD LAYOUT

0.07 MINALL AROUND

0.07 MAXALL AROUND

(1)

4X (0.65)

(1.95)

6X (0.3)

6X (0.45)

(1.6)

(R0.05) TYP

( 0.2) VIATYP

(1.1)


4222173/B 04/2018

SYMM

1

34

6

SYMM

LAND PATTERN EXAMPLESCALE:25X

7

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

SOLDER MASKOPENINGSOLDER MASK

METAL UNDER

SOLDER MASKDEFINED

METALSOLDER MASKOPENING

SOLDER MASK DETAILS

NON SOLDER MASKDEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

6X (0.3)

6X (0.45)

4X (0.65)

(0.7)

(1)

(1.95)

(R0.05) TYP

(0.45)


4222173/B 04/2018

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:30X

SYMM

1

3 4

6

SYMM

METAL7

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