BLUECHIP TECHNOLOGIES

VLSI 2014 IEEE TITLESS.NO CODE PROJECT TITLE YEAR

1 VL01 Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits

2014

2 VL02 On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions

2014

3 VL03 Delay Test for Diagnosis of Power Switches 2014

4 VL04 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

2014

5 VL05 Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code

2014

6 VL06 High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

2014

7 VL07 Incremental Trace-Buffer Insertion for FPGA Debug 2014

8 VL08 LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

2014

9 VL09 Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers

2014

10 VL10 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme

2014

11 VL11 A 12.5-GB/S ON-CHIP OSCILLOSCOPE TO MEASURE EYE DIAGRAMS AND JITTER HISTOGRAMS OF HIGH-SPEED SIGNALS

2014

12 VL12 PULSED-LATCH UTILIZATION FOR CLOCK-TREEPOWER OPTIMIZATION

2014

13 VL13 BUILT-IN BINARY CODE INVERSION TECHNIQUE FORON-CHIP FLASH MEMORY SENSE AMPLIFIER WITHREDUCED READ CURRENT CONSUMPTION

2014

14 VL14 Software/Hardware Parallel Long-Period Random NumberGeneration Framework Based On The Well Method

2014

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BLUECHIP TECHNOLOGIES15 VL15

Variation-Aware Variable Latency Design2014

16 VL16 On-Chip Memory Hierarchy In One Coarse-GrainedReconfigurable Architecture To Compress Memory Space AndTo Reduce Reconfiguration Time And Data-Reference Time

2014

17 VL17 On The Automatic Generation Of Optimized Software-BasedSelf-Test Programs For Vliw Processors

2014

18 VL18Ultra-High Throughput Low-Power Packet Classification

2014

19 VL19 Light-Weight On-Chip Structure For Measuring Timing Uncertainty Induced By Noise In Integrated Circuits

2014

20 VL20 A Synergetic Use Of Bloom Filters For Error Detection And Correction

2014

21 VL21 An Accuracy-Adjustment Fixed Width Booth Multiplier BasedOn Multilevel Conditional Probability

2014

22 VL22 FPGA Based Bit Error Rate Performance Measurement Of Wireless Systems

2014

23 VL23Hardware Efficient Mixed Radix-25/16/9 Fft For Lte Systems

2014

24 VL24High-Throughput And Low-Complexity Bch Decoding

2014

25 VL25A Real-Time Motion-Feature-Extraction Vlsi Employing

2014

26 VL26 Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution

2014

27 VL27 Low-Energy Two Stage Algorithm For High Efficacy EpilepticSeizure Detection

2014

28 VL28Design and Implementation of Modified Signed-Digit Adder

2014

29 VL29Area-Delay Efficient Binary Adders in QCA

2014

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#7, KRISHNA COMPLEX, OPP TO DAILY DHANTHI, ERODE. 9962064074/9884977977