IMPACT • DMI• 1 05/05/2008

Variability in Analog/Mixed-Signal CircuitsElad Alon, Dept. of EECS, UC Berkeley

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2008 IMPACT Seminar

IMPACT • DMI• 2 05/05/2008

Motivation

Lots of current work on variability in digital circuits– E.g., ring oscillator arrays,

SSTA, etc.– Small number of well-

defined metrics (delay, power,area, yield)

Few efforts focusing on analog/mixed-signal– Problem isn’t “new” – but overheads largely un-quantified– Harder to perform general studies – need to know more about the

circuit/system

IMPACT • DMI• 3 05/05/2008

Outline

Variability Examples and Mitigation Techniques

Phase-Locked Loop Design

Conclusions

IMPACT • DMI• 4 05/05/2008

Analog Variations

Two categories:– Global variations– Random mismatch

Global variations– Absolute tolerances on RL, CL, ro, etc.– Typically +/- 50% or more

– (Still largest issue in digital)

Example: Amplifier with constant Ibias– 50% decrease in RL 50% drop in gain– May no longer be able to detect input signal

IMPACT • DMI• 5 05/05/2008

Ratiometric Design

Build circuits that only depend on ratios of parameters– Not on absolute value

Classic example: Negative feedback amplifier– A = 1 + R1/R2

Very easy to apply to some specs (e.g., gain) – Can also be used to control parameters not naturally related (e.g.,

bandwidth = gm/CL)– Requires “clever” biasing – more later

IMPACT • DMI• 6 05/05/2008

Ratiometric Layout

Performance set by matching between ratioedelements– Designers take every

precaution to make ratio hold

Analog designers make heavyuse of “restricted design rules”– Regular arrays of unit cells– Heavy use of dummies– Common centroid to cancel gradients

IMPACT • DMI• 7 05/05/2008

Random Mismatch

Even with “perfect” design/layout, need to deal with random mismatch

Typical mismatch issue: random offset– Min. sized 90nm device: σΔVth = 30mV– What if need to detect a 1mV signal?

IMPACT • DMI• 8 05/05/2008

Does Offset Really Matter?

Depends on how the circuit is being used

Example: Radio receiver– LNA – offset basically ignored (different frequency band)– ADC – offset critical to performance

ADCLNA LPF

LO

IMPACT • DMI• 9 05/05/2008

What This Means

To quantify impacts of variability on analog or mixed-signal circuits– Need to perform study in context of real designs– And use best available techniques to tolerate/mitigate variability

Focus on key, representative blocks– Start with a phase-locked loop (PLL)

IMPACT • DMI• 10 05/05/2008

Outline

Variability Examples and Mitigation Techniques

Phase-Locked Loop Design

Conclusions

IMPACT • DMI• 11 05/05/2008

Phase-Locked Loop Review

Modern processor runswith 2-3 GHz clock– Cheap crystals usually

go up to only ~100MHz

Phase-locked loop (PLL) multiplies low frequency crystal reference

Functionality critical: PLL fails to “lock”, whole chip fails– Failure can be parametric too (jitter)

Clk

PFD BufferVcp

Vreg

up

down +-

ref_clk

÷N

VCO

IMPACT • DMI• 12 05/05/2008

Linearized Model

Clk

PFD BufferVcp

Vreg

up

down +-

ref_clk

÷N

VCO

PLLs are intrinsically2nd order or higherfeedback loops– Stability is one of the

primary concerns

Variations can destabilize the loop– E.g., what if R drops

by 50%?

IMPACT • DMI• 13 05/05/2008

Icp

Vreg

up

downR

C+

-

clk

÷N

PFDref_clk

“Self-biasing”: Applyratio-metric design toPLL to ensure stability

Key design changes: – Charge pump current and filter

R derived from VCO bias current

Assuming quadratic devices (ID α βVreg2):

Self-Biased PLL

( )vco reg reg

vco

f I CV V C

K C

β

β

∝ ∝

∝

IMPACT • DMI• 14 05/05/2008

Icp

Vreg

up

downR

C+

-

clk

÷N

PFDref_clk

Self-Biased PLL cont’d

( ) 21 , ,

~

cp vcocp vco n

reg cp reg vco reg vco

n vco

I KR I K C

CR V I V f V C K C

const f

ζ ω

β β β β

ζ ω

⋅∝ ⋅ ⋅ ⋅ ∝

∝ ∝ ∝ ∝

→ ∝

IMPACT • DMI• 15 05/05/2008

Issues with Self-Biasing

Self-biasing has so far been very effective– But, relies heavily on local matching between devices

Local matching increasingly difficult to guarantee– Brute force approach of increasing device size very expensive in

terms of power dissipation

Icp

Vreg

up

downR

C+

-

clk

÷N

PFDref_clk

IMPACT • DMI• 16 05/05/2008

Proposed Digital PLL

Instead of relying on matching– Measure the underlying parameters and adjust control

accordingly

Much easier to do with a digital control loop…

÷N

ref_clk

+-

Vref

Cdecap

LPF

ΣDCO

TDCN

fprop

fint

Vreg

Clk

IMPACT • DMI• 17 05/05/2008

Proposed Digital PLL cont’d

PFD replaced by a time-to-digital converter(TDC)

Loop filter and charge pump replaced by digitallogic

VCO replaced by digitally-controlled oscillator (DCO)

÷N

ref_clk

+-

Vref

Cdecap

LPF

ΣDCO

TDCN

fprop

fint

Vreg

Clk

reg

prop

intN

IMPACT • DMI• 18 05/05/2008

Digital PLL Calibration

Digital arch. well-suited to calibration– DCO easily measured

by forcing control input– Adjustments easily

made by digital logic after LF

– Logic complexity set by range/type of variations

÷N

ref_clk DCOTDC ClkLF

gain_cal

+

off_cal

IMPACT • DMI• 19 05/05/2008

On-Going Work

Many challenges– In particular, resolution required of TDC to meet certain jitter

specs– TDC of course also affected by variations

Plan over next ~1 year:– Complete architecture development, leading to model of

variability vs. power consumption– Tape-out and characterize test-chip verify architecture

performance and model

IMPACT • DMI• 20 05/05/200804/09/2008

Outline

Variability Examples and Mitigation Techniques

Phase-Locked Loop Design

Conclusions

IMPACT • DMI• 21 05/05/2008

Conclusions

Analog/mixed-signal variability not new– But increasingly important– And power costs largely uncharacterized

Study of power overhead due to variability must be done in circuit/system context– What matters strongly depends on how the circuit is used – Can’t just look at noise margins, min./max. paths

Initial focus on PLLs– Exploring digital architecture to improve tolerance to local

variations