2008 iedm presentation

S.L. Rommel

Record PVCR GaAs-based Tunnel Record PVCR GaAs-based Tunnel Diodes Fabricated on Si Substrates Diodes Fabricated on Si Substrates

using Aspect Ratio Trappingusing Aspect Ratio TrappingS. L. Rommel1, D. Pawlik1, P. Thomas1, M. Barth1, K. Johnson1, S. Kurinec1, A. Seabaugh2, Z. Cheng3, J. Li3, J. Park3, J. Hydrick3, N. Bai3, M. Carroll3, J.

G. Fiorenza3, and A. Lochtefeld3

1Department of Microelectronic Engineering, Rochester Institute of Technology,

Rochester, NY 14623 USA

2Department of Electrical Engineering, University of Notre Dame,

South Bend, IN 46556 USA

3Amberwave Systems Corporation,

Salem, NH 03079-4235 USA

S.L. Rommel

– Motivation: • Why use tunnel diodes?

• Why use III-V tunnel diodes?

– Enabling Technology: “Aspect Ratio Trapping” (ART) • Developed by AmberWave

– World Record GaAs-based Esaki diodes on a Si Substrate• Fourth highest PVCR ever reported

• Structures are grown entirely by CVD.

OutlineOutline

S.L. Rommel

Tunnel Diode Characteristics and ApplicationsTunnel Diode Characteristics and Applications

V

IP

IV

VP VV

PVCR

IP

IV

Goals:

Demonstrate GaAs tunnel junctions on Si to enable:

Tunnel SRAM

Low-subthreshold- swing III-V tunnel transistors

n+n+

p+p+

PVCR > 10 desired!

Degenerate doping

Abrupt junction

S.L. Rommel

III-V Tunnel Diodes have larger PVCR than Si

Extensive literature reports of III-V Esaki diodes

MOCVD has been demonstrated for III-Vs

Si Vs. III-V Tunnel DiodesSi Vs. III-V Tunnel Diodes

Approach in this study: Integrate a III-V Esaki Diode on SiIntegrate a III-V Esaki Diode on Si

S.L. Rommel






High Speed High Speed LogicLogic

MemoryMemory

S.L. Rommel






Si Si EsakiEsaki

DiodesDiodes

III-V III-V EsakiEsaki

DiodesDiodes

S.L. Rommel

Silicon

Ge

SiO2

500 nm

J.S. Park et al., Appl. Phys. Lett 90 052113 (2007)

• Aspect Ratio Trapping (ART)– Enables heterointegration of Ge and

III-V on Si– Traps mismatch dislocations in high

aspect ratio trenches

• Advantages of ART– Works on variety of materials (Ge,

GaAs, InP) – Thin buffer layer (100-400 nm) enables

integration in CMOS– Accommodates high lattice mismatch

(up to 8% demonstrated)– Enables selective integration of

different materials

Aspect Ratio Trapping (ART)Aspect Ratio Trapping (ART)

Defect Trapping

S.L. Rommel


1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

0 1 2 3 4

Trench Aspect Ratio

De

fec

t D

en

sit

y (

cm

-2) Blanket Ge film

Detection limit = 7.3 x105 cm-2

Trench Width 100 to 400 nm

H

W

Ge

Si

Important Points: High trench aspect ratio is the key to trapping defects ART reduces defects by 3 orders of magnitude

Aspect Ratio = H/W

S.L. Rommel

Approach used for this study:

Integrate a III-V device atop a coalesced Ge substrate. RP-CVD for Ge MOCVD for III-V Growth

Germanium

Silicon

CoalescenceDislocation

Germanium

Silicon

CoalescenceDislocation


S.L. Rommel

Coalesced Ge

InGaAs/GaAs TD

Strained InGaAs/top contact (Some layers are all InGaAs)

Gold Contact

GaAs/Ge heterointerface

TEM image of Fabricated Device illustrates strained InGaAs diode layer.

GaAs/InGaAs Device ConceptGaAs/InGaAs Device Concept

Si SubstrateGe filled SiO2 trenches

S.L. Rommel

50 nm GaAs n-type (Si) >1x1019cm-3

10 nm In0.1Ga0.9As n-type (Si) ≥1x1019cm-3

80 nm GaAs p-type (C) >1x1020 cm-3

80 90 100 110 120

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Energ

y (e

V)

Position (nm)

TD1: Baseline StructureTD1: Baseline Structure

T.A. Richard et. al. Appl. Phys. Lett. 63, pp. 3613-5, (1993)

PVCR of 21 Grown on a GaAs substrate

Target structure based on published III-V Device (GaAs/In0.1Ga0.9As)

S.L. Rommel

Strained p-GaAs (C)

Strained n-InGaAs (Si) QW, 10nm wide

n-GaAs (Si)

TEM image confirms the excellent crystal quality and sharp interface.

0 20 40 60 80 1001015

1016

1017

1018

1019

1020

In

Si

C

C,S

i conc (cm

-3)

Depth (nm)

Ga

10-2

10-1

100

In,

Ga

com

p.

SIMS profile of TD1 shows doping in mid-1019 cm-3.

TD1: TEM image & SIMS profileTD1: TEM image & SIMS profile

S.L. Rommel

0.00 0.25 0.50 0.75 1.00

10-5

10-4

10-3

425,

5 m

in. N

2

Curr

ent (A

)

Voltage (V)

GaAs/InGaAs Esaki on Si

No Annea

l

• Post growth anneal removes H2 from epi growth; Richard et. al.

• Result:Result: Large increase in PVCR

• Similar trend is observed here:• No annealNo anneal: PVCR 2.4 - 7• 425 425 ooC, 5 min, NC, 5 min, N22: PVCR 24

• All devices reported use 425oC, 5 min. N2 anneal.

Influence of Anneal on PVCRInfluence of Anneal on PVCR

S.L. Rommel

• Devices of ~ 3.5 m2 show larger PVCR of 27

• Current density is low due to doping levels.

KEY POINT:

Exceeds GaAs world record PVCR (25) reported by Holonyak, et. al.

TD1: I-V CharacteristicsTD1: I-V Characteristics

0.0 0.2 0.4 0.6 0.8 1.010-2

10-1

100

PVCR 27

Cur

rent

Den

sity

(A

/cm

2 )

Voltage (V)

S.L. Rommel

2.0 2.4 2.8 3.2 3.6 4.00

5

10

15

20TD

1

Peak-t

o-V

alle

y C

urr

ent R

atio

1000/Temperature (1/K)

Hol

onya

k et

. al

Proc

. IR

E 1

960

500 450 400 350 300 250

2.0 2.4 2.8 3.2 3.610-1

100

101

JV (TD1)

Curr

ent D

ensi

ty (A

/cm

2 )

1000/Temperature (1/K)

Jp (TD1)

500 450 400 350 300

Temperature (K)

Temperature (K)TD1: Temperature ResponseTD1: Temperature Response

KEY POINTS: Similar response as

published GaAs Esaki diodes.

PVCR remains greater then or equal to the room temperature PVCR of Si/SiGe TDs.

S.L. Rommel

• Higher current density (as high as 1 kA/cm2)• Higher PVCR: 43

TD2: 20% InTD2: 20% In

0.0 0.2 0.4 0.6 0.8 1.0 1.2100

101

102

Cur

rent

Den

sity

(A

/cm

2 )

Voltage (V)

PVCR 43

JP = 500 A/cm2


10 nm In0.2Ga0.9As n-type (Si) ≥9x1018cm-3

80 nm GaAs p-type (C) =5x1019 cm-3

KEY POINT:

Increasing In composition elevates current density and PVCR

S.L. Rommel

1.1. World Record World Record GaAs PVCR

2.2. Fourth Highest reported PVCR Fourth Highest reported PVCR on any material system or Tunnel diode.

TD3: All 10% InGaAs Esaki DiodeTD3: All 10% InGaAs Esaki Diode

0.0 0.2 0.4 0.6 0.8 1.0 1.2100

101

102

PVCR 56

Cur

rent

Den

sity

(A

/cm

2 )Voltage (V)


10 nm In10 nm In0.10.1GaGa0.90.9As n-type (Si) ≥9x10As n-type (Si) ≥9x101818cmcm-3-3

80 nm In80 nm In0.10.1GaGa0.90.9As p-type (C) =5x10As p-type (C) =5x101919 cm cm-3-3

KEY POINTS:

250 A/cm2

S.L. Rommel

Key pointsKey points:

Lower PVCR than other structures

• Due to elimination of quantum well

TD4: Graded 10% InGaAs Esaki DiodeTD4: Graded 10% InGaAs Esaki Diode

0.0 0.2 0.4 0.6 0.8 1.01

10

100

TD4: PVCR 8

Cu

rren

t D

ensi

ty (

A/c

m2 )

Voltage (V)


10 nm In10 nm In0.10.1GaGa0.90.9As n-type (Si) ≥9x10As n-type (Si) ≥9x101818cmcm-3-3

80 nm GaAs p-type (C) =5x1080 nm GaAs p-type (C) =5x101919 cm cm-3-3

10 nm gradedGaAs to In10 nm gradedGaAs to In0.10.1GaGa0.90.9As n-type As n-type

65 A/cm2

S.L. Rommel

Comparison with Devices in LiteratureComparison with Devices in Literature

1 10 10010-3

10-2

10-1

100

101

102

103

104

Franks, 1965Eberl, 2001

Chung, 2006

Wang, 2003Ismail, 1993

See, 2001Rommel, 1

998

Franks, 1965

Holonyak, 1960Richard, 1993

Smet, 1993

Day,1993

Tsai, 1994

Broekaert,1989

Cohen, 1995

Si Substrate GaAs Substrate InP Substrate This Study

Pea

k C

urr

ent

Den

sity

(kA

/cm

2 )

PVCR

Richard, 1993

Holonyak, 1960

S.L. Rommel

Comparison with Devices in LiteratureComparison with Devices in Literature

1 10 10010-3

10-2

10-1

100

101

102

103

104

Franks, 1965Eberl, 2001

Chung, 2006

Wang, 2003Ismail, 1993

See, 2001Rommel, 1

998

Franks, 1965

Holonyak, 1960Richard, 1993

Smet, 1993

Day,1993

Tsai, 1994

Broekaert,1989

Cohen, 1995

TD1

TD2

TD3

TD4

Si Substrate GaAs Substrate InP Substrate This Study

Pea

k C

urr

ent

Den

sity

(kA

/cm

2 )

PVCR

Richard, 1993

Holonyak, 1960

S.L. Rommel

ConclusionsConclusions– Enabling Technology: ART

• Developed by AmberWave

– World Record: GaAs-based Esaki diodes

• Fourth highest PVCR reported for anyany tunnel diode

• Realized on a Si Substrate.

• Structure are grown entirely by CVD.

• Temperature response comparable to bulk GaAs Esaki Diodes

0.00 0.25 0.50 0.75 1.0010-2

10-1

100

101

102

103

TD1: P

VCR 2

7

TD3: PVCR 56

TD4: PVCR 10

Cur

rent

Den

sity

(A

/cm

2 )

Voltage (V)

TD2: PVCR 43

S.L. Rommel

RIT: R. Rafaelle, S. Hubbard, S. Polly, C. Bailey, and SMFL Staff

Amberwave: M. Curtin, C. Major and the other lab staff

Micron Technology: D. MacMahon (TEM imaging)

Silvaco Corporation: TCAD software donation

Project supported by National Science Foundation grants ECCS-0725760 and ECCS-0832653

AcknowledgementsAcknowledgements

2008 iedm presentation

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