Proceedings

2007 IEEE nternational Conference on Electron Devices

and Solid-State Circuits

December 20-22, 2007

Tayih Landis Hotel, Tainan, Taiwan

Volume I

Fuh-Cheng Jong, Southern Taiwan University, Taiwan.

Chien-Min Cheng, Southern Taiwan University, Taiwan.

Max Chung, Southern Taiwan University, Taiwan.

Shih-Fang Chen, Southern Taiwan University, Taiwan.

Cheng-Fu Yang, National University of Kaoshiung, Taiwan.

Hsien-Tsai Wu, National Don-Hwa University, Taiwan.

Wen-Jeng Tzou, Southern Taiwan University, Taiwan.

International Advisory Committee

P. K. Chu, City University of Hong Kong.

S. Dimitrijev, Griffith University, Australia.

J. Deen, McMaster University, Canada.

T. Hattori, Musashi, Institute of Technology, Japan.

K. ltoh, Hitachi, Japan.

H. Iwai, Tokyo Institute of Technology, Japan.

H-S Philip Wong, Stanford University, USA.

T. Hiramoto, Tokyo University, Japan.

P. T. Lai, University of Hong Kong.

M. Ostling, Royal Institute of Technology, Sweden.

C. Surya, Hong Kong Polytechnic University

N. Stojadinovic, University ofNis, Serbia.

A. Wang, Illinois Institute of Technology, USA.

C. Yang, Santa Clara University, USA.

J. Woo, University of California, USA.

N. W. Cheung, UC Berkeley, USA.

P. K. Yu, UC San Diego, USA.

F. Schwietz, Technical University Illmenau, Germany.

Z. Yu, TsingHua University, China.

R. Chau, Intel, USA.

R. Huang, Peking University, China.

A. Ortiz-Conde, Simon Boltvar University, Venezuela.

M. Shur, Rensselaer Polytechnic Institute, USA.

A. Rezazadeh, University of Manchester, UK.

S. Selberherr, T~chnische University Wien, Austria.

J. C. Lee, University of Texas at Austin, USA.

S. Cristoloveanu, Laboratorie de Physique des Composants a Semiconducteurs, France.

T. H. Ning, IBM.

B. Yu, NASA Ames Res. Center, USA.

S. Mirabbasi, University of British Columbia, Canada.

K. Iniewski, University ofAlberta, Canada.

S. Voinigescu, University of Toronto, Canada.

Ming-Chen Chen, Clarkson University, USA

Table of Content

Forward

PLENARY SESSION

IPOt Advances in Gallium Nitride-Based Electronics (keynote) J Ade;ida and V Kumar Nanotechnology Laboratory, Department of Electrical and Computer Engineerir and Department of Materials Science and Engineering, University ofIliinois, USA

IP02 The Implementation of Retinal Functions on CMOS ICs and Applications (keynote) Chung-Yu (Peter) Wu President/Chair Professor, at National Chiao Tung University, Taiwan

Their 7

IP03 Infrared Plasmonic Thermal Emitter and Its Application in Biological System (keynote) Si-Chen Lee Department of Electrical Engineering National Taiwan University, Taiwan

II

IP04 Semiconductor Foundry Partnership (keynote) Shih- We i Sun United Microelectronics Corp. Taiwan, ROC

13

INVITED SESSIONS

IAt Transport in Carbon Nanostructures Cary Y Yang Center for Nanostructures, Santa Clara University Santa Clara, California

15

IA2 Anything more than size in nanoelectronics Wei-Xin Ni, Jia-Min Shieh, and Horng-Chih Lin

National Nano Device Laboratories, Taiwan.

17

IA3 Ultra High Power Light-Emitting Diodes with Electroplating Technology Y. K Su, IEEE Fellow, KC. Chen, C. L. Lin Institute of Microelectronics and Advanced Optoelectronic Technology Center, National Cheng Kung University, Taiwan.

19

IA4 Technology Roadmaps on the Ballistic Transport in Strain Engineered Nanoscale CMOS Devices Steve S. Chung, Y. J Tsai, C. H. Tsai, P. W. Liu, Y. H. Lin. C. T. Tsai. G. H. Ma. S. C. Chien, and S. W. Sun Department of Electronic Engineering, National Chiao Tung University, Taiwan

23

IA5 Saturation Effect of Electroabsorption Modulator on Analog Link Gain and Linearity P.K.L. Yu, XB. Xie, G.£. Bells,l Shubin, and WS.C Chang Department of Electrical and Computer Engineering, University of Cali fomia San Diego

27

IA6 The Current Conduction Issues in High-k Gate Dielectrics Hei Wong Department of Electronic Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong.

31

IA7 Thin Gate Oxide Reliability Study Using Nano-Scaled Stress Y L. Wu, C Y Hwang, C H Liang, S. T Lin, and J J Liou Department of Electrical Engineering, National Chi Nan University, Taiwan

37

IB1 Quantum Transport Devices Application in Multi-walled Nano-tubes Y Ochiai. T Kawamura, T Morimoto. N. Aoki and JP. Bird Chiba University, Japan, SUNY Buffalo, USA

Carbon­ 41

IB2 Fabrication of Silicon-on-Insulator Substrates Using Plasma Technologies Paul K. Chu Department of Physics and Materials Science, City University of Hong Kong, Hong Kong

43

IB3 Design and Modeling of RF ICs for Low-Noise and Low-Power Transceivers Chih-Hung Chen, Andrew Leung, and Horace Gon Department of Electrical and Computer Engineering, McMaster University, Hamilton, Canada

47

IB4 ESD Simulation using Compact Models: from VO Cell to Full Chip Yuanzhong (Paul) Zhou, Thorsten Weyl, Jean-Jacques Hajjar, Kenneth P. Lisiak ESD Department, Analog Devices Inc., Wilmington, MA 01887, USA.

53

IB5 Modeling tbe Drain Current of DG FD SOl NMOS Devices with N+/P+ Poly ToplBottom Gate C H Hsu, J B. Kuo Dept of Elec Eng, National Taiwan University Taipei, Taiwan

59

IB6 Hf02 CMOS Device and Circuit Reliability J S. Yuan Electrical Engineering and Computer Science, University of Central Orlando, Florida, U.S.A

Florida,

63

IB7 Efficient Transistor Optimization with Stress Enhanced Notch-gate Tecbnology for sub-90nm CMOSFET W-K. Yeh, C-W Hsu, C-M. Lai, C-T Lin Y-K. Fang, C-H. Hsu, L.-W Chen, Y-T Huang, C.-T TSGI Department of Electrical Engineering, National University of Kaohsiung, Taiwan.

67

II

Fabrication of Silicon-on-Insulator Substrates Using Plasma Technologies

Paul K. Chu

Abstract – This invited paper reviews the work done in our laboratory on the fabrication of silicon-on-insulator (SOI) materials using plasma hydrogenation and the synthesis of novel silicon-on-diamond and silicon-on-dual-insulator SOI structures with better thermal properties.

I. INTRODUCTION

As device dimensions continue to shrink to the deep sub-micrometer regime, bulk silicon encounters some intrinsic deficiencies. Silicon-on-insulator (SOI) possesses many advantages over bulk silicon such as the reduction of parasitic capacitance, excellent sub-threshold slope, elimination of latch up, and resistance to radiation [1]. Hence, SOI is the preferred substrate for high speed, low power devices such as fully-depleted metal-oxide semiconductor field effect transistors (MOSFET). Plasma technology is very useful in the fabrication of SOI materials and this paper reviews recent work performed in our laboratory in this area.

II. PLASMA HYDROGENATION

The conventional ion cutting process involves

beam-line hydrogen ion implantation that introduces excessive damage to the silicon substrate and can also be quite costly. Therefore, we have investigated the use of economical low-energy plasma hydrogenation to substitute for hydrogen ion implantation to produce SOI materials [2, 3]. Boron ion implantation is first used to introduce H-trapping centers into the Si wafer. In lieu of the well known interactions between boron and hydrogen, lattice damage such as dangling bonds traps H atoms is observed to lead to surface blistering during hydrogenation or upon post-annealing at higher temperature. B ion implantation and the subsequent processes control the uniformity of the H trapping centers and depths. While the trapping centers can be introduced by boron ion implantation in this study, it should be pointed out that there are many other means to accomplish the same purpose without implantation. Using this technology, we have successfully fabricated SOI structure [4].

The process commences with a p-type 1-35 Ω-cm <111> Si wafer. 5 x1015 cm-2 B+ is implanted into the Si substrate at 170 kV followed by thermal activation at 900oC in a nitrogen ambient for 20 minutes. Plasma hydrogenation is subsequently conducted at 280oC in a plasma immersion ion implanter (PIII) equipped with a radio frequency (RF) plasma source for 10 minutes [5]. These conditions are chosen to introduce sufficient hydrogen atoms into the substrate without causing premature surface blistering. After argon plasma activation, the hydrogenated sample is bonded to a Si handle wafer with an oxide top layer. Finally, the bonded structure is thermally annealed at 400oC to induce Si layer cleavage and transfer, yielding the SOI structure depicted in Fig. 1.

Fig. 1. Cross-sectional transmission electron micrograph of the SOI structure produced by plasma hydrogenation and ion cutting.

The hydrogen distribution in the SOI sample is

examined by elastic recoil analysis (ERA) and within the detection limit, no hydrogen can be detected in the bulk of the transferred Si layer other than a surface H concentration peak. RBS channeling indicates that the average value of the channeling minimum yield (χmin) in the entire transferred Si layer is ~8% which can be further improved by annealing. These results indicate the capability of the plasma hydrogenation process for fabrication of high-quality Si transferred layers, with implanted B damage as trapping centers.

Paul K Chu is with the Department of Physics and Materials

Science, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong, E-mail: paul.chu@cityu.edu.hk

Buried SiO2 Transferred Layer

SOI surface

SiO2

200n

431-4244-0637-4/07/$20.00 ©2007 IEEE

In addition, we have evaluated the feasibility of using plasma hydrogenation to realize Si1-xGex layer transfer, which is critical to the fabrication of SiGe-on-insulator (SGOI), strained Si on insulator (SSOI) and related materials. SiGe/Si heterostructures consisting of a 210 nm thick Si0.79Ge0.21 epitaxial layer on <100> p-Si substrate with a resistivity of 1-10 Ω-cm are fabricated by chemical vapor deposition (CVD). The sample is implanted with 1.5x1016

cm-2

He+

at 45 kV and then

annealed at 850oC for 10 minutes in argon to relax the as-grown strained SiGe/Si heterostructure. Hydrogenation is then performed at a negative substrate bias of several hundred volts at 320~380oC for 1.5 hours. After hydrogenation, both the samples with and without He-induced relaxation show surface bubbles. The ERA spectra in Fig. 2 indicate different H distributions in the hydrogenated samples with and without He implantation. A small near-surface hydrogen peak is observed in both samples. The peak position matches the expected implantation depth of hydrogen impacting the surface of the wafer with a few hundred volts during hydrogenation. Little or no notable hydrogen and accumulation can be detected in the bulk SiGe sample without He implantation. However, in the He relaxed and hydrogenated sample, hydrogen atoms are trapped at a specific depth below the sample surface resulting in a significant H peak deep in the substrate.

Fig. 2. He+ Elastic recoil analysis spectra acquired from hydrogenated Si0.79Ge0.21/Si heterostructures: (a) As-grown CVD and (b) After He+

implantation and

post-annealing.

III. NOVEL SOI STRUCTURES WITH GOOD

THERMAL CONDUCTIVITY Wider applications of SOI in ULSI are stifled by

self-heating effects caused by the poor thermal conductivity of the buried silicon dioxide layer [6]. We have studied alternative buried insulators with better thermal conductivity and successfully fabricated SOI structures incorporating aluminum nitride or diamond-like carbon as the substitute for the buried silicon dioxide layer [7]. Fig. 3 displays the TEM micrograph of the SOD (silicon-on-diamond) structure.

Fig. 3. (a) TEM micrograph of the SOD structure formed using wafer bonding and hydrogen-induced layer transfer. (b) HRTEM micrograph of the interfacial region between the top Si layer and buried DLC layer, indicating a defect-free and single crystal Si layer as well as an abrupt bonded interface.

The breakdown field of the as-deposited DLC film is

4.2 MV/cm which compares reasonably well with previously reported results. When the sample is annealed in the furnace at temperatures under 900ºC, the breakdown field does not change. When the annealing temperature reaches 900ºC, the breakdown field begins to decrease, but the changes are not obvious. However, when the temperature is increased to 1000ºC, the breakdown field diminishes significantly. It can be inferred that graphitization of our materials does not become significant until the annealing temperature reaches 1000ºC and our Raman results (not shown here) are consistent with the electrical measurements. The RTA results indicate that after RTA at 900ºC or 1000ºC, no appreciable graphitization can be detected from our electrical data. Based on our results, the DLC synthesized using the special PIII&D process can withstand furnace annealing and RTA up to 900ºC, rendering the materials and process compatible with thin film transistor (TFT) processing.

The resistance against graphitization has been

further investigated and the presence of hydrogen in the DLC layer is found to retard the deleterious process up to about 900oC [8]. The thermal stability of exposed and buried DLC films is compared using Raman spectroscopy and x-ray photoelectron spectroscopy (XPS). Our Raman analysis indicates that the obvious separation of the D and G peaks indicative of nano-crystalline graphite emerges at 500oC in the exposed DLC film. In comparison, the separation appears in the buried DLC film only at annealing temperatures above 800oC. Analysis of the XPS C1s core level spectra discloses that the (sp3+C-H) carbon content of the unprotected DLC film decreases rapidly

44

between 300-700oC indicating the rapid transformation of sp3-bonded carbon to sp2-bonded carbon combined with hydrogen evolution. In contrast, the decrease in the (sp3+C-H) carbon content in the buried DLC film is slower below 800oC. ERA results confirm that this superior thermal stability is due to the slower hydrogen out-diffusion from the buried DLC film thereby impeding the graphitization process.

Even though a diamond-like-carbon (DLC) layer

can be used to substitute for the buried SiO2 layer in silicon-on-insulator (SOI) to mitigate the self-heating effects as shown previously, there are drawbacks associated with the inferior Si/DLC interface, inadequate thermal stability for regular CMOS processing, as well as carbon-silicon inter-diffusion at the Si/DLC interface that may limit future applications of the SOD structure. Hence, we introduce a silicon dioxide barrier layer between the Si film and DLC buried layer to form a silicon-on-SiO2/DLC dual-insulator (SODI) structure to tackle these problems [9]. The cross-sectional high-resolution transmission electron microscopy in Fig. 4 reveals that the Si/insulator interface is atomically flat and the top Si layer has nearly perfect crystalline quality. The SiO2/DLC dual insulator (SDOI) layer retains excellent insulating properties at typical CMOS processing temperatures.

Fig. 4: (a) TEM micrograph of the SiO2/DLC SODI structure. (b) HRTEM micrograph of the interfacial region between the top Si layer and buried insulator structure showing a sharp Si/SiO2 interface and defect-free crystalline Si layer

Similar to the work conducted on SOD, we measure

the breakdown electric fields of the SODI sample at various temperatures to determine the thermal stability. As shown in Fig. 5, even at an annealing temperature as high as 1000oC, the breakdown field of 4.6±0.1 MV/cm remains more or less unchanged. This is a substantial improvement over our previous SOD structure which

shows significant degradation at 1000oC. The enhanced property is believed to be due to two reasons. First of all, the SiO2 layer has high thermal stability. Secondly, the SiO2 layer impedes hydrogen out-diffusion from the underlying DLC layer. It is also noted that the insulating property of this SiO2/DLC dual layer is better than that of a typical buried oxide produced by SIMOX

Fig. 5: Influence of the annealing temperature on the breakdown electric fields of the SODI structure.

Numerical simulation reveals that the negative

differential resistance and channel temperature are significantly reduced compared to those of the same MOSFET (metal oxide semiconductor field effect transistors) fabricated in conventional SiO2-based SOI, suggesting that the silicon-on-dual-insulator (SODI) structure can alleviate the self-heating penalty effectively.

IV. CONCLUSION

This paper succinctly reviews our recent work on the fabrication of SOI materials using low-energy plasma hydrogenation and synthesis of novel SOI structures such as silicon-on-diamond and silicon-on-dual-insulator using plasma immersion ion implantation. PIII is used to both produce the diamond-like carbon layer and implant hydrogen to cause layer cleavage in the ion cutting process.

ACKNOWLEDGEMENT

The work described here was supported by City

University of Hong Kong Direct Allocation Grant # 9360110.

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45

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