2. digital electronics combinational tests .pdf

8/18/2019 2. Digital Electronics Combinational Tests .pdf

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Chapter 1

Analog to Digital Conversion

1.

1p

The process of converting the analog signal into a digital signal

consists of:a.) converting a continuous signal to a digital number

b.) converting a broken signal to a digital numberc.) converting a continuous signal to a analog number

d.) converting a broken signal to a analog number

Correct answer a.)

2.

1p

The figure below shows:

a.) block diagram of an analog filterb.) block diagram of a digital analog to converter;

c.) block diagram of a digital filter;d.) block diagram of an analog to digital converter

Correct answer d.)

3.2p

From a formal standpoint, the A-D conversion involves only:

a.) sampling followed by quantification of the analog signal;

b.) sampling of the analog signal;

c.) quantification of the analog signald.) quantification followed by sampling of the analog signal;

Correct answer a.)

4.

2p

Sampling an analog signal means means:

a.) that the sample selection is based on the average value of the


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signalb.) that the sample selection is based on signal peaksc.) taking of samples of the signal at some intervals

d.) taking of samples of the signal at predetermined intervals

Correct answer d.)

5.

1p

Figure 1.1 shows a digital anolog converter. Digital word D0 - D7

is:

Figura 1.1

a.) input signalb.) output signal

c.) control signal

d.) synchronization signal

Correct answer b.)

6.3p

Figure 1.1 shows a digital anolog converter. The full scale voltagerange (VF) is:

Figura 1.1

a.)+−

−= REFREFF VVV

b.)

−

+=

REF

REFF

V

VV

c.) _REFREFF VVV −= +

d.)

+

−=

REF

REFF

V

VV


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Correct answer a.)

7.

3p

Assume the digital word 10010011. The Most Significant Bit

(MSB) is:a.) All bits with value "1"

b.)

c.)

d.) All bits with value "0"

Correct answer b.)

8.

3p

Assume the digital word 10010011. The Least Significant Bit

(LSB) is:a.) All bits with value "1"b.)

c.)

d.) All bits with value "0"

Correct answer c.)

9.

3p

Binary number N=1010 B has the following decimal

representation:a.) N=10 Db.) N=2 D

c.) N=14 D

d.) N10=6 D

Correct answer a.)

10.3p

Binary number N=0010 B has the following decimalrepresentation:a.) N=10 D

b.) N=2 Dc.) N=14 Dd.) N=6 D


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Correct answer b.)

11

3p


representation:a.) N=10 D

b.) N=2 Dc.) N=14 Dd.) N=6 D

Correct answer c.)

12

3p


representation:a.) N=10 D

b.) N=2 Dc.) N=14 D

d.) N=6 D

Correct answer d.)

13.3p

Binary number N=1010 B has the following hexadecimalrepresentation:a.) N=A H

b.) N=2 H

c.) N=E Dd.) N=6 D

Correct answer a.)

14.

3p

Binary number N=0010 B has the following hexadecimal

representation:a.) N=A Hb.) N=2 H

c.) N=E Dd.) N=6 D

Correct answer b.)

14.

3p

Binary number N=1110 B has the following hexadecimal

representation:a.) N=A H

b.) N=2 Hc.) N=E Dd.) N=6 D

Correct answer c.)


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15.3p

Binary number N=0110 B has the following hexadecimalrepresentation:a.) N=A H

b.) N=2 H

c.) N=E Dd.) N=6 D

Correct answer d.)

16.

3p

Hexadecimal number N=A87C H may be encoded, using as

hexadecimal to binary code (8421) as:a.) 1010 1000 0111 1100b.) 11001010 0011 1000

c.) 1010 0011 1000 0001d.) 1010 0001 1000 0101

Correct answer a.)

17.3p

Hexadecimal number N=C001 H may be encoded, using ashexadecimal to binary code (8421) as:a.) 1010 0000 0000 1000

b.) 1010 0000 0000 0001

c.) 0001 0000 0000 1010

d.) 1101 1111 0000 0110

Correct answer b.)


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Chapter 2

Combinational Circuits – Representing

1.1p

Figure 2.1 shows the block diagram of a combinational logiccircuit.

CLC

X1 X2

Xn Ym

Y1 Y2

Figure 2.1

The set { }n21 X,X,XX K= is:a.) the set of states

b.) the set of inputs

c.) the set of outputs

d.) the set of input-output functions

Correct answer b.)

2.

1p

Figure 2.1 shows the block diagram of a combinational logic

circuit.

CLC

X1 X2

Xn Ym

Y1 Y2

Figure 2.1

The set { }m21 Y,Y,YY K= is: a.) the set of states




Correct answer c.)

3. Figure 2.1 shows the block diagram of a combinational logic


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1p circuit.

CLC

X1 X2

Xn Ym

Y1 Y2

Figure 2.1

Knowing that:

( )n2111 X,...,X,Xf Y =

( )n2122 X,...,X,Xf Y =

M

( )n21mmX,...,X,Xf Y =

The set { }m21 f ,f ,f f K= is: a.) the set of states




Correct answer d.)

4.2p

Figure 2.1 shows the block diagram of a combinational logiccircuit.

CLC

X1 X2

Xn Ym

Y1 Y2

Figure 2.1

Noting:

{ }n21 X,X,XX K=

{ }m21 Y,Y,YY K=

{ }m21 f ,f ,f f K= where:

X the set of inputsY the set of outputs

f the set of input-output functions.

the combinational logic circuit is defined as:a.) { }f ,Y,XSc =


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b.) { }Y,XSc = c.) { }f ,XSc = d.) { }f ,YSc = Correct answer a.)


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Chapter 3

Logic Gates

1.

1p

The symbol of an “AND” logic gate, ANSI standard is:

a.)

b.)

c.)

d.)

Correct answer a.)

2.1p

The symbol of a “NAND” logic gate, ANSI standard is:

a.)

b.)

c.)

d.)

Correct answer c.)

3.1p

The symbol of an “OR” logic gate, ANSI standard is:

a.)

b.)


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c.)

d.)

Correct answer b.)

4.

1p

The symbol of a “NOR” logic gate, ANSI standard is:

a.)

b.)

c.)

d.)

Correct answer d.)

5.

1p

The symbol of an “AND” logic gate, DIN standard is:

a.)

b.)

c.)

d.)

Correct answer a.)

6.

1p

The symbol of a “NAND” logic gate, DIN standard is:

a.)

b.)

c.)

d.)


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Correct answer c.)

7.1p

The symbol of an “OR” logic gate, DIN standard is:

a.)

b.)

c.)

d.)

Correct answer b.)

8.

1p

The symbol of a “NOR” logic gate, DIN standard is:

a.)

b.)

c.)

d.)

Correct answer d.)

9.1p

The symbol of a “NOT” logic gate, DIN standard is:

a.)

b.)

c.)

d.)

Correct answer d.)

10.1p

The symbol of a “NAND” logic gate, ANSI standard is:


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a.)

b.)

c.)

d.)

Correct answer c.)

11.1p

The figure shows the symbol of a logic gate, type:

a.) AND standard ANSI;

b.) AND standard DIN;

c.) NAND standard ANSI;

d.) NAND standard DIN;

Correct answer a.)

12.

1p



b.) AND standard DIN;c.) NAND standard ANSI;


Correct answer b.)

13.1p





d.) NAND standard DIN;Correct answer c.)


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14.1p






Correct answer d.)

15.1p


a.) OR standard ANSI;

b.) OR standard DIN;

c.) NOR standard ANSI;

d.) NOR standard DIN;

Correct answer a.)

16.1p



b.) OR standard DIN;c.) NOR standard ANSI;


Correct answer b.)

17.1p






Correct answer c.)


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18.1p






Correct answer d.)

19.1p




c.) NOT standard ANSI;

d.) NOT standard DIN;

Correct answer c.)

20.

1p




c.) NOT standard ANSI;d.) NOT standard DIN;

Correct answer d.)

21.

4p

The logic function implemented by an AND gate is:

a.) AB)B,A(Y =

b.) AB)B,A(Y =

c.) BA)B,A(Y +=

d.) BA)B,A(Y +=

Correct answer a.)

22.

4p

The logic function implemented by a NAND gate is:


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a.) AB)B,A(Y = b.) AB)B,A(Y =

c.) BA)B,A(Y +=

d.) BA)B,A(Y +=

Correct answer b.)

23.

4p

The logic function implemented by an OR gate is:

a.) AB)B,A(Y =

b.) AB)B,A(Y =

c.) BA)B,A(Y +=

d.) BA)B,A(Y +=

Correct answer c.)

24.

4p

The logic function implemented by a NOR gate is:

a.) AB)B,A(Y =

b.) AB)B,A(Y =

c.) BA)B,A(Y +=

d.) BA)B,A(Y +=

Correct answer d.)

25.1p

The logic function implemented by a NOT gate is:

a.) AB)B,A(Y =

b.) AB)B,A(Y =

c.) A)A(Y =

d.) A)A(Y =

Correct answer d.)

26.3p

The logic function AB)B,A(Y = is implemented using:

a.) AND gate

b.) NAND gate

c.) OR gate


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d.) NOR gateCorrect answer a.)

27.

3pThe logic function AB)B,A(Y = is implemented using:

a.) AND gate

b.) NAND gate

c.) OR gate

d.) NOR gate

Correct answer b.)

28.

3p

The logic function BA)B,A(Y += is implemented using:

a.) AND gate

b.) NAND gate

c.) OR gate

d.) NOR gate

Correct answer c.)

29.

3pThe logic function BA)B,A(Y += is implemented using:

a.) AND gate

b.) NAND gate

c.) OR gate

d.) NOR gate

Correct answer d.)

30.

1pThe logic function A)A(Y = is implemented using:

a.) NOT gate

b.) NAND gate

c.) OR gate

d.) NOR gate

Correct answer a.)

31.

4p

AND logic function is described by the truth table noted:

a.) Inputs OutputX1 X2 Y

0 0 0


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0 1 01 0 0

1 1 1

b.) Inputs Output

X1 X2 Y

0 0 1

0 1 1

1 0 1

1 1 0

c.)Inputs Output

X1 X2 Y

0 0 0

0 1 1

1 0 1

1 1 1

d.) Inputs Output

X1 X2 Y

0 0 1

0 1 0

1 0 0

1 1 0Correct answer a.)

32.4p

NAND logic function is described by the truth table noted:

a.) Inputs Output

X1 X2 Y

0 0 0

0 1 0

1 0 0

1 1 1


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b.) Inputs OutputX1 X2 Y

0 0 1

0 1 1

1 0 1

1 1 0

c.) Inputs Output

X1 X2 Y

0 0 0

0 1 1

1 0 1

1 1 1

d.) Inputs Output

X1 X2 Y

0 0 1

0 1 0

1 0 0

1 1 0

Correct answer b.)

33.

4p

OR logic function is described by the truth table noted:

a.) Inputs Output

X1 X2 Y

0 0 0

0 1 0

1 0 0

1 1 1

b.) Inputs Output

X1 X2 Y

0 0 1

0 1 11 0 1

1 1 0


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c.) Inputs Output

X1 X2 Y

0 0 0

0 1 1

1 0 1

1 1 1

d.) Inputs Output

X1 X2 Y

0 0 1

0 1 0

1 0 0

1 1 0

Correct answer c.)

34.

4p

NOR logic function is described by the truth table noted:

a.) Inputs Output

X1 X2 Y

0 0 0

0 1 0

1 0 0

1 1 1b.) Inputs Output

X1 X2 Y

0 0 1

0 1 1

1 0 1

1 1 0

c.) Inputs Output

X1 X2 Y

0 0 0

0 1 1

1 0 1

1 1 1


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d.) Inputs OutputX1 X2 Y

0 0 1

0 1 0

1 0 0

1 1 0

Correct answer d.)

35.3p

Funcţia logică NOT este descrisă de tabelul de adevăr notat::

a.) Inputs Output

X1 X2 Y

0 0 0

0 1 0

1 0 0

1 1 1

b.) Inputs Output

X1 X2 Y

0 0 1

0 1 1

1 0 1

1 1 0

c.) Inputs Output

X1 X2 Y

0 0 0

0 1 1

1 0 1

1 1 1

d.) Input Output

X Y

0 1

1 0

Correct answer d.)


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36.4p

The truth table presented below, describes the logical function:

Inputs Output

X1 X2 Y

0 0 0

0 1 0

1 0 0

1 1 1

a.) AND

b.) NAND

c.) OR

d.) NOR

Correct answer a.)

37.4p


Inputs Output

X1 X2 Y

0 0 1

0 1 1

1 0 1

1 1 0

a.) AND

b.) NAND

c.) OR

d.) NOR

Correct answer b.)

38.

4p


Inputs Output

X1 X2 Y

0 0 0

0 1 1

1 0 1

1 1 1

a.) AND

b.) NAND


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c.) ORd.) NOR

Correct answer c.)

39.

4p


Inputs Output

X1 X2 Y

0 0 1

0 1 0

1 0 0

1 1 0

a.) ANDb.) NAND

c.) OR

d.) NOR

Correct answer d.)

40.

2p


Inputs Output

X Y

0 1

1 0

a.) AND

b.) NAND

c.) NOT

d.) NOR

Correct answer c)

41.

4p

The waveforms, associated with an AND-type logic gate, are

shown in figure:

a.)

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y


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b.)

A

B

Y

0

1

0

0

0

11

1

01 1

1

c.)

A

B

Y

0 0

0

0 0

1 1

11

1 11

d.)

Y 000

00

00

B

A

11

1

1

1

Correct answer a)

42.4p

The waveforms, associated with a NAND-type logic gate, areshown in figure:

a.)

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

b.)

A

B

Y

0

1

0

0

0

11

1

01 1

1


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c.)

A

B

Y

0 0

0

0 0

1 1

11

1 11

d.)

Y 000

00

00

B

A

11

1

1

1

Correct answer b)

43.

4p

The waveforms, associated with an OR-type logic gate, are shown

in figure:

a.)

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

b.)

A

B

Y

0

1

0

0

0

11

1

0 1 1

1

c.)

A

B

Y

0 0

0

0 0

1 1

11

1 11


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d.)

Y 000

00

00

B

A

11

1

1

1

Correct answer c)

44.

4p

The waveforms, associated with a NOR-type logic gate, are shown

in figure:

a.)

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

b.)

A

B

Y

0

1

0

0

0

11

1

01 1

1

c.)

A

B

Y

0 0

0

0 0

1 1

11

1 11

d.)

Y 000

00

00

B

A

11

1

1

1

Correct answer d)

45.2p The waveforms, associated with a NOT-type logic gate, are shownin figure:


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a.)

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

b.)

A

B 1

0

0

1

c.)

A

B

Y

0 0

0

0 0

1 1

11

1 11

d.)

Y 000

00

00

B

A

11

1

1

1

Correct answer b)

46.4p

The figure presented below shows the waveforms of a logic gatetype:

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

a.) AND

b.) NAND

c.) OR

d.) NOR

Correct answer a)


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47.

4p

The figure presented below shows the waveforms of a logic gate

type:

A

B

Y

0

1

0

0

0

11

1

01 1

1

a.) AND

b.) NAND

c.) OR

d.) NORCorrect answer b)

48.

4p


type:

A

B

Y

0 0

0

0 0

1 1

11

1 11

a.) AND

b.) NAND

c.) OR

d.) NOR

Correct answer c)

49.

4p


type:

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

1 1

11 1

1

0

0

0

0

0 00

A

B

Y

a.) AND

b.) NAND


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c.) ORd.) NOR

Correct answer d)

50.

2p


type:

A

B 1

0

0

1

a.) AND

b.) NAND

c.) NOT

d.) NOR

Correct answer c)


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Chapter 4

Logic Gates - Problems

1.

4pThe logic gate 321 X)XX(Y = may be implemented by the circuit:

a.)

b.)

c.)

d.)

Correct answer a)

2.4p

The logic gate 321 X)XX(Y = may be implemented by the circuit:

a.)

b.)

c.)


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d.)

Correct answer b)

3.

4pThe logic gate 321 X)XX(Y += may be implemented by the

circuit:

a.)

b.)

c.)

d.)

Correct answer c)

4.4p

The logic gate 321 X)XX(Y += may be implemented by the

circuit:

a.)

b.)

c.)

d.)

Correct answer d)


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5.

4p

The circuit shown in the figure below performs logic function:

a.)321 X)XX(Y +=

b.)321 XXXY =

c.)321 X)XX(Y +=

d.)321 X)XX(Y +=

Correct answer a)

6.

4p


a.)321 X)XX(Y +=

b.)321 XXXY =

c.)321 X)XX(Y +=

d.)321 X)XX(Y +=

Correct answer b)

7.4p


a.)321 X)XX(Y +=

b.)321 XXXY =

c.)321 X)XX(Y +=

d.) 321 X)XX(Y +=

Correct answer c)


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8.

4p


a.)321 X)XX(Y +=

b.)321 XXXY =

c.)321 X)XX(Y +=

d.)321 X)XX(Y +=

Correct answer d)

9.

4p

The following waveforms are generated by the circuit:

A

B

C

Y

a.)

b.)

c.)

d.)

Correct answer a)


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Chapter 5

Multiplexers, Demultiplexers

1.2p

Assume a logic circuit. Let’s note:[X]-input word

[Y]-output word

[S]-selection wordIn this case, the multiplexer is a circuit

a.) with "n" inputs and one output, which performs the function of a

rotary switch connected as shown:

b.) with one input and "n" outputs, which performs the function of arotary switch connected as shown:

c.) with "n" inputs and "m" outputs, which performs the function of a

rotary switch controlled by the output signal

d.) with "n" inputs and "m" outputs, which performs the function of a


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rotary switch controlled by the input signal

Correct answer a)

2.

2p

Assume a logic circuit. Let’s note:

[X]-input word

[Y]-output word

[S]-selection wordIn this case, the demultiplexer is a circuit

a.) with "n" inputs and one output, which performs the function of a


b.) with one input and "n" outputs, which performs the function of a


c.) with "n" inputs and "m" outputs, which performs the function of a

rotary switch controlled by the output signal


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d.) with "n" inputs and "m" outputs, which performs the function of arotary switch controlled by the input signal

Correct answer b)

3.

3p

The symbol of a multiplexer (4 bits ANSI standard) is:

a.)

b.)

c.)

d.)

Correct answer a)

4.

3p

The symbol of a multiplexer (4 bits DIN standard) is:

a.)

b.)


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c.)

d.)

Correct answer b)

5.

3p

The symbol of a demultiplexer (4 bits DIN standard) is:

a.)

b.)

c.)

d.)

Correct answer d)

6.

3p

The symbol of a demultiplexer (4 bits ANSI standard) is:

a.)

b.)


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c.)

d.)

Correct answer c)

7.)

1p

The figure presented below shows the symbol of:

a.) multiplexer, standard ANSI

b.) multiplexer, standard DIN

c.) demultiplexer, standard ANSI

d.) demultiplexer, standard DIN

Correct answer a)

8.)

1p






Correct answer b)

9.

1p



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Correct answer c)

10.1p






Correct answer d)

11.3p

Figure 5.1 presents the schematic diagram of a multiplexer 4 to 1.Figure 5.2 shows the simplified truth table associated.

Figure 5.1 Figure 5.2

If the selection word is {S0, S1}={0, 0}, then:

a.)0XY =

b.)1XY =

c.)2XY =

d.)3XY =

Correct answer a)

12. Figure 5.1 presents the schematic diagram of a multiplexer 4 to 1.


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3p Figure 5.2 shows the simplified truth table associated.



a.)0XY =

b.)1XY =

c.)2XY =

d.)3XY =

Correct answer b)

13.

3p

Figure 5.1 presents the schematic diagram of a multiplexer 4 to 1.

Figure 5.2 shows the simplified truth table associated.



a.)0XY =

b.) 1XY =

c.)2XY =

d.)3XY =

Correct answer c)

14.3p

Figure 5.1 presents the schematic diagram of a multiplexer 4 to 1.Figure 5.2 shows the simplified truth table associated.




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a.) 0XY =

b.)1XY =

c.)2XY =

d.)3XY =

Correct answer d)

15.3p

Figure 5.3 presents the schematic diagram of a demultiplexer 1 to4. Figure 5.4 shows the simplified truth table associated.



a.) }1,1,1,X{}YYY,Y{ 03210 =

b.) }1,1,X,1{}YYY,Y{ 13210 =

c.) }1,X,1,1{}YYY,Y{ 23210 =

d.) }X,1,1,1{}YYY,Y{ 33210 =

Correct answer a)

16.3p

Figure 5.3 presents the schematic diagram of a demultiplexer 1 to4. Figure 5.4 shows the simplified truth table associated.



a.) }1,1,1,X{}YYY,Y{ 03210 =

b.) }1,1,X,1{}YYY,Y{ 13210 =

c.) }1,X,1,1{}YYY,Y{ 23210 =

d.) }X,1,1,1{}YYY,Y{ 33210 =

Correct answer b)


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17.

3p

Figure 5.3 presents the schematic diagram of a demultiplexer 1 to

4. Figure 5.4 shows the simplified truth table associated.



a.) }1,1,1,X{}YYY,Y{ 03210 =

b.) }1,1,X,1{}YYY,Y{ 13210 = c.) }1,X,1,1{}YYY,Y{ 23210 =

d.) }X,1,1,1{}YYY,Y{ 33210 =

Correct answer c)

18.

3p

Figure 5.3 presents the schematic diagram of a demultiplexer 1 to

4. Figure 5.4 shows the simplified truth table associated.



a.) }1,1,1,X{}YYY,Y{ 03210 =

b.) }1,1,X,1{}YYY,Y{ 13210 =

c.) }1,X,1,1{}YYY,Y{ 23210 =

d.) }X,1,1,1{}YYY,Y{ 33210 =

Correct answer d)

19.4p

Assume a 4 to 1 multiplexer. Let’s note:{X0, X1, X2, X3}-inputs;

{S0, S1}-selection word;Y–output.

The truth table is presented below:


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If the selection word is {S0, S1}={0, 0}, the waveforms associated arepresented in figure:

a.)

X0

X1

X2

X3

Y

b.)

X0

X1

X2

X3

Y

c.)

X0

X1

X2

X3

Y

d.)

X0

X1

X2

X3

Y

Correct answer a)

20.

4p

Assume a 4 to 1 multiplexer. Let’s note:

{X0, X1, X2, X3}-inputs;{S0, S1}-selection word;

Y–output.The truth table is presented below:


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a.)

X0

X1

X2

X3

Y

b.)

X0

X1

X2

X3

Y

c.)

X0

X1

X2

X3

Y

d.)

X0

X1

X2

X3

Y

Correct answer b)

21.

4p





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a.)

X0

X1

X2

X3

Y

b.)

X0

X1

X2

X3

Y

c.)

X0

X1

X2

X3

Y

d.)

X0

X1

X2

X3

Y

Correct answer c)

22.

4p





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a.)

X0

X1

X2

X3

Y

b.)

X0

X1

X2

X3

Y

c.)

X0

X1

X2

X3

Y

d.)

X0

X1

X2

X3

Y

Correct answer d)

23.

4p





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The waveforms presented below are obtained if the selection wordis:

X0

X1

X2

X3

Y

a.) }0,0{}S,S{ 10 =

b.) }0,1{}S,S{ 10 =

c.) }1,0{}S,S{ 10 =

d.) }1,1{}S,S{ 10 =

Correct answer a.)

24.

4p



Y–output.



X0

X1

X2

X3

Y

a.) }0,0{}S,S{ 10 =

b.) }0,1{}S,S{ 10 =


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c.) }1,0{}S,S{ 10 =

d.) }1,1{}S,S{ 10 =

Correct answer b.)

25.

4p


{X0, X1, X2, X3}-inputs;

{S0, S1}-selection word;Y–output.



X0

X1

X2

X3

Y

a.) }0,0{}S,S{ 10 =

b.) }0,1{}S,S{ 10 =

c.) }1,0{}S,S{ 10 =

d.) }1,1{}S,S{ 10 =

Correct answer c.)

26.

4p



Y–output.


The waveforms presented below are obtained if the selection word


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is:

X0

X1

X2

X3

Y

a.) }0,0{}S,S{ 10 =

b.) }0,1{}S,S{ 10 =

c.) }1,0{}S,S{ 10 =

d.) }1,1{}S,S{ 10 =

Correct answer d.)


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51

Chapter 6

Decoders, Multiplexers and Demultiplexers

Problems

1.4p

Figure6.1 shows how to connect the BCD – seven segments decoderwith a seven segments display cell. LSB is “X0”. MSB is “X3”. If

{X0,X1,X2,X3}={0,1,1,0} then the display cell will show:

Figure 6.1

a.) 2

b.) 6

c.) 4

d.) 8

Correct answer b)

2.4p

Figure 6.1 shows how to connect the BCD - seven segments decoderwith a seven segments display cell. LSB is “X0”. MSB is “X3”. If{X0,X1,X2,X3}={0,1,0,0} then the display cell will show:

Figure 6.1 a.) 2

b.) 6

c.) 4d.) 8

Correct answer a)


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3.

4p

Figure 6.1 shows how to connect the BCD - seven segments decoder

with a seven segments display cell. LSB is “X0”. MSB is “X3”. If{X0,X1,X2,X3}={0,0,0,8} then the display cell will show:

Figure 6.1 a.) 2

b.) 6

c.) 4

d.) 8

Correct answer d)

4.

4p

The circuit diagram and the simplified truth table of a multiplixer

4 to 1 are presented below.

Let’s note:


Y–output

If {S0,S1}={0,0} and {X0,X1,X2,X3}={0,1,1,0}, then:

a.) Y=0

b.) Y=1

c.) 0/1 (unpredictable)

d.) according to the the previous state of the multiplexer

Correct answer a.)

5.4p

The circuit diagram and the simplified truth table of a multiplixer4 to 1 are presented below.


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Let’s note:{X0, X1, X2, X3}-inputs;{S0, S1}-selection word;

Y–output

If {S0,S1}={1,1} and {X0,X1,X2,X3}={0,1,1,0}, then:a.) Y=0

b.) Y=1

c.) 0/1 (unpredictable)d.) according to the the previous state of the multiplexer

Correct answer a)

8.

4p

The circuit diagram and the simplified truth table of a

demultiplixer 1 to 4 are presented below.

If {S0, S1}={1, 1} and X=0 thena.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}

b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}

c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}

d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}

Correct answer d)

9.

4p

The circuit diagram and the simplified truth table of a

demultiplixer 1 to 4 are presented below.


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If {S0, S1}={1, 1} and X=0 thena.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}

b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}

c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}

d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}

Correct answer d)

10.4p

The circuit diagram and the simplified truth table of ademultiplixer 1 to 4 are presented below.

If {S0, S1}={0, 0} and X=1 then

a.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}

b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}

c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}

d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}

Correct answer a.)

11.4p

The circuit diagram and the simplified truth table of ademultiplixer 1 to 4 are presented below.

If {S0, S1}={0, 0} and X=0 then

a.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}

b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}

c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}

d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}

Correct answer b.)

12.

4p

The truth table of a binary–seven segments decoder and a display

cell are presented below.


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Inputs Outputs

X3 X2 X1 X0 a b c d e f g

0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 0 0 1 1

If {X3, X2, X1, X0}={0, 0, 1, 1} then:

a.) {a, b, c, d, e, f, g}={1, 1, 1, 0, 0, 0, 1}

b.) {a, b, c, d, e, f, g}={1, 1, 0, 1, 0, 0, 1}c.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 0, 0, 1}

d.) {a, b, c, d, e, f, g}={1, 0, 1, 1, 0, 0, 1}

Correct answer c.)

13.4p

The truth table of a binary–seven segments decoder and a displaycell are presented below.

Inputs Outputs


0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 0 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 01 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1

If {X3, X2, X1, X0}={0, 1, 1, 0} then:

a.) {a, b, c, d, e, f, g}={1, 1, 1, 0, 0, 0, 1}

b.) {a, b, c, d, e, f, g}={1, 1, 0, 1, 0, 0, 1}

c.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 0, 0, 1}

d.) {a, b, c, d, e, f, g}={1, 0, 1, 1, 1, 1, 1}

Correct answer d.)

14.

4p

The truth table of a binary–seven segments decoder and a display

cell are presented below:


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Inputs Outputs


0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 0 0 1 1

If {X3, X2, X1, X0}={1, 0, 0, 1} then:

a.) {a, b, c, d, e, f, g}={1, 1, 1, 0, 0, 0, 1}

b.) {a, b, c, d, e, f, g}={0, 0, 1, 1, 1, 1, 1}c.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 0, 1, 1}

d.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 1, 1, 1}

Correct answer c.)

18.4p

The diagram circuit of a multiplexer-demultiplexer circuit ispresented below:

A

B

~G

YD0

D1

D2

D3

1Y0

4

1Y1

5

1Y2

6

1Y3

7

1A

2

1B

3

~1G

1

X0

X1

X2

X3

S0

S2

S1

Y2

S3

Y1

Y3

Y0

Let’s note:

X3, X2, X1, X0 input data;S1, S0 selection word for the multiplexerS3, S2 selection word for the demultiplexer

Y3, Y2, Y1, Y0 output data;

The circuit diagram and the truth table for the multiplexer are

In the same time the circuit diagram and the truth table for the


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demultiplexer are:

If the selection word for the multiplexer is {S1, S0}={1,0} and theselection word for the demultiplexer is {S3, S2}={0,1} then:

a.) Y0=X1b.) Y1=X1c.) Y2=X1

d.) Y3=X1 Correct answer c.)

19.

4p

The diagram circuit of a multiplexer-demultiplexer circuit is

presented below:

A

B

~G

YD0

D1

D2

D3

1Y0

4

1Y1

5

1Y2

6

1Y3

7

1A

2

1B

3

~1G

1

X0

X1

X2

X3

S0

S2

S1

Y2

S3

Y1

Y3

Y0

Let’s note:X3, X2, X1, X0 input data;

S1, S0 selection word for the multiplexer

S3, S2 selection word for the demultiplexerY3, Y2, Y1, Y0 output data;


In the same time the circuit diagram and the truth table for thedemultiplexer are:


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If the selection word for the multiplexer is {S1, S0}={1,1} and the

selection word for the demultiplexer is {S3, S2}={0,0} then:a.) Y0=X3b.) Y1=X3c.) Y2=X3

d.) Y3=X3

Correct answer a.)

20.4p


A

B

~G

YD0

D1

D2

D3

1Y0

4

1Y1

5

1Y2

6

1Y3

7

1A

2

1B

3

~1G

1

X0

X1

X2

X3

S0

S2

S1

Y2

S3

Y1

Y3

Y0



S3, S2 selection word for the demultiplexer




demultiplexer are:


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d.) Y3=X2

Correct answer b.)

20.4p


A

B

~G

YD0

D1

D2

D3

1Y0

4

1Y1

5

1Y2

6

1Y3

7

1A

2

1B

3

~1G

1

X0

X1

X2

X3

S0

S2

S1

Y2

S3

Y1

Y3

Y0



S3, S2 selection word for the demultiplexer




demultiplexer are:


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d.) Y3=X2

Correct answer d.)


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Chapter 7

Memories

1.1p

ROM Memories

a.) are storage devices that can be written into once (as a general

rule) and the the information in ROMs is perserved after the

supply voltage is switched ofb.) are storage devices that can be written every time is needed and

the the information in ROMs is not perserved after the supply

voltage is switched of

c.) are storage devices that can be written into once (as a generalrule) and the the information in ROMs is not perserved after the

supply voltage is switched of

d.) are storage devices that can be written every time is needed andall stored information is lost when the supply is switched of

Correct answer a.)

2.

1p

RAM Memories

a.) are storage devices that can be written into once (as a general

rule) and the the information in ROMs is perserved after the


b.) are storage devices that can be written every time is needed and

the the information in ROMs is not perserved after the supply

voltage is switched of

c.) are storage devices that can be written into once (as a generalrule) and the the information in ROMs is not perserved after the


d.) are storage devices that can be written every time is needed andall stored information is lost when the supply is switched of

Correct answer b.)

3.

1p

The symbol of a standard memory is presented below. The so

called “Address Bus”


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a.) set of data that transmit information needed to access a memorylocation;

b.) set of data that is contained in a memory location;

c.) set of data which control the operation of the memory chip

d.) set of data that is contained in a memory location and set of datawhich control the operation of the memory chip

Correct answer a.)

4.

1p


called “Data Bus”

a.) set of data that transmit information needed to access a memory

location;b.) set of data that is contained in a memory location;



Correct answer b.)

5.

1p


called “Control Bus”


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a.) set of data that transmit information needed to access a memorylocation;

b.) set of data that is contained in a memory location;



Correct answer c.)

6.

3p

A memory that can be written - once - with a particular device is a:

a.) PROM type

b.) EPROM type

c.) EAROM type

d.) EEPROM type

Correct answer a.)

7.

3p

A memory that can be erased but the writing is performed using a s

particular device is a:

a.) PROM typeb.) EPROM type

c.) EAROM type

d.) EEPROM type

Correct answer b.)

83p

A memory whose contents can be changed only one bit is a:

a.) PROM type

b.) EPROM type

c.) EAROM type

d.) EEPROM type

Correct answer c.)

9 A memory that can be erased (not just one bit but whole sections or


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3p fully) or rewritten without requiring their removal from thecomputer's memory is:

a.) PROM type

b.) EPROM type

c.) EAROM type

d.) EEPROM type

Correct answer d.)


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2. digital electronics combinational tests .pdf

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