2-channel 500 mhz a/d, ddc, duc, 2-channel 800 mhz d/a and ... · entire fpga design as a block...

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Pentek, Inc.

Model 54851 2-Channel 500 MHz A/D, DDC, DUC, 2-Channel 800 MHzD/A and Kintex UltraScale FPGA - 3U VPX

General InformationModel 54851 is a member of the JadeTM

family of high-performance 3U VPX boards.The Jade architecture embodies a new stream-lined approach to FPGA-based boards,simplifying the design to reduce power andcost, while still providing some of the high-est-performance FPGA resources availabletoday. Designed to work with Pentek’s newNavigatorTM Design Suite of tools, the com-bination of Jade and Navigator offers usersan efficient path to developing and deployingFPGA-based data acquisition and processing.

The 54851 is a 2-channel, high-speeddata converter with programmable DDCs(digital downconverters). It is suitable forconnection to HF or IF ports of a communi-cations or radar system. Its built-in datacapture feature offers an ideal turnkey solu-tion as well as a platform for developingand deploying custom FPGA-processing IP.

It includes two A/Ds, a complete multi-board clock and sync section, a large DDR4memory, two DDCs, one DUC and twoD/As. In addition to supporting PCI Ex-press Gen. 3 as a native interface, the Model54851 includes optional high-bandwidthconnections to the Kintex UltraScale FPGA forcustom digital I/O. The 54851 includes op-tional support for VITA 66.5, 67.2 and 67.3Cfor additional signal routing flexibilitythrough the VPX blackplane.

The Jade ArchitectureEvolved from the proven designs of the

Pentek Cobalt and Onyx families, Jade raisesthe processing performance with the newflagship family of Kintex UltraScale FPGAsfrom Xilinx. As the central feature of theboard architecture, the FPGA has access toall data and control paths, enabling fac-tory-installed functions including datamultiplexing, channel selection, data pack-ing, gating, triggering and memorycontrol. The Jade architecture organizes theFPGA as a container for data-processing ap-plications where each function exists as anintellectual property (IP) module.

Each member of the Jade family is deliveredwith factory-installed applications ideallymatched to the board’s analog interfaces.

The 54851 factory-installed functionsinclude two A/D acquisition and a wave-form playback IP module for simplifyingdata capture and playback, and data trans-fer between the board and a host computer.

Additional IP includes: a powerful, pro-grammable DDC IP core; an IP module forDDR4 SDRAM memory; a controller for alldata clocking and synchronization functions;two test signal generators; a programmableinterpolator, and a PCIe interface. These com-plete the factory-installed functions and enablethe 54851 to operate as a complete turnkeysolution for many applications, thereby sav-ing the cost and time of custom IPdevelopment.

Features■ Complete radar and

software radio interfacesolution

■ Supports Xilinx KintexUltraScale FPGAs

■ Compatible with severalVITA standards including:VITA 66.5, VITA 67.2 andVITA 67.3C

■ Supports VITA-49.2 VITARadio Transport standard

■ Two 500 MHz 12-bit A/Ds■ Two multiband DDCs (digital

downconverters)■ One DUC (digital upconverter)

■ Two 800 MHz 16-bit D/As■ 5 GB of DDR4 SDRAM■ Sample clock synchronization

to an external systemreference

■ LVPECL clock/sync bus formultimodule synchronization

■ PCI Express (Gen. 1, 2 & 3)interface up to x8

■ Optional LVDS and gigabitserial connections to theFPGA for custom I/O

■ Optional 400 MHz 14-bit A/Ds■ Ruggedized and

conduction-cooled versionsavailable

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Model 54851 Commercial (left)and rugged version

Standard front panel and VPX-P2 connections shown

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Pentek, Inc.


Extendable IP DesignFor applications that require specialized

functions, users can install their own customIP for data processing. The Pentek Naviga-tor FPGA Design Kits include the board’sentire FPGA design as a block diagram thatcan be edited in Xilinx’s Vivado tool suite.

In addition to the block diagrams, all sourcecode and complete IP core documentationis included. Developers can integrate theirown IP along with the Pentek factory-installedfunctions or use the Navigator kit to completelyreplace the Pentek IP with their own. ➤

Xilinx Kintex UltraScale FPGADepending on the requirements of the

processing task, the Kintex Ultrascale canbe selected from a range of FPGAs spanningthe KU035 through KU115.

The KU115 features 5520 DSP48E2 slicesand is ideal for modulation/demodulation,encoding/decoding, encryption/decryption,and channelization of the signals betweentransmission and reception. For applicationsnot requiring large DSP resources or logic,a lower-cost FPGA can be installed.

Option -104 provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O. Thisoption can not be combined with option111 or 112.

Option -105 provides one 8X gigabit linkbetween the FPGA and the VPX P1 connec-tor to support serial protocols. This link is4X when option 105 is combined with op-tion 110.

A/D Converter StageThe front end accepts two analog HF

or IF inputs on front panel SSMC connec-tors with transformer coupling into twoTexas Instruments ADS5463 500 MHz, 12-bit A/D converters.

Optionally, a Texas Instruments ADS5474400 MHz, 14-bit A/D may be factory-installedinstead of the ADS5463.

The digital outputs are delivered intothe Kintex FPGA for signal processing,data capture and for routing to othermodule resources.

Digital Upconverter and D/A StageA TI DAC5688 DUC (digital upconverter)

and D/A accepts a baseband real or complexdata stream from the FPGA and providesthat input to the upconvert, interpolate anddual D/A stages.

When operating as a DUC, it interpo-lates and translates real or complex basebandinput signals to any IF center frequency upto 360 MHz. It delivers real or quadrature(I+Q) analog outputs to the dual 16-bitD/A converter. Analog output is through apair of front panel SSMC connectors.

Option -111 or -112 VPX-P2 connections shown


Pentek, Inc.


If translation is disabled, the DAC5688acts as a dual interpolating 16-bit D/A withoutput sampling rates up to 800 MHz. Inboth modes the DAC5688 provides interpo-lation factors of 2x, 4x and 8x. In addition tothe DAC5688, an FPGA-based interpolatorcore provides additional interpolation from2x to 32,768x. The two interpolators can becombined to create a total range from 2x to262,144x.

Clocking and SynchronizationTwo internal timing buses provide either a

single clock or two different clock rates to theA/D and D/A signal paths.

Each timing bus includes a clock, sync anda gate or trigger signal. An on-board clockgenerator receives an external sample clockfrom the front panel SSMC connector. Thisclock can be used directly for either the A/Dor D/A sections or can be divided by a built-inclock synthesizer circuit to provide differentA/D and D/A clocks. In an alternate mode,the sample clock can be sourced from an on-board programmable VCXO. In this mode,the front panel SSMC connector can be usedto provide a 10 MHz reference clock for syn-chronizing the internal oscillator.

A front panel 26-pin LVPECL Clock/Syncconnector allows multiple boards to be syn-chronized. In the slave mode, it acceptsLVPECL inputs that drive the clock, sync andgate signals. In the master mode, the LVPECLbus can drive the timing signals for synchro-nizing multiple boards.

Multiple 54851’s can be driven from theLVPECL bus master, supporting synchronoussampling and sync functions across all con-nected boards.

Memory ResourcesThe 54851 architecture supports a 5 GB

bank of DDR4 SDRAM memory. User-installed IP along with the Pentek-suppliedDDR4 controller core within the FPGA cantake advantage of the memory for customapplications.

PCI Express InterfaceThe Model 54851 includes an industry-

standard interface fully compliant with PCIExpress Gen. 1, 2 and 3 bus specifications.Supporting PCIe links up to x8, the inter-face includes multiple DMA controllers forefficient transfers to and from the board.

VPX-P2 Interface OptionsWhen purchased with option 110, the

Model 54851 supports the emerging VITA66.5 standard and provides four opticalduplex lanes to a mating VITA 66.5backplane connector. With the instalationof a serial protocol like 10 or 40 GigabitEhternet in the FPGA, the VITA 66.5 inter-face enables high bandwidthcommunications between boards or chas-sis independent of the PCIe interface.

Options 111 and 112 provide analogsignal routing through the VPX backplaneBoth options replace front panel connec-tors for RF In, RF Out, Sample Clock/Reference Clock In and Gate/Trigger/Sync/PPS In with coax signals which passthrough the backplane for connections toother boards or chassis. Option 111 sicompatible with VITA 67.2 and option 112is compatible with VITA 67.3C.

A/D Acquisition IP ModulesThe 54851 features two A/D Acquisi-

tion IP Modules for easily capturing andmoving data. Each module can receivedata from either of the two A/Ds, or atest signal generator.

Each acquisition module has a DMAengine for easily moving A/D datathrough the PCIeinterface.

These powerful linked-list DMA en-gines are capable of a unique AcquisitionGate Driven mode. In this mode, thelength of a transfer performed by a linkdefinition need not be known prior todata acquisition; rather, it is governed bythe length of the acquisition gate. Thisis extremely useful in applications wherean external gate drives acquisition andthe exact length of that gate is not knownor is likely to vary.

For each transfer, the DMA engine canautomatically construct metadata packetscontaining A/D channel ID, a sample-accurate time stamp and data lengthinformation. These actions simplify thehost processor’s job of identifying andexecuting on the data.

DDC IP CoresWithin each A/D Acquisition IP Module

is a powerful DDC IP core. Because ofthe flexible input routing of the A/D Ac-quisition IP Modules, many differentconfigurations can be achieved includingone A/D driving both DDCs or each of thetwo A/Ds driving its own DDC. ➤


Pentek, Inc.


➤ Each DDC has an independent 32-bittuning frequency setting that ranges fromDC to ƒs, where ƒs is the A/D samplingfrequency. Each DDC can have its ownunique decimation setting, supporting asmany as two different output band-widths for the board. Decimations can beprogrammed from 2 to 65,536 providing awide range to satisfy most applications.

The decimating filter for each DDCaccepts a unique set of user-supplied 16-bitcoefficients. The 80% default filters deliveran output bandwidth of 0.8*ƒs/N, whereN is the decimation setting. The rejectionof adjacent-band components withinthe 80% output bandwidth is better than 100dB. Each DDC delivers a complex outputstream consisting of 24-bit I + 24-bit Qor16-bit I + 16-bit Q samples at a rate ofƒs/N.

D/A Waveform Playback IP ModuleThe Model 54851 factory-installed

functions include a sophisticated D/AWaveform Playback IP module. It allowsusers to easily play back to the dual D/Aswaveforms stored in either on-boardmemory or off-board host memory.

VITA 49.2 Radio Transport StandardVITA 49.2 is a data transport protocol

for conveying digitized signal informa-tion among signal acquisition/generation

and processing elements in a communica-tion, radar or similar system.

The Model 52851 implements the VITA49 packet format for the ADC/DDC databeing transferred to the host memory viaDMA.

VITA 49.2 packet elements alwayssupported are:

- Signal Data Packet Type- Stream Identifier- Integer Seconds Timestamp- Fractions Seconds Timestamp- Trailer

Programmable elements are:- Packet Size- Stream Identifier- Trailer

The Timestamp is automatically insertedfrom the metadata engine. After initializa-tion an externally applied 1 PPS pulse willincrement the Integer SecondsTimestamp. A division of the sample clock will incrementthe fractional seconds timestamp and thiscount is reset by the 1 PPS pulse.

VITA 49 packets sent via DMA to theDAC/DUC for output will have the header,stream ID, timestamp and trailer re-moved leaving only the signal data to betransmitted.


Pentek, Inc.


Ordering InformationModel Description

54851 2-Channel 500 MHz A/Dwith DDCs, DUC with2-Channel 800 MHz D/A,and Kintex UltraScaleFPGA - 3U VPX

Options:

-014 400 MHz, 14-bit A/Ds

-084 XCKU060-2 FPGA

-087 XCKU115-2 FPGA

-104 LVDS FPGA I/O throughVPX P2 connector

-105 Gigabit serial FPGA I/Othrough VPX P1 connector

-110 VITA 66.5 opticalinterface

-111 VITA 67.2 RF interface

-112 VITA 67.3C RF interface

- 249 VITA 49-2 support

-702 Air cooled, Level L2

-763 Conduction cooled,Level L3

Contact Pentek for completespecifications of rugged andconduction-cooled versions

SpecificationsFront Panel Analog Signal Inputs

Input Type: Transformer-coupled, frontpanel female SSMC connectorsTransformer Type: Coil CraftWBC4-6TLBFull Scale Input: +5 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz

A/D Converters (standard)Type: Texas Instruments ADS5463Sampling Rate: 20 MHz to 500 MHzResolution: 12 bits

A/D Converters (option -014)Type: Texas Instruments ADS5474Sampling Rate: 20 MHz to 400 MHzResolution: 14 bits

Digital DownconvertersQuantity: Two channelsDecimation Range: 2x to 65,536x inthree stages of 2x to 32x and one fixedstage of 2xLO Tuning Freq. Resolution: 32 bits,0 to ƒsLO SFDR: >120 dBPhase Offset Resolution: 32 bits,0 to 360 degreesFIR Filter: 16-bit coefficients, 24-bit output,with user programmable coefficientsDefault Filter Set: 80% bandwidth, <0.3dB passband ripple, >100 dB stopbandattenuation

D/A ConvertersType: Texas Instruments DAC5688Input Data Rate: 250 MHz max.Output IF: DC to 400 MHz max.Output Signal: 2-channel real or1-channel with frequency translationOutput Sampling Rate: 800 MHz max.with 2x, 4x or 8x interpolationResolution: 16 bits

Digital Interpolator CoreInterpolation Range: 2x to 32,768x inone stage of 2x to 256x and one stage of2x to 128x

Total Interpolation Range (D/A and inter-polator core combined): 2x to 262,144x

Front Panel Analog Signal OutputsOutput: Transformer-coupled, frontpanel female SSMC connectorsTransformer: Coil Craft WBC4-6TLBFull Scale Output: +4 dBm into 50 ohms3 dB Passband: 300 kHz to 700 MHz

Sample Clock Sources: On-board clocksynthesizer generates two clocks: oneA/D clock and one D/A clock

Clock SynthesizerClock Source: Selectable from on-boardprogrammable VCXO (10 to 810 MHz),front panel external clock or LVPECLtiming bus

Synchronization: VCXO can be lockedto an external 4 to 180 MHz PLL systemreference, typically 10 MHzClock Dividers: External clock or VCXOcan be divided by 1, 2, 4, 8, or 16, indepen-dently for the A/D clock and D/A clock

External ClockType: Front panel female SSMC connector,sine wave, 0 to +10 dBm, AC-coupled, 50ohms, accepts 10 to 800 MHz divider inputclock or PLL system reference

Timing Bus: 26-pin connector LVPECL busincludes, clock/sync/gate/PPS inputsand outputs; TTL signal for gate/triggerand sync/PPS inputs

Field Programmable Gate ArrayStandard: Xilinx Kintex UltraScaleXCKU035-2Option -084: XCKU060-2Option -087: XCKU115-2

Custom I/OOption -104: provides 20 pairs of LVDSconnections between the FPGA and theVPX P2 connector for custom I/O (notavailable with options 111 and 112)Option -105: provide one 8X gigabit linkbetween the FPGA and the VPX P1 con-nector to support serial protocols (gigabitlink is 4X when combined with option110)Option -110: VITA 66.5 interface pro-vides optical 4X duplex lanesOption -111: VITA 67.2: RF In, RF Out,Sample Clock/Reference Clock In andGate/Trigger/Sync/PPS InOption -112: VITA 67.3C: RF In, RF Out,Sample Clock/Reference Clock In andGate/Trigger/Sync/PPS In

MemoryType: DDR4 SDRAMSize: 5 GBSpeed: 1200 MHz (2400 MHz DDR)

PCI-Express InterfacePCI Express Bus: Gen. 1, 2 or 3: x4

EnvironmentalStandard: L0 (air cooled)

Operating Temp: 0° to 50° CStorage Temp: –20° to 90° CRelative Humidity: 0 to 95%, non-condensing

Option -702: L2 (air cooled)Operating Temp: –20° to 65° CStorage Temp: –40° to 100° CRelative Humidity: 0 to 95%, non-condensing

Option -763: L3 (conduction cooled)Operating Temp: –40° to 70° CStorage Temp: –50° to 100° CRelative Humidity: 0 to 95%, non-condensing

Size: 3U VPX board 3.937 in x 6.717 in(100.00 mm x 170.61 mm)

The SPARK DevelopmentSystems are fully-integratedplatforms for Pentek board-levelproducts. They were created tosave engineers and system inte-grators the time and expenseassociated with building andtesting a development system.Each SPARK system is deliveredwith the Pentek board(s) andrequired software installed. Thesystem is equipped with sufficientpower and cooling to ensureoptimum performance.

2-channel 500 mhz a/d, ddc, duc, 2-channel 800 mhz d/a and ... · entire fpga design as a block...

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